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Searched refs:gpu_write (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/msm/adreno/
H A Da3xx_gpu.c123 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
124 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010); in a3xx_hw_init()
125 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
126 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
127 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
128 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
129 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010); in a3xx_hw_init()
131 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff); in a3xx_hw_init()
133 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030); in a3xx_hw_init()
135 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); in a3xx_hw_init()
[all …]
H A Da4xx_gpu.c81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
87 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
89 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_SP(i), 0x22222222); in a4xx_enable_hwcg()
91 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_SP(i), 0x00222222); in a4xx_enable_hwcg()
93 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_SP(i), 0x00000104); in a4xx_enable_hwcg()
95 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_SP(i), 0x00000081); in a4xx_enable_hwcg()
96 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_UCHE, 0x22222222); in a4xx_enable_hwcg()
97 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_UCHE, 0x02222222); in a4xx_enable_hwcg()
[all …]
H A Da2xx_gpu.c121 gpu_write(gpu, REG_AXXX_CP_ME_CNTL, AXXX_CP_ME_CNTL_HALT); in a2xx_hw_init()
123 gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0xfffffffe); in a2xx_hw_init()
124 gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0xffffffff); in a2xx_hw_init()
127 gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0xffffffff); in a2xx_hw_init()
129 gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0x00000000); in a2xx_hw_init()
132 gpu_write(gpu, REG_A2XX_SQ_FLOW_CONTROL, 0x18000000); in a2xx_hw_init()
135 gpu_write(gpu, REG_A2XX_RBBM_CNTL, 0x00004442); in a2xx_hw_init()
138 gpu_write(gpu, REG_A2XX_MH_MMU_MPU_BASE, 0x00000000); in a2xx_hw_init()
139 gpu_write(gpu, REG_A2XX_MH_MMU_MPU_END, 0xfffff000); in a2xx_hw_init()
141 gpu_write(gpu, REG_A2XX_MH_MMU_CONFIG, A2XX_MH_MMU_CONFIG_MMU_ENABLE | in a2xx_hw_init()
[all …]
H A Da5xx_gpu.c63 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
465 gpu_write(gpu, regs[i].offset, in a5xx_set_hwcg()
469 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0); in a5xx_set_hwcg()
470 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_HYST_GPMU, state ? 0x00000004 : 0); in a5xx_set_hwcg()
473 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0); in a5xx_set_hwcg()
474 gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180); in a5xx_set_hwcg()
702 gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); in a5xx_hw_init()
706 gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); in a5xx_hw_init()
709 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); in a5xx_hw_init()
712 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001); in a5xx_hw_init()
[all …]
H A Da8xx_gpu.c30 gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val); in a8xx_aperture_slice_set()
66 gpu_write(gpu, offset, data); in a8xx_write_pipe()
176 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); in a8xx_flush()
194 gpu_write(gpu, REG_A8XX_RBBM_CGC_0_PC, 0x00000702); in a8xx_set_hwcg()
203 gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 1); in a8xx_set_hwcg()
204 gpu_write(gpu, REG_A8XX_RBBM_CGC_GLOBAL_LOAD_CMD, !!state); in a8xx_set_hwcg()
207 gpu_write(gpu, REG_A8XX_RBBM_CGC_P2S_TRIG_CMD, 1); in a8xx_set_hwcg()
215 gpu_write(gpu, REG_A8XX_RBBM_CLOCK_CNTL_GLOBAL, 0); in a8xx_set_hwcg()
249 gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); in a8xx_set_cp_protect()
328 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, in a8xx_set_ubwc_config()
[all …]
H A Da6xx_gpu.c41 gpu_write(gpu, offset, value); in fence_status_check()
57 gpu_write(gpu, offset, value); in fenced_write()
73 gpu_write(gpu, offset, value); in fenced_write()
669 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); in a6xx_set_hwcg()
670 gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); in a6xx_set_hwcg()
673 gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); in a6xx_set_hwcg()
681 gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); in a6xx_set_hwcg()
698 gpu_write(gpu, reg->offset, state ? reg->value : 0); in a6xx_set_hwcg()
704 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); in a6xx_set_hwcg()
718 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, in a6xx_set_cp_protect()
[all …]
H A Da6xx_gpu_state.c163 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
168 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
187 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg); in debugbus_read()
188 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg); in debugbus_read()
189 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_C, reg); in debugbus_read()
190 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_D, reg); in debugbus_read()
241 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
244 gpu_write(gpu, ctrl1, i); in vbif_debugbus_read()
278 gpu_write(gpu, REG_A6XX_VBIF_CLKON, in a6xx_get_vbif_debugbus_block()
282 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS1_CTRL0, 0); in a6xx_get_vbif_debugbus_block()
[all …]
H A Da2xx_gpummu.c56 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_map()
71 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_unmap()
H A Da5xx_preempt.c52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
168 gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1); in a5xx_preempt_trigger()
H A Da6xx_preempt.c230 gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0x1); in a6xx_preempt_hw_init()
H A Da6xx_gmu.c997 gpu_write(gpu, gbif_cx[i].offset, gbif_cx[i].value); in a6xx_gmu_fw_start()
1000 gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000); in a6xx_gmu_fw_start()
H A Dadreno_gpu.c734 gpu_write(gpu, reg, wptr); in adreno_flush()
/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_iommu.c100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
110 gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
111 gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
112 gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
113 gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
H A Detnaviv_iommu_v2.c186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
203 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
205 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
207 gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
209 gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
211 gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
213 gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG, in etnaviv_iommuv2_restore_sec()
228 gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
H A Detnaviv_sched.c59 gpu_write(gpu, VIVS_MC_PROFILE_CONFIG0, in etnaviv_sched_timedout_job()
H A Detnaviv_gpu.h170 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_device.h418 gpu_write(ptdev, __reg_prefix ## _INT_MASK, 0); \
439 gpu_write(ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \
447 gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, 0); \
456 gpu_write(pirq->ptdev, __reg_prefix ## _INT_CLEAR, mask); \
457 gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, mask); \
477 static inline void gpu_write(struct panthor_device *ptdev, u32 reg, u32 data) in gpu_write() function
494 gpu_write(ptdev, reg, lower_32_bits(data)); in gpu_write64()
495 gpu_write(ptdev, reg + 4, upper_32_bits(data)); in gpu_write64()
H A Dpanthor_gpu.c53 gpu_write(ptdev, GPU_COHERENCY_PROTOCOL, in panthor_gpu_coherency_set()
72 gpu_write(ptdev, GPU_ASN_HASH(i), data->asn_hash[i]); in panthor_gpu_l2_config_set()
76 gpu_write(ptdev, GPU_L2_CONFIG, l2_config); in panthor_gpu_l2_config_set()
81 gpu_write(ptdev, GPU_INT_CLEAR, status); in panthor_gpu_irq_handler()
302 gpu_write(ptdev, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other)); in panthor_gpu_flush_caches()
341 gpu_write(ptdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); in panthor_gpu_soft_reset()
342 gpu_write(ptdev, GPU_CMD, GPU_SOFT_RESET); in panthor_gpu_soft_reset()
H A Dpanthor_pwr.c58 gpu_write(ptdev, PWR_INT_CLEAR, status); in panthor_pwr_irq_handler()
79 gpu_write(ptdev, PWR_COMMAND, command); in panthor_pwr_write_command()
99 gpu_write(ptdev, PWR_INT_CLEAR, PWR_IRQ_RESET_COMPLETED); in panthor_pwr_reset()
H A Dpanthor_fw.c1053 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_init_global_iface()
1062 gpu_write(ptdev, JOB_INT_CLEAR, status); in panthor_job_irq_handler()
1083 gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_AUTO); in panthor_fw_start()
1114 gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_DISABLE); in panthor_fw_stop()
1142 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_halt_mcu()
1405 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_ring_csg_doorbells()
1420 gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1); in panthor_fw_ping_work()
H A Dpanthor_mmu.c520 gpu_write(ptdev, AS_COMMAND(as_nr), cmd); in write_cmd()
786 gpu_write(ptdev, MMU_INT_CLEAR, panthor_mmu_as_fault_mask(ptdev, as)); in panthor_vm_active()
789 gpu_write(ptdev, MMU_INT_MASK, ~ptdev->mmu->as.faulty_mask); in panthor_vm_active()
1693 gpu_write(ptdev, MMU_INT_CLEAR, mask); in panthor_mmu_irq_handler()
H A Dpanthor_sched.c3346 gpu_write(ptdev, CSF_DOORBELL(queue->doorbell_id), 1); in queue_run_job()
/linux/drivers/gpu/drm/msm/
H A Dmsm_gpu.h595 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) in gpu_write() function