Home
last modified time | relevance | path

Searched refs:gpu_write (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_iommu.c100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
110 gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
111 gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
112 gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
113 gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
H A Detnaviv_iommu_v2.c186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
203 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
205 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
207 gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
209 gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
211 gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
213 gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG, in etnaviv_iommuv2_restore_sec()
228 gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
H A Detnaviv_gpu.c503 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
505 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
562 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
565 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
570 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
578 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
582 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
605 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
697 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); in etnaviv_gpu_start_fe()
698 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
[all …]
H A Detnaviv_gpu.h170 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_device.h526 gpu_write(pirq->iomem, INT_MASK, 0); \
561 gpu_write(pirq->iomem, INT_MASK, pirq->mask); \
571 gpu_write(pirq->iomem, INT_MASK, 0); \
582 gpu_write(pirq->iomem, INT_CLEAR, pirq->mask); \
583 gpu_write(pirq->iomem, INT_MASK, pirq->mask); \
596 gpu_write(pirq->iomem, INT_MASK, 0); \
616 gpu_write(pirq->iomem, INT_MASK, pirq->mask); \
630 gpu_write(pirq->iomem, INT_MASK, pirq->mask); \
635 static inline void gpu_write(void __iomem *iomem, u32 reg, u32 data) in gpu_write() function
652 gpu_write(iomem, reg, lower_32_bits(data)); in gpu_write64()
[all …]
H A Dpanthor_gpu.c62 gpu_write(ptdev->gpu->iomem, GPU_COHERENCY_PROTOCOL, in panthor_gpu_coherency_set()
82 gpu_write(gpu->iomem, GPU_ASN_HASH(i), data->asn_hash[i]); in panthor_gpu_l2_config_set()
86 gpu_write(gpu->iomem, GPU_L2_CONFIG, l2_config); in panthor_gpu_l2_config_set()
93 gpu_write(gpu->irq.iomem, INT_CLEAR, status); in panthor_gpu_irq_handler()
342 gpu_write(gpu->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other)); in panthor_gpu_flush_caches()
387 gpu_write(gpu->irq.iomem, INT_CLEAR, GPU_IRQ_RESET_COMPLETED); in panthor_gpu_soft_reset()
388 gpu_write(gpu->iomem, GPU_CMD, GPU_SOFT_RESET); in panthor_gpu_soft_reset()
H A Dpanthor_pwr.c64 gpu_write(pwr->irq.iomem, INT_CLEAR, status); in panthor_pwr_irq_handler()
87 gpu_write(pwr->iomem, PWR_COMMAND, command); in panthor_pwr_write_command()
111 gpu_write(pwr->irq.iomem, INT_CLEAR, PWR_IRQ_RESET_COMPLETED); in panthor_pwr_reset()
H A Dpanthor_fw.c1098 gpu_write(ptdev->fw->irq.iomem, INT_CLEAR, status); in panthor_job_irq_handler()
1127 gpu_write(fw->iomem, MCU_CONTROL, MCU_CONTROL_AUTO); in panthor_fw_start()
1159 gpu_write(fw->iomem, MCU_CONTROL, MCU_CONTROL_DISABLE); in panthor_fw_stop()
1431 gpu_write(ptdev->iomem, CSF_DOORBELL(doorbell_id), 1); in panthor_fw_ring_doorbell()
H A Dpanthor_mmu.c548 gpu_write(ptdev->mmu->iomem, AS_COMMAND(as_nr), cmd); in as_send_cmd_and_wait()
794 gpu_write(ptdev->mmu->irq.iomem, INT_CLEAR, fault_mask); in panthor_vm_active()
1834 gpu_write(mmu->irq.iomem, INT_CLEAR, mask); in panthor_mmu_irq_handler()
/linux/drivers/gpu/drm/msm/adreno/
H A Da2xx_gpummu.c56 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_map()
71 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_unmap()
H A Da5xx_preempt.c52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
168 gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1); in a5xx_preempt_trigger()
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Dhuge_pages.c1055 static int gpu_write(struct intel_context *ce, in gpu_write() function
1175 err = gpu_write(ce, vma, dword, val); in __igt_write_huge()
1891 err = gpu_write(ce, vma, n++, 0xdeadbeaf); in igt_shrink_thp()