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Searched refs:gpu_read (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/msm/adreno/
H A Da8xx_gpu.c79 val = gpu_read(gpu, offset); in a8xx_read_pipe_slice()
140 if (gpu_read(gpu, REG_A8XX_RBBM_STATUS) & in _a8xx_check_idle()
144 return !(gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS) & in _a8xx_check_idle()
158 gpu_read(gpu, REG_A8XX_RBBM_STATUS), in a8xx_idle()
159 gpu_read(gpu, REG_A8XX_RBBM_INT_0_STATUS), in a8xx_idle()
160 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a8xx_idle()
161 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a8xx_idle()
419 *dest++ = gpu_read(gpu, reglist->regs[i]); in a8xx_patch_pwrup_reglist()
429 *dest++ = gpu_read(gpu, reglist->regs[i]); in a8xx_patch_pwrup_reglist()
641 gpu_read(gpu, REG_A6XX_GBIF_HALT); in hw_init()
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H A Da5xx_gpu.c1019 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i))); in a5xx_recover()
1026 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover()
1066 if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY) in _a5xx_check_idle()
1073 return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) & in _a5xx_check_idle()
1094 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle()
1095 gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS), in a5xx_idle()
1096 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle()
1097 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle()
1110 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(4)), in a5xx_fault_handler()
1111 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(5)), in a5xx_fault_handler()
[all …]
H A Da6xx_gpu.c128 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
132 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
145 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
146 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle()
147 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_idle()
148 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a6xx_idle()
703 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); in a6xx_set_hwcg()
833 *dest++ = gpu_read(gpu, reglist->regs[i]); in a7xx_patch_pwrup_reglist()
842 *dest++ = gpu_read(gpu, reglist->regs[i]); in a7xx_patch_pwrup_reglist()
870 *dest++ = gpu_read(gpu, dyn_pwrup_reglist->regs[i].offset); in a7xx_patch_pwrup_reglist()
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H A Da3xx_gpu.c370 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a3xx_recover()
378 gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); in a3xx_recover()
404 if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & in a3xx_idle()
419 status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS); in a3xx_irq()
473 gpu_read(gpu, REG_A3XX_RBBM_STATUS)); in a3xx_dump()
486 state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS); in a3xx_gpu_state_get()
508 ret = spin_until(((ack = gpu_read(gpu, REG_A3XX_VBIF_XIN_HALT_CTRL1)) & in a3xx_vbif_halt()
535 ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); in a3xx_get_rptr()
H A Da6xx_gpu_state.c197 data[0] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2); in debugbus_read()
198 data[1] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1); in debugbus_read()
247 data[i] = gpu_read(gpu, REG_A6XX_VBIF_TEST_BUS_OUT); in vbif_debugbus_read()
277 clk = gpu_read(gpu, REG_A6XX_VBIF_CLKON); in a6xx_get_vbif_debugbus_block()
1171 obj->data[index++] = gpu_read(gpu, in a6xx_get_ahb_gpu_registers()
1196 obj->data[index++] = gpu_read(gpu, regs[i] + j); in a7xx_get_ahb_gpu_registers()
1478 return gpu_read(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2) >> 14; in a6xx_get_cp_roq_size()
1490 return 4 * (gpu_read(gpu, REG_A6XX_CP_SQE_UCODE_DBG_DATA) >> 20); in a7xx_get_cp_roq_size()
1516 obj->data[i] = gpu_read(gpu, indexed->data); in a6xx_get_indexed_regs()
1538 val = gpu_read(gpu, REG_A6XX_CP_CHICKEN_DBG); in a6xx_get_indexed_registers()
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H A Da5xx_gpu.h146 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
H A Da5xx_preempt.c194 status = gpu_read(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL); in a5xx_preempt_irq()
H A Dadreno_gpu.c823 state->registers[pos++] = gpu_read(gpu, addr); in adreno_gpu_state_get()
1082 uint32_t val = gpu_read(gpu, addr); in adreno_dump()
/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c217 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
218 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
219 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
220 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
364 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
372 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
374 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
375 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
376 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); in etnaviv_hw_identify()
383 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); in etnaviv_hw_identify()
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H A Detnaviv_iommu_v2.c172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
196 if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE) in etnaviv_iommuv2_restore_sec()
H A Detnaviv_dump.c94 reg->value = cpu_to_le32(gpu_read(gpu, read_addr)); in etnaviv_core_dump_registers()
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_device.h522 if (!gpu_read(pirq->iomem, INT_STAT)) { \
548 u32 status = gpu_read(pirq->iomem, INT_RAWSTAT) & pirq->mask; \
643 static inline u32 gpu_read(void __iomem *iomem, u32 reg) in gpu_read() function
661 return (gpu_read(iomem, reg) | ((u64)gpu_read(iomem, reg + 4) << 32)); in gpu_read64()
674 hi1 = gpu_read(iomem, reg + 4); in gpu_read64_counter()
675 lo = gpu_read(iomem, reg); in gpu_read64_counter()
676 hi2 = gpu_read(iomem, reg + 4); in gpu_read64_counter()
682 read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false, \
687 read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us, \
H A Dpanthor_gpu.c84 l2_config = gpu_read(gpu->iomem, GPU_L2_CONFIG); in panthor_gpu_l2_config_set()
102 u32 fault_status = gpu_read(gpu->iomem, GPU_FAULT_STATUS); in panthor_gpu_irq_handler()
356 !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED)) in panthor_gpu_flush_caches()
397 !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED)) in panthor_gpu_soft_reset()
475 if ((gpu_read(ptdev->gpu->iomem, GPU_COHERENCY_FEATURES) & in panthor_gpu_coherency_init()
H A Dpanthor_fw.c1141 !(gpu_read(fw->irq.iomem, INT_STAT) & JOB_INT_GLOBAL_IF)) in panthor_fw_start()
1152 u32 status = gpu_read(fw->iomem, MCU_STATUS); in panthor_fw_start()
1178 halted = gpu_read(ptdev->fw->iomem, MCU_STATUS) == MCU_STATUS_HALT; in panthor_fw_mcu_halted()
H A Dpanthor_pwr.c94 return gpu_read(pwr->irq.iomem, INT_RAWSTAT) & PWR_IRQ_RESET_COMPLETED; in reset_irq_raised()
H A Dpanthor_mmu.c1877 fault_status = gpu_read(mmu->iomem, AS_FAULTSTATUS(as)); in panthor_mmu_irq_handler()
/linux/drivers/gpu/drm/msm/
H A Dmsm_gpu.h654 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) in gpu_read() function