Home
last modified time | relevance | path

Searched refs:gpu (Results 1 – 25 of 397) sorted by relevance

12345678910>>...16

/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c43 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
45 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
49 *value = gpu->identity.model; in etnaviv_gpu_get_param()
53 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
57 *value = gpu->identity.features; in etnaviv_gpu_get_param()
61 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
65 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
69 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
73 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
77 *value = gpu->identity.minor_features4; in etnaviv_gpu_get_param()
[all …]
H A Detnaviv_sched.c29 dev_dbg(submit->gpu->dev, "skipping bad job\n"); in etnaviv_sched_run_job()
38 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_timedout_job() local
54 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
55 change = dma_addr - gpu->hangcheck_dma_addr; in etnaviv_sched_timedout_job()
58 mutex_lock(&gpu->lock); in etnaviv_sched_timedout_job()
59 gpu_write(gpu, VIVS_MC_PROFILE_CONFIG0, in etnaviv_sched_timedout_job()
62 primid = gpu_read(gpu, VIVS_MC_PROFILE_FE_READ); in etnaviv_sched_timedout_job()
63 mutex_unlock(&gpu->lock); in etnaviv_sched_timedout_job()
65 if (gpu->state == ETNA_GPU_STATE_RUNNING && in etnaviv_sched_timedout_job()
66 (gpu->completed_fence != gpu->hangcheck_fence || in etnaviv_sched_timedout_job()
[all …]
H A Detnaviv_gpu.h90 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
170 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() argument
172 writel(data, gpu->mmio + reg); in gpu_write()
175 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() argument
182 readl(gpu->mmio + reg); in gpu_read()
184 return readl(gpu->mmio + reg); in gpu_read()
187 static inline u32 gpu_fix_power_address(struct etnaviv_gpu *gpu, u32 reg) in gpu_fix_power_address() argument
190 if (gpu->identity.model == chipModel_GC300 && in gpu_fix_power_address()
191 gpu->identity.revision < 0x2000) in gpu_fix_power_address()
197 static inline void gpu_write_power(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write_power() argument
[all …]
H A Detnaviv_drv.c51 struct etnaviv_gpu *g = priv->gpu[i]; in load_gpu()
58 priv->gpu[i] = NULL; in load_gpu()
86 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_open() local
89 if (gpu) { in etnaviv_open()
90 sched = &gpu->sched; in etnaviv_open()
113 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_postclose() local
115 if (gpu) in etnaviv_postclose()
151 static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_mmu_show() argument
156 seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev)); in etnaviv_mmu_show()
163 mutex_lock(&gpu->lock); in etnaviv_mmu_show()
[all …]
H A Detnaviv_iommu_v2.c165 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_nonsec() argument
172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
175 if (gpu->mmu_context) in etnaviv_iommuv2_restore_nonsec()
176 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv2_restore_nonsec()
177 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv2_restore_nonsec()
179 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec()
182 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec()
184 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec()
186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
189 static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_sec() argument
[all …]
H A Detnaviv_iommu.c89 static void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu, in etnaviv_iommuv1_restore() argument
95 if (gpu->mmu_context) in etnaviv_iommuv1_restore()
96 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv1_restore()
97 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv1_restore()
100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
[all …]
H A Detnaviv_dump.c82 struct etnaviv_gpu *gpu) in etnaviv_core_dump_registers() argument
92 read_addr = gpu_fix_power_address(gpu, read_addr); in etnaviv_core_dump_registers()
94 reg->value = cpu_to_le32(gpu_read(gpu, read_addr)); in etnaviv_core_dump_registers()
120 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_core_dump() local
142 mmu_size + gpu->buffer.size + submit->cmdbuf.size; in etnaviv_core_dump()
165 dev_warn(gpu->dev, "failed to allocate devcoredump file\n"); in etnaviv_core_dump()
175 etnaviv_core_dump_registers(&iter, gpu); in etnaviv_core_dump()
177 etnaviv_core_dump_mem(&iter, ETDUMP_BUF_RING, gpu->buffer.vaddr, in etnaviv_core_dump()
178 gpu->buffer.size, in etnaviv_core_dump()
179 etnaviv_cmdbuf_get_va(&gpu->buffer, in etnaviv_core_dump()
[all …]
H A Detnaviv_cmd_parser.c16 struct etnaviv_gpu *gpu; member
94 dev_warn_once(state->gpu->dev, in etnaviv_warn_if_non_sensitive()
124 dev_warn_ratelimited(state->gpu->dev, in etnaviv_validate_load_state()
148 bool etnaviv_cmd_validate_one(struct etnaviv_gpu *gpu, u32 *stream, in etnaviv_cmd_validate_one() argument
157 state.gpu = gpu; in etnaviv_cmd_validate_one()
190 dev_err(gpu->dev, "%s: op %u not permitted at offset %tu\n", in etnaviv_cmd_validate_one()
201 dev_err(gpu->dev, "%s: commands overflow end of buffer: %tu > %u\n", in etnaviv_cmd_validate_one()
/linux/drivers/gpu/drm/msm/adreno/
H A Da3xx_gpu.c28 static void a3xx_dump(struct msm_gpu *gpu);
29 static bool a3xx_idle(struct msm_gpu *gpu);
31 static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a3xx_submit() argument
82 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_submit()
85 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument
87 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
108 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_me_init()
109 return a3xx_idle(gpu); in a3xx_me_init()
112 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init() argument
114 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a3xx_hw_init()
[all …]
H A Da8xx_gpu.c19 static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) in a8xx_aperture_slice_set() argument
21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_slice_set()
30 gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val); in a8xx_aperture_slice_set()
35 static void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) in a8xx_aperture_acquire() argument
37 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_acquire()
42 a8xx_aperture_slice_set(gpu, pipe, 0); in a8xx_aperture_acquire()
45 static void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags) in a8xx_aperture_release() argument
47 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_release()
53 static void a8xx_aperture_clear(struct msm_gpu *gpu) in a8xx_aperture_clear() argument
57 a8xx_aperture_acquire(gpu, PIPE_NONE, &flags); in a8xx_aperture_clear()
[all …]
H A Da2xx_gpu.c10 static void a2xx_dump(struct msm_gpu *gpu);
11 static bool a2xx_idle(struct msm_gpu *gpu);
13 static void a2xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a2xx_submit() argument
51 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_submit()
54 static bool a2xx_me_init(struct msm_gpu *gpu) in a2xx_me_init() argument
56 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a2xx_me_init()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
107 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a2xx_me_init()
108 return a2xx_idle(gpu); in a2xx_me_init()
111 static int a2xx_hw_init(struct msm_gpu *gpu) in a2xx_hw_init() argument
[all …]
H A Da5xx_preempt.c25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in get_next_ring()
63 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
65 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
68 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
84 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local
[all …]
H A Da5xx_gpu.h54 void a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
138 int a5xx_power_init(struct msm_gpu *gpu);
139 void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
141 static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, in spin_usecs() argument
146 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
157 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
158 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
160 void a5xx_preempt_init(struct msm_gpu *gpu);
161 void a5xx_preempt_hw_init(struct msm_gpu *gpu);
162 void a5xx_preempt_trigger(struct msm_gpu *gpu);
[all …]
H A Da2xx_gpummu.c16 struct msm_gpu *gpu; member
56 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_map()
71 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_unmap()
94 struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu) in a2xx_gpummu_new() argument
109 gpummu->gpu = gpu; in a2xx_gpummu_new()
/linux/drivers/gpu/drm/msm/
H A Dmsm_gpu.h49 int (*get_param)(struct msm_gpu *gpu, struct msm_context *ctx,
51 int (*set_param)(struct msm_gpu *gpu, struct msm_context *ctx,
53 int (*hw_init)(struct msm_gpu *gpu);
58 int (*ucode_load)(struct msm_gpu *gpu);
60 int (*pm_suspend)(struct msm_gpu *gpu);
61 int (*pm_resume)(struct msm_gpu *gpu);
62 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
63 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
65 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
66 void (*recover)(struct msm_gpu *gpu);
[all …]
H A Dmsm_debugfs.c37 struct msm_gpu *gpu = priv->gpu; in msm_gpu_show() local
40 ret = mutex_lock_interruptible(&gpu->lock); in msm_gpu_show()
44 drm_printf(&p, "%s Status:\n", gpu->name); in msm_gpu_show()
45 gpu->funcs->show(gpu, show_priv->state, &p); in msm_gpu_show()
47 mutex_unlock(&gpu->lock); in msm_gpu_show()
57 struct msm_gpu *gpu = priv->gpu; in msm_gpu_release() local
59 mutex_lock(&gpu->lock); in msm_gpu_release()
60 gpu->funcs->gpu_state_put(show_priv->state); in msm_gpu_release()
61 mutex_unlock(&gpu->lock); in msm_gpu_release()
72 struct msm_gpu *gpu = priv->gpu; in msm_gpu_open() local
[all …]
H A Dmsm_submitqueue.c10 int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sysprof) in msm_context_set_sysprof() argument
20 return UERR(EINVAL, gpu->dev, "Invalid sysprof: %d", sysprof); in msm_context_set_sysprof()
22 pm_runtime_get_sync(&gpu->pdev->dev); in msm_context_set_sysprof()
25 refcount_inc(&gpu->sysprof_active); in msm_context_set_sysprof()
34 pm_runtime_put_autosuspend(&gpu->pdev->dev); in msm_context_set_sysprof()
37 refcount_dec(&gpu->sysprof_active); in msm_context_set_sysprof()
44 if (gpu->funcs->sysprof_setup) in msm_context_set_sysprof()
45 gpu->funcs->sysprof_setup(gpu); in msm_context_set_sysprof()
183 if (!priv->gpu) in msm_submitqueue_create()
201 priv->gpu->nr_rings == 1 && enable_preemption != 0; in msm_submitqueue_create()
[all …]
H A Dmsm_perf.c61 struct msm_gpu *gpu = priv->gpu; in refill_buf() local
72 for (i = 0; i < gpu->num_perfcntrs; i++) { in refill_buf()
73 const struct msm_gpu_perfcntr *perfcntr = &gpu->perfcntrs[i]; in refill_buf()
90 ret = msm_gpu_perfcntr_sample(gpu, &activetime, &totaltime, in refill_buf()
155 struct msm_gpu *gpu = priv->gpu; in perf_open() local
158 if (!gpu) in perf_open()
161 mutex_lock(&gpu->lock); in perf_open()
173 msm_gpu_perfcntr_start(gpu); in perf_open()
177 mutex_unlock(&gpu->lock); in perf_open()
185 msm_gpu_perfcntr_stop(priv->gpu); in perf_release()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_topology.c108 return top_dev->gpu; in kfd_device_by_id()
261 if (iolink->gpu && kfd_devcgroup_check_permission(iolink->gpu)) in iolink_show()
303 if (mem->gpu && kfd_devcgroup_check_permission(mem->gpu)) in mem_show()
335 if (cache->gpu && kfd_devcgroup_check_permission(cache->gpu)) in kfd_cache_show()
417 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu)) in node_show()
426 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu)) in node_show()
433 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu)) in node_show()
438 dev->gpu ? dev->node_props.simd_count : 0); in node_show()
462 dev->gpu ? (dev->node_props.array_count * in node_show()
463 NUM_XCC(dev->gpu->xcc_mask)) : 0); in node_show()
[all …]
/linux/Documentation/gpu/
H A Dvc4.rst5 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_drv.c
18 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_crtc.c
24 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_hvs.c
30 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_plane.c
36 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_hdmi.c
42 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_dsi.c
48 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_dpi.c
54 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_vec.c
69 --kunitconfig=drivers/gpu/drm/vc4/tests/.kunitconfig \
84 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_bo.c
[all …]
H A Ddrm-kms.rst159 .. kernel-doc:: drivers/gpu/drm/drm_mode_config.c
191 .. kernel-doc:: drivers/gpu/drm/drm_mode_object.c
288 .. kernel-doc:: drivers/gpu/drm/drm_atomic.c
297 .. kernel-doc:: drivers/gpu/drm/drm_atomic.c
303 .. kernel-doc:: drivers/gpu/drm/drm_atomic_uapi.c
306 .. kernel-doc:: drivers/gpu/drm/drm_atomic_uapi.c
312 .. kernel-doc:: drivers/gpu/drm/drm_crtc.c
321 .. kernel-doc:: drivers/gpu/drm/drm_crtc.c
327 .. kernel-doc:: drivers/gpu/drm/drm_color_mgmt.c
336 .. kernel-doc:: drivers/gpu/drm/drm_framebuffer.c
[all …]
H A Dv3d.rst5 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_drv.c
11 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_bo.c
16 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_mmu.c
21 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_sched.c
27 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_irq.c
H A Dmeson.rst5 .. kernel-doc:: drivers/gpu/drm/meson/meson_drv.c
30 .. kernel-doc:: drivers/gpu/drm/meson/meson_viu.c
36 .. kernel-doc:: drivers/gpu/drm/meson/meson_vpp.c
42 .. kernel-doc:: drivers/gpu/drm/meson/meson_venc.c
48 .. kernel-doc:: drivers/gpu/drm/meson/meson_vclk.c
54 .. kernel-doc:: drivers/gpu/drm/meson/meson_dw_hdmi.c
H A Dvga-switcheroo.rst7 .. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
16 .. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
22 .. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
31 .. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
58 .. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
61 .. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
/linux/Documentation/gpu/xe/
H A Dxe_mm.rst7 .. kernel-doc:: drivers/gpu/drm/xe/xe_bo_doc.h
13 .. kernel-doc:: drivers/gpu/drm/xe/xe_ggtt.c
19 .. kernel-doc:: drivers/gpu/drm/xe/xe_ggtt_types.h
22 .. kernel-doc:: drivers/gpu/drm/xe/xe_ggtt.c
28 .. kernel-doc:: drivers/gpu/drm/xe/xe_pt.c

12345678910>>...16