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/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c42 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
44 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
48 *value = gpu->identity.model; in etnaviv_gpu_get_param()
52 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
56 *value = gpu->identity.features; in etnaviv_gpu_get_param()
60 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
64 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
68 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
72 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
76 *value = gpu->identity.minor_features4; in etnaviv_gpu_get_param()
[all …]
H A Detnaviv_gpu.h90 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
170 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() argument
172 writel(data, gpu->mmio + reg); in gpu_write()
175 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() argument
182 readl(gpu->mmio + reg); in gpu_read()
184 return readl(gpu->mmio + reg); in gpu_read()
187 static inline u32 gpu_fix_power_address(struct etnaviv_gpu *gpu, u32 reg) in gpu_fix_power_address() argument
190 if (gpu->identity.model == chipModel_GC300 && in gpu_fix_power_address()
191 gpu->identity.revision < 0x2000) in gpu_fix_power_address()
197 static inline void gpu_write_power(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write_power() argument
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H A Detnaviv_drv.c51 struct etnaviv_gpu *g = priv->gpu[i]; in load_gpu()
58 priv->gpu[i] = NULL; in load_gpu()
86 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_open() local
89 if (gpu) { in etnaviv_open()
90 sched = &gpu->sched; in etnaviv_open()
113 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_postclose() local
115 if (gpu) in etnaviv_postclose()
151 static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_mmu_show() argument
156 seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev)); in etnaviv_mmu_show()
163 mutex_lock(&gpu->lock); in etnaviv_mmu_show()
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H A Detnaviv_iommu_v2.c165 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_nonsec() argument
172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
175 if (gpu->mmu_context) in etnaviv_iommuv2_restore_nonsec()
176 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv2_restore_nonsec()
177 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv2_restore_nonsec()
179 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec()
182 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec()
184 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec()
186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
189 static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_sec() argument
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H A Detnaviv_iommu.c89 static void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu, in etnaviv_iommuv1_restore() argument
95 if (gpu->mmu_context) in etnaviv_iommuv1_restore()
96 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv1_restore()
97 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv1_restore()
100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
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H A Detnaviv_dump.c82 struct etnaviv_gpu *gpu) in etnaviv_core_dump_registers() argument
92 read_addr = gpu_fix_power_address(gpu, read_addr); in etnaviv_core_dump_registers()
94 reg->value = cpu_to_le32(gpu_read(gpu, read_addr)); in etnaviv_core_dump_registers()
120 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_core_dump() local
142 mmu_size + gpu->buffer.size + submit->cmdbuf.size; in etnaviv_core_dump()
165 dev_warn(gpu->dev, "failed to allocate devcoredump file\n"); in etnaviv_core_dump()
175 etnaviv_core_dump_registers(&iter, gpu); in etnaviv_core_dump()
177 etnaviv_core_dump_mem(&iter, ETDUMP_BUF_RING, gpu->buffer.vaddr, in etnaviv_core_dump()
178 gpu->buffer.size, in etnaviv_core_dump()
179 etnaviv_cmdbuf_get_va(&gpu->buffer, in etnaviv_core_dump()
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H A Detnaviv_cmd_parser.c16 struct etnaviv_gpu *gpu; member
94 dev_warn_once(state->gpu->dev, in etnaviv_warn_if_non_sensitive()
124 dev_warn_ratelimited(state->gpu->dev, in etnaviv_validate_load_state()
148 bool etnaviv_cmd_validate_one(struct etnaviv_gpu *gpu, u32 *stream, in etnaviv_cmd_validate_one() argument
157 state.gpu = gpu; in etnaviv_cmd_validate_one()
190 dev_err(gpu->dev, "%s: op %u not permitted at offset %tu\n", in etnaviv_cmd_validate_one()
201 dev_err(gpu->dev, "%s: commands overflow end of buffer: %tu > %u\n", in etnaviv_cmd_validate_one()
H A Detnaviv_perfmon.h26 int etnaviv_pm_query_dom(struct etnaviv_gpu *gpu,
29 int etnaviv_pm_query_sig(struct etnaviv_gpu *gpu,
35 void etnaviv_perfmon_process(struct etnaviv_gpu *gpu,
/linux/drivers/gpu/drm/panthor/
H A Dpanthor_gpu.c62 gpu_write(ptdev->gpu->iomem, GPU_COHERENCY_PROTOCOL, in panthor_gpu_coherency_set()
68 struct panthor_gpu *gpu = ptdev->gpu; in panthor_gpu_l2_config_set() local
82 gpu_write(gpu->iomem, GPU_ASN_HASH(i), data->asn_hash[i]); in panthor_gpu_l2_config_set()
84 l2_config = gpu_read(gpu->iomem, GPU_L2_CONFIG); in panthor_gpu_l2_config_set()
86 gpu_write(gpu->iomem, GPU_L2_CONFIG, l2_config); in panthor_gpu_l2_config_set()
91 struct panthor_gpu *gpu = ptdev->gpu; in panthor_gpu_irq_handler() local
93 gpu_write(gpu->irq.iomem, INT_CLEAR, status); in panthor_gpu_irq_handler()
97 gpu_read64(gpu->iomem, SHADER_READY), in panthor_gpu_irq_handler()
98 gpu_read64(gpu->iomem, TILER_READY), in panthor_gpu_irq_handler()
99 gpu_read64(gpu->iomem, L2_READY)); in panthor_gpu_irq_handler()
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/linux/drivers/gpu/drm/msm/adreno/
H A Da5xx_preempt.c25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in get_next_ring()
63 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
65 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
68 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
84 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local
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H A Da5xx_gpu.h54 void a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
138 int a5xx_power_init(struct msm_gpu *gpu);
139 void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
141 static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, in spin_usecs() argument
146 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
157 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
158 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
160 void a5xx_preempt_init(struct msm_gpu *gpu);
161 void a5xx_preempt_hw_init(struct msm_gpu *gpu);
162 void a5xx_preempt_trigger(struct msm_gpu *gpu);
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H A Da2xx_gpummu.c16 struct msm_gpu *gpu; member
56 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_map()
71 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in a2xx_gpummu_unmap()
94 struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu) in a2xx_gpummu_new() argument
109 gpummu->gpu = gpu; in a2xx_gpummu_new()
/linux/tools/testing/selftests/vfio/lib/drivers/nv_falcon/
H A Dnv_falcon.c72 static inline u32 gpu_read32(struct gpu_device *gpu, u32 offset) in gpu_read32() argument
74 return readl(gpu->bar0 + offset); in gpu_read32()
77 static inline void gpu_write32(struct gpu_device *gpu, u32 offset, u32 value) in gpu_write32() argument
79 writel(value, gpu->bar0 + offset); in gpu_write32()
96 struct gpu_device *gpu = to_gpu_device(device); in gpu_poll_register() local
104 value = gpu_read32(gpu, offset); in gpu_poll_register()
126 struct gpu_device *gpu = to_gpu_device(device); in fsp_poll_queue() local
134 head = gpu_read32(gpu, head_reg); in fsp_poll_queue()
135 tail = gpu_read32(gpu, tail_reg); in fsp_poll_queue()
156 struct gpu_device *gpu = to_gpu_device(device); in fsp_emem_write() local
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/linux/Documentation/gpu/
H A Dvc4.rst5 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_drv.c
18 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_crtc.c
24 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_hvs.c
30 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_plane.c
36 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_hdmi.c
42 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_dsi.c
48 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_dpi.c
54 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_vec.c
69 --kunitconfig=drivers/gpu/drm/vc4/tests/.kunitconfig \
84 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_bo.c
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H A Dv3d.rst5 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_drv.c
11 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_bo.c
16 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_mmu.c
21 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_sched.c
27 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_irq.c
H A Dmeson.rst5 .. kernel-doc:: drivers/gpu/drm/meson/meson_drv.c
30 .. kernel-doc:: drivers/gpu/drm/meson/meson_viu.c
36 .. kernel-doc:: drivers/gpu/drm/meson/meson_vpp.c
42 .. kernel-doc:: drivers/gpu/drm/meson/meson_venc.c
48 .. kernel-doc:: drivers/gpu/drm/meson/meson_vclk.c
54 .. kernel-doc:: drivers/gpu/drm/meson/meson_dw_hdmi.c
H A Dvga-switcheroo.rst7 .. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
16 .. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
22 .. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
31 .. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
58 .. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
61 .. kernel-doc:: drivers/gpu/vga/vga_switcheroo.c
H A Dxen-front.rst12 .. kernel-doc:: drivers/gpu/drm/xen/xen_drm_front.h
18 .. kernel-doc:: drivers/gpu/drm/xen/xen_drm_front.h
24 .. kernel-doc:: drivers/gpu/drm/xen/xen_drm_front.h
30 .. kernel-doc:: drivers/gpu/drm/xen/xen_drm_front.h
/linux/Documentation/gpu/xe/
H A Dxe_mm.rst7 .. kernel-doc:: drivers/gpu/drm/xe/xe_bo_doc.h
13 .. kernel-doc:: drivers/gpu/drm/xe/xe_ggtt.c
19 .. kernel-doc:: drivers/gpu/drm/xe/xe_ggtt_types.h
22 .. kernel-doc:: drivers/gpu/drm/xe/xe_ggtt.c
28 .. kernel-doc:: drivers/gpu/drm/xe/xe_pt.c
H A Dxe_rtp.rst7 .. kernel-doc:: drivers/gpu/drm/xe/xe_rtp.c
13 .. kernel-doc:: drivers/gpu/drm/xe/xe_rtp_types.h
16 .. kernel-doc:: drivers/gpu/drm/xe/xe_rtp.h
19 .. kernel-doc:: drivers/gpu/drm/xe/xe_rtp.c
/linux/Documentation/gpu/amdgpu/display/
H A Ddisplay-manager.rst8 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
17 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
20 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
26 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
47 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
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/linux/drivers/gpu/drm/renesas/
H A DKconfig3 source "drivers/gpu/drm/renesas/rcar-du/Kconfig"
4 source "drivers/gpu/drm/renesas/rz-du/Kconfig"
5 source "drivers/gpu/drm/renesas/shmobile/Kconfig"
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c83 unsigned int *gpu) in loongson_gfxpll_get_rates() argument
113 if (gpu) in loongson_gfxpll_get_rates()
114 *gpu = gpu_mhz; in loongson_gfxpll_get_rates()
122 unsigned int dc, gmc, gpu; in loongson_gfxpll_print() local
134 this->funcs->get_rates(this, &dc, &gmc, &gpu); in loongson_gfxpll_print()
136 drm_printf(p, "dc: %uMHz, gmc: %uMHz, gpu: %uMHz\n", dc, gmc, gpu); in loongson_gfxpll_print()
/linux/Documentation/gpu/amdgpu/
H A Dras.rst11 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
17 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
23 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
29 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
35 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/vfn/
H A Dr535.c37 const struct nvkm_rm_gpu *gpu = device->gsp->rm->gpu; in r535_vfn_new() local
50 rm->user.base.oclass = gpu->usermode.class; in r535_vfn_new()

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