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/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c40 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
42 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
46 *value = gpu->identity.model; in etnaviv_gpu_get_param()
50 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
54 *value = gpu->identity.features; in etnaviv_gpu_get_param()
58 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
62 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
66 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
70 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
74 *value = gpu->identity.minor_features4; in etnaviv_gpu_get_param()
[all …]
H A Detnaviv_sched.c29 dev_dbg(submit->gpu->dev, "skipping bad job\n"); in etnaviv_sched_run_job()
38 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_sched_timedout_job() local
54 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
55 change = dma_addr - gpu->hangcheck_dma_addr; in etnaviv_sched_timedout_job()
58 mutex_lock(&gpu->lock); in etnaviv_sched_timedout_job()
59 gpu_write(gpu, VIVS_MC_PROFILE_CONFIG0, in etnaviv_sched_timedout_job()
62 primid = gpu_read(gpu, VIVS_MC_PROFILE_FE_READ); in etnaviv_sched_timedout_job()
63 mutex_unlock(&gpu->lock); in etnaviv_sched_timedout_job()
65 if (gpu->state == ETNA_GPU_STATE_RUNNING && in etnaviv_sched_timedout_job()
66 (gpu->completed_fence != gpu->hangcheck_fence || in etnaviv_sched_timedout_job()
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H A Detnaviv_gpu.h90 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
170 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() argument
172 writel(data, gpu->mmio + reg); in gpu_write()
175 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() argument
182 readl(gpu->mmio + reg); in gpu_read()
184 return readl(gpu->mmio + reg); in gpu_read()
187 static inline u32 gpu_fix_power_address(struct etnaviv_gpu *gpu, u32 reg) in gpu_fix_power_address() argument
190 if (gpu->identity.model == chipModel_GC300 && in gpu_fix_power_address()
191 gpu->identity.revision < 0x2000) in gpu_fix_power_address()
197 static inline void gpu_write_power(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write_power() argument
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H A Detnaviv_drv.c50 struct etnaviv_gpu *g = priv->gpu[i]; in load_gpu()
57 priv->gpu[i] = NULL; in load_gpu()
85 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_open() local
88 if (gpu) { in etnaviv_open()
89 sched = &gpu->sched; in etnaviv_open()
112 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_postclose() local
114 if (gpu) in etnaviv_postclose()
150 static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_mmu_show() argument
155 seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev)); in etnaviv_mmu_show()
162 mutex_lock(&gpu->lock); in etnaviv_mmu_show()
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H A Detnaviv_iommu_v2.c165 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_nonsec() argument
172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
175 if (gpu->mmu_context) in etnaviv_iommuv2_restore_nonsec()
176 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv2_restore_nonsec()
177 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv2_restore_nonsec()
179 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec()
182 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec()
184 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec()
186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
189 static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_sec() argument
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H A Detnaviv_iommu.c89 static void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu, in etnaviv_iommuv1_restore() argument
95 if (gpu->mmu_context) in etnaviv_iommuv1_restore()
96 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv1_restore()
97 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv1_restore()
100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
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/linux/drivers/gpu/drm/msm/adreno/
H A Da4xx_gpu.c22 static void a4xx_dump(struct msm_gpu *gpu);
23 static bool a4xx_idle(struct msm_gpu *gpu);
25 static void a4xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a4xx_submit() argument
69 adreno_flush(gpu, ring, REG_A4XX_CP_RB_WPTR); in a4xx_submit()
76 static void a4xx_enable_hwcg(struct msm_gpu *gpu) in a4xx_enable_hwcg() argument
78 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a4xx_enable_hwcg()
81 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
83 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
85 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
87 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
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H A Da3xx_gpu.c28 static void a3xx_dump(struct msm_gpu *gpu);
29 static bool a3xx_idle(struct msm_gpu *gpu);
31 static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a3xx_submit() argument
82 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_submit()
85 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument
87 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
108 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_me_init()
109 return a3xx_idle(gpu); in a3xx_me_init()
112 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init() argument
114 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a3xx_hw_init()
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H A Da5xx_gpu.c17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
36 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
46 update_shadow_rptr(gpu, ring); in a5xx_flush()
63 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
66 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit_in_rb() argument
68 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_submit_in_rb()
115 a5xx_flush(gpu, ring, true); in a5xx_submit_in_rb()
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H A Dadreno_gpu.h73 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
287 static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu) in adreno_patchid() argument
293 WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1); in adreno_patchid()
294 return gpu->chip_id & 0xff; in adreno_patchid()
297 static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) in adreno_is_revn() argument
299 if (WARN_ON_ONCE(!gpu->info)) in adreno_is_revn()
301 return gpu->info->revn == revn; in adreno_is_revn()
304 static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) in adreno_has_gmu_wrapper() argument
306 return gpu->gmu_is_wrapper; in adreno_has_gmu_wrapper()
309 static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) in adreno_is_a2xx() argument
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H A Da6xx_gpu.c19 static inline bool _a6xx_check_idle(struct msm_gpu *gpu) in _a6xx_check_idle() argument
21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in _a6xx_check_idle()
29 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
33 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
37 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a6xx_idle() argument
40 if (!adreno_idle(gpu, ring)) in a6xx_idle()
43 if (spin_until(_a6xx_check_idle(gpu))) { in a6xx_idle()
45 gpu->name, __builtin_return_address(0), in a6xx_idle()
46 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
47 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle()
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H A Da5xx_preempt.c25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in get_next_ring()
63 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
65 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
68 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
83 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local
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H A Dadreno_device.c66 struct msm_gpu *gpu = NULL; in adreno_load_gpu() local
71 gpu = dev_to_gpu(&pdev->dev); in adreno_load_gpu()
73 if (!gpu) { in adreno_load_gpu()
78 adreno_gpu = to_adreno_gpu(gpu); in adreno_load_gpu()
90 if (gpu->funcs->ucode_load) { in adreno_load_gpu()
91 ret = gpu->funcs->ucode_load(gpu); in adreno_load_gpu()
109 mutex_lock(&gpu->lock); in adreno_load_gpu()
110 ret = msm_gpu_hw_init(gpu); in adreno_load_gpu()
111 mutex_unlock(&gpu->lock); in adreno_load_gpu()
120 if (gpu->funcs->debugfs_init) { in adreno_load_gpu()
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H A Da5xx_debugfs.c14 static void pfp_print(struct msm_gpu *gpu, struct drm_printer *p) in pfp_print() argument
21 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print()
23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
27 static void me_print(struct msm_gpu *gpu, struct drm_printer *p) in me_print() argument
34 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print()
36 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
40 static void meq_print(struct msm_gpu *gpu, struct drm_printer *p) in meq_print() argument
45 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print()
49 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
53 static void roq_print(struct msm_gpu *gpu, struct drm_printer *p) in roq_print() argument
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H A Dadreno_gpu.c30 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt() argument
33 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
85 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); in zap_shader_load_mdt()
90 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); in zap_shader_load_mdt()
140 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) { in zap_shader_load_mdt()
176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) in adreno_zap_shader_load() argument
178 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_zap_shader_load()
179 struct platform_device *pdev = gpu->pdev; in adreno_zap_shader_load()
191 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); in adreno_zap_shader_load()
195 adreno_create_address_space(struct msm_gpu *gpu, in adreno_create_address_space() argument
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H A Da6xx_gpu_state.c131 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument
134 dumper->ptr = msm_gem_kernel_new(gpu->dev, in a6xx_crashdumper_init()
135 SZ_1M, MSM_BO_WC, gpu->aspace, in a6xx_crashdumper_init()
144 static int a6xx_crashdumper_run(struct msm_gpu *gpu, in a6xx_crashdumper_run() argument
147 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_crashdumper_run()
161 gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE, dumper->iova); in a6xx_crashdumper_run()
163 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
165 ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val, in a6xx_crashdumper_run()
168 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
174 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, in debugbus_read() argument
[all …]
H A Da5xx_gpu.h54 void a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
137 int a5xx_power_init(struct msm_gpu *gpu);
138 void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
140 static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, in spin_usecs() argument
145 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
156 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
157 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
159 void a5xx_preempt_init(struct msm_gpu *gpu);
160 void a5xx_preempt_hw_init(struct msm_gpu *gpu);
161 void a5xx_preempt_trigger(struct msm_gpu *gpu);
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H A Da6xx_gpu.h214 static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) in a6xx_has_gbif() argument
216 if(adreno_is_a630(gpu)) in a6xx_has_gbif()
240 int a6xx_gmu_resume(struct a6xx_gpu *gpu);
241 int a6xx_gmu_stop(struct a6xx_gpu *gpu);
254 void a6xx_preempt_init(struct msm_gpu *gpu);
255 void a6xx_preempt_hw_init(struct msm_gpu *gpu);
256 void a6xx_preempt_trigger(struct msm_gpu *gpu);
257 void a6xx_preempt_irq(struct msm_gpu *gpu);
258 void a6xx_preempt_fini(struct msm_gpu *gpu);
259 int a6xx_preempt_submitqueue_setup(struct msm_gpu *gpu,
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/linux/Documentation/gpu/
H A Ddrm-kms-helpers.rst53 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
59 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
68 .. kernel-doc:: drivers/gpu/drm/drm_atomic_helper.c
74 .. kernel-doc:: drivers/gpu/drm/drm_atomic_state_helper.c
80 .. kernel-doc:: drivers/gpu/drm/drm_atomic_state_helper.c
86 .. kernel-doc:: drivers/gpu/drm/drm_gem_atomic_helper.c
92 .. kernel-doc:: drivers/gpu/drm/drm_gem_atomic_helper.c
98 .. kernel-doc:: drivers/gpu/drm/drm_simple_kms_helper.c
104 .. kernel-doc:: drivers/gpu/drm/drm_simple_kms_helper.c
110 .. kernel-doc:: drivers/gpu/drm/drm_fb_helper.c
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H A Dvc4.rst5 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_drv.c
18 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_crtc.c
24 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_hvs.c
30 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_plane.c
36 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_hdmi.c
42 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_dsi.c
48 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_dpi.c
54 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_vec.c
69 --kunitconfig=drivers/gpu/drm/vc4/tests/.kunitconfig \
84 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_bo.c
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/linux/drivers/gpu/drm/panthor/
H A Dpanthor_gpu.c165 spin_lock(&ptdev->gpu->reqs_lock); in panthor_gpu_irq_handler()
166 if (status & ptdev->gpu->pending_reqs) { in panthor_gpu_irq_handler()
167 ptdev->gpu->pending_reqs &= ~status; in panthor_gpu_irq_handler()
168 wake_up_all(&ptdev->gpu->reqs_acked); in panthor_gpu_irq_handler()
170 spin_unlock(&ptdev->gpu->reqs_lock); in panthor_gpu_irq_handler()
172 PANTHOR_IRQ_HANDLER(gpu, GPU, panthor_gpu_irq_handler);
184 panthor_gpu_irq_suspend(&ptdev->gpu->irq); in panthor_gpu_unplug()
187 spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags); in panthor_gpu_unplug()
188 ptdev->gpu->pending_reqs = 0; in panthor_gpu_unplug()
189 wake_up_all(&ptdev->gpu->reqs_acked); in panthor_gpu_unplug()
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/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_topology.c108 return top_dev->gpu; in kfd_device_by_id()
119 if (top_dev->gpu && top_dev->gpu->adev->pdev == pdev) { in kfd_device_by_pci_dev()
120 device = top_dev->gpu; in kfd_device_by_pci_dev()
279 if (iolink->gpu && kfd_devcgroup_check_permission(iolink->gpu)) in iolink_show()
321 if (mem->gpu && kfd_devcgroup_check_permission(mem->gpu)) in mem_show()
353 if (cache->gpu && kfd_devcgroup_check_permission(cache->gpu)) in kfd_cache_show()
435 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu)) in node_show()
444 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu)) in node_show()
451 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu)) in node_show()
456 dev->gpu ? dev->node_props.simd_count : 0); in node_show()
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/linux/Documentation/gpu/amdgpu/
H A Ddriver-misc.rst14 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
20 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
26 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
32 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
38 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
44 .. kernel-doc:: drivers/gpu/drm/amd/pm/amdgpu_pm.c
50 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
78 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
84 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
90 .. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
[all …]
/linux/drivers/gpu/drm/msm/
H A Dmsm_debugfs.c37 struct msm_gpu *gpu = priv->gpu; in msm_gpu_show() local
40 ret = mutex_lock_interruptible(&gpu->lock); in msm_gpu_show()
44 drm_printf(&p, "%s Status:\n", gpu->name); in msm_gpu_show()
45 gpu->funcs->show(gpu, show_priv->state, &p); in msm_gpu_show()
47 mutex_unlock(&gpu->lock); in msm_gpu_show()
57 struct msm_gpu *gpu = priv->gpu; in msm_gpu_release() local
59 mutex_lock(&gpu->lock); in msm_gpu_release()
60 gpu->funcs->gpu_state_put(show_priv->state); in msm_gpu_release()
61 mutex_unlock(&gpu->lock); in msm_gpu_release()
72 struct msm_gpu *gpu = priv->gpu; in msm_gpu_open() local
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/linux/drivers/gpu/drm/
H A DKconfig226 source "drivers/gpu/drm/clients/Kconfig"
240 source "drivers/gpu/drm/display/Kconfig"
329 source "drivers/gpu/drm/i2c/Kconfig"
331 source "drivers/gpu/drm/arm/Kconfig"
333 source "drivers/gpu/drm/radeon/Kconfig"
335 source "drivers/gpu/drm/amd/amdgpu/Kconfig"
337 source "drivers/gpu/drm/nouveau/Kconfig"
339 source "drivers/gpu/drm/i915/Kconfig"
341 source "drivers/gpu/drm/xe/Kconfig"
343 source "drivers/gpu/drm/kmb/Kconfig"
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