Lines Matching refs:gpu
131 static int a6xx_crashdumper_init(struct msm_gpu *gpu,
134 dumper->ptr = msm_gem_kernel_new(gpu->dev,
135 SZ_1M, MSM_BO_WC, gpu->aspace,
144 static int a6xx_crashdumper_run(struct msm_gpu *gpu,
147 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
161 gpu_write64(gpu, REG_A6XX_CP_CRASH_SCRIPT_BASE, dumper->iova);
163 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1);
165 ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val,
168 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0);
174 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset,
180 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg);
181 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg);
182 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_C, reg);
183 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_D, reg);
188 data[0] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2);
189 data[1] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1);
222 static int vbif_debugbus_read(struct msm_gpu *gpu, u32 ctrl0, u32 ctrl1,
227 gpu_write(gpu, ctrl0, reg);
230 gpu_write(gpu, ctrl1, i);
231 data[i] = gpu_read(gpu, REG_A6XX_VBIF_TEST_BUS_OUT);
246 static void a6xx_get_vbif_debugbus_block(struct msm_gpu *gpu,
261 clk = gpu_read(gpu, REG_A6XX_VBIF_CLKON);
264 gpu_write(gpu, REG_A6XX_VBIF_CLKON,
268 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS1_CTRL0, 0);
271 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS_OUT_CTRL, 1);
276 ptr += vbif_debugbus_read(gpu,
282 ptr += vbif_debugbus_read(gpu,
288 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS2_CTRL0, 0);
291 ptr += vbif_debugbus_read(gpu,
297 gpu_write(gpu, REG_A6XX_VBIF_CLKON, clk);
300 static void a6xx_get_debugbus_block(struct msm_gpu *gpu,
315 ptr += debugbus_read(gpu, block->id, i, ptr);
336 static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu,
340 (a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0);
342 if (adreno_is_a650_family(to_adreno_gpu(gpu)))
352 a6xx_get_debugbus_block(gpu,
364 if (a6xx_has_gbif(to_adreno_gpu(gpu))) {
365 a6xx_get_debugbus_block(gpu, a6xx_state,
373 if (adreno_is_a650_family(to_adreno_gpu(gpu))) {
375 a6xx_get_debugbus_block(gpu,
383 static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu,
386 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
416 a6xx_get_debugbus_block(gpu,
422 a6xx_get_debugbus_block(gpu,
430 static void a6xx_get_debugbus(struct msm_gpu *gpu,
433 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
439 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLT,
442 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_CNTLM,
445 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0, 0);
446 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1, 0);
447 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2, 0);
448 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3, 0);
450 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0, 0x76543210);
451 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1, 0xFEDCBA98);
453 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0, 0);
454 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1, 0);
455 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2, 0);
456 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3, 0);
461 res = platform_get_resource_byname(gpu->pdev, IORESOURCE_MEM,
491 a7xx_get_debugbus_blocks(gpu, a6xx_state);
493 a6xx_get_debugbus_blocks(gpu, a6xx_state);
503 a6xx_get_vbif_debugbus_block(gpu, a6xx_state,
545 static void a6xx_get_dbgahb_cluster(struct msm_gpu *gpu,
583 if (a6xx_crashdumper_run(gpu, dumper))
591 static void a7xx_get_dbgahb_cluster(struct msm_gpu *gpu,
625 if (a6xx_crashdumper_run(gpu, dumper))
633 static void a6xx_get_dbgahb_clusters(struct msm_gpu *gpu,
649 a6xx_get_dbgahb_cluster(gpu, a6xx_state,
654 static void a7xx_get_dbgahb_clusters(struct msm_gpu *gpu,
658 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
685 a7xx_get_dbgahb_cluster(gpu, a6xx_state,
691 static void a6xx_get_cluster(struct msm_gpu *gpu,
697 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
743 if (a6xx_crashdumper_run(gpu, dumper))
751 static void a7xx_get_cluster(struct msm_gpu *gpu,
788 if (a6xx_crashdumper_run(gpu, dumper))
796 static void a6xx_get_clusters(struct msm_gpu *gpu,
811 a6xx_get_cluster(gpu, a6xx_state, &a6xx_clusters[i],
815 static void a7xx_get_clusters(struct msm_gpu *gpu,
819 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
845 a7xx_get_cluster(gpu, a6xx_state, &clusters[i],
850 static void a6xx_get_shader_block(struct msm_gpu *gpu,
876 if (a6xx_crashdumper_run(gpu, dumper))
884 static void a7xx_get_shader_block(struct msm_gpu *gpu,
890 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
900 gpu_rmw(gpu, REG_A7XX_SP_DBG_CNTL, GENMASK(1, 0), 3);
921 if (a6xx_crashdumper_run(gpu, dumper))
930 gpu_rmw(gpu, REG_A7XX_SP_DBG_CNTL, GENMASK(1, 0), 0);
934 static void a6xx_get_shaders(struct msm_gpu *gpu,
949 a6xx_get_shader_block(gpu, a6xx_state, &a6xx_shader_blocks[i],
953 static void a7xx_get_shaders(struct msm_gpu *gpu,
957 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
983 a7xx_get_shader_block(gpu, a6xx_state, &shader_blocks[i],
988 static void a6xx_get_crashdumper_hlsq_registers(struct msm_gpu *gpu,
1017 if (a6xx_crashdumper_run(gpu, dumper))
1026 static void a6xx_get_crashdumper_registers(struct msm_gpu *gpu,
1038 if (!adreno_is_a660_family(to_adreno_gpu(gpu)) &&
1060 if (a6xx_crashdumper_run(gpu, dumper))
1068 static void a7xx_get_crashdumper_registers(struct msm_gpu *gpu,
1097 if (a6xx_crashdumper_run(gpu, dumper))
1107 static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu,
1115 if (!adreno_is_a660_family(to_adreno_gpu(gpu)) &&
1132 obj->data[index++] = gpu_read(gpu,
1137 static void a7xx_get_ahb_gpu_registers(struct msm_gpu *gpu,
1157 obj->data[index++] = gpu_read(gpu, regs[i] + j);
1161 static void a7xx_get_ahb_gpu_reglist(struct msm_gpu *gpu,
1167 gpu_write(gpu, regs->sel->host_reg, regs->sel->val);
1169 a7xx_get_ahb_gpu_registers(gpu, a6xx_state, regs->regs, obj);
1173 static void _a6xx_get_gmu_registers(struct msm_gpu *gpu,
1179 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1210 static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
1213 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1225 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[0],
1227 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1],
1231 _a6xx_get_gmu_registers(gpu, a6xx_state, &a621_gpucc_reg,
1234 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gpucc_reg,
1241 gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
1243 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2],
1270 static void a6xx_snapshot_gmu_hfi_history(struct msm_gpu *gpu,
1273 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1291 static void a6xx_get_registers(struct msm_gpu *gpu,
1299 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1309 a6xx_get_ahb_gpu_registers(gpu,
1314 a6xx_get_ahb_gpu_registers(gpu,
1318 a6xx_get_ahb_gpu_registers(gpu,
1330 a6xx_get_ahb_gpu_registers(gpu,
1337 a6xx_get_crashdumper_registers(gpu,
1343 a6xx_get_crashdumper_hlsq_registers(gpu,
1351 static void a7xx_get_registers(struct msm_gpu *gpu,
1355 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1395 a7xx_get_ahb_gpu_registers(gpu, a6xx_state, pre_crashdumper_regs,
1399 a7xx_get_ahb_gpu_reglist(gpu,
1406 a7xx_get_crashdumper_registers(gpu,
1412 static void a7xx_get_post_crashdumper_registers(struct msm_gpu *gpu,
1415 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1421 a7xx_get_ahb_gpu_registers(gpu,
1426 static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu)
1429 return gpu_read(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2) >> 14;
1432 static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu)
1439 gpu_write(gpu, REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 0x70d3);
1441 return 4 * (gpu_read(gpu, REG_A6XX_CP_SQE_UCODE_DBG_DATA) >> 20);
1445 static void a6xx_get_indexed_regs(struct msm_gpu *gpu,
1455 count = indexed->count_fn(gpu);
1463 gpu_write(gpu, indexed->addr, 0);
1467 obj->data[i] = gpu_read(gpu, indexed->data);
1470 static void a6xx_get_indexed_registers(struct msm_gpu *gpu,
1483 a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_indexed_reglist[i],
1486 if (adreno_is_a650_family(to_adreno_gpu(gpu))) {
1489 val = gpu_read(gpu, REG_A6XX_CP_CHICKEN_DBG);
1490 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, val | 4);
1493 a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_cp_mempool_indexed,
1496 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, val);
1502 mempool_size = gpu_read(gpu, REG_A6XX_CP_MEM_POOL_SIZE);
1503 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 0);
1506 a6xx_get_indexed_regs(gpu, a6xx_state, &a6xx_cp_mempool_indexed,
1516 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, mempool_size);
1521 static void a7xx_get_indexed_registers(struct msm_gpu *gpu,
1524 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1549 a6xx_get_indexed_regs(gpu, a6xx_state, &indexed_regs[i],
1552 gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, 0, BIT(2));
1553 gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, 0, BIT(2));
1557 a6xx_get_indexed_regs(gpu, a6xx_state, &a7xx_cp_bv_mempool_indexed[i],
1560 gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(2), 0);
1561 gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, BIT(2), 0);
1565 struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
1568 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1572 bool stalled = !!(gpu_read(gpu, REG_A6XX_RBBM_STATUS3) &
1581 adreno_gpu_state_get(gpu, &a6xx_state->base);
1584 a6xx_get_gmu_registers(gpu, a6xx_state);
1590 a6xx_snapshot_gmu_hfi_history(gpu, a6xx_state);
1599 a7xx_get_indexed_registers(gpu, a6xx_state);
1601 a6xx_get_indexed_registers(gpu, a6xx_state);
1609 if (!stalled && !gpu->needs_hw_init &&
1610 !a6xx_crashdumper_init(gpu, &_dumper)) {
1615 a7xx_get_registers(gpu, a6xx_state, dumper);
1618 a7xx_get_shaders(gpu, a6xx_state, dumper);
1619 a7xx_get_clusters(gpu, a6xx_state, dumper);
1620 a7xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
1622 msm_gem_kernel_put(dumper->bo, gpu->aspace);
1625 a7xx_get_post_crashdumper_registers(gpu, a6xx_state);
1627 a6xx_get_registers(gpu, a6xx_state, dumper);
1630 a6xx_get_shaders(gpu, a6xx_state, dumper);
1631 a6xx_get_clusters(gpu, a6xx_state, dumper);
1632 a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
1634 msm_gem_kernel_put(dumper->bo, gpu->aspace);
1639 a6xx_get_debugbus(gpu, a6xx_state);
1641 a6xx_state->gpu_initialized = !gpu->needs_hw_init;
1953 void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
1956 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1964 drm_printf(p, "gpu-initialized: %d\n", a6xx_state->gpu_initialized);
1966 adreno_show(gpu, state, p);