xref: /linux/drivers/staging/media/atomisp/pci/isp2400_input_system_local.h (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Support for Intel Camera Imaging ISP subsystem.
4  * Copyright (c) 2010-2015, Intel Corporation.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  */
15 
16 #ifndef __INPUT_SYSTEM_2400_LOCAL_H_INCLUDED__
17 #define __INPUT_SYSTEM_2400_LOCAL_H_INCLUDED__
18 
19 #include "input_system_defs.h"		/* HIVE_ISYS_GPREG_MULTICAST_A_IDX,... */
20 
21 /*
22  * _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX,
23  * _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX,...
24  */
25 #include "css_receiver_2400_defs.h"
26 
27 #include "isp_capture_defs.h"
28 
29 #include "isp_acquisition_defs.h"
30 #include "input_system_ctrl_defs.h"
31 
32 struct target_cfg2400_s {
33 	input_switch_cfg_channel_t		input_switch_channel_cfg;
34 	target_isp_cfg_t	target_isp_cfg;
35 	target_sp_cfg_t		target_sp_cfg;
36 	target_strm2mem_cfg_t	target_strm2mem_cfg;
37 };
38 
39 // Configuration of a channel.
40 struct channel_cfg_s {
41 	u32		ch_id;
42 	backend_channel_cfg_t	backend_ch;
43 	input_system_source_t	source_type;
44 	source_cfg_t		source_cfg;
45 	target_cfg2400_t	target_cfg;
46 };
47 
48 // Complete configuration for input system.
49 struct input_system_cfg2400_s {
50 	input_system_source_t source_type;
51 	input_system_config_flags_t	source_type_flags;
52 	//channel_cfg_t		channel[N_CHANNELS];
53 	input_system_config_flags_t	ch_flags[N_CHANNELS];
54 	//  This is the place where the buffers' settings are collected, as given.
55 	csi_cfg_t			csi_value[N_CSI_PORTS];
56 	input_system_config_flags_t	csi_flags[N_CSI_PORTS];
57 
58 	// Possible another struct for ib.
59 	// This buffers set at the end, based on the all configurations.
60 	isp2400_ib_buffer_t			csi_buffer[N_CSI_PORTS];
61 	input_system_config_flags_t	csi_buffer_flags[N_CSI_PORTS];
62 	isp2400_ib_buffer_t			acquisition_buffer_unique;
63 	input_system_config_flags_t	acquisition_buffer_unique_flags;
64 	u32			unallocated_ib_mem_words; // Used for check.DEFAULT = IB_CAPACITY_IN_WORDS.
65 	//uint32_t			acq_allocated_ib_mem_words;
66 
67 	input_system_connection_t		multicast[N_CSI_PORTS];
68 	input_system_multiplex_t		multiplexer;
69 	input_system_config_flags_t		multiplexer_flags;
70 
71 	tpg_cfg_t			tpg_value;
72 	input_system_config_flags_t	tpg_flags;
73 	prbs_cfg_t			prbs_value;
74 	input_system_config_flags_t	prbs_flags;
75 	gpfifo_cfg_t		gpfifo_value;
76 	input_system_config_flags_t	gpfifo_flags;
77 
78 	input_switch_cfg_t		input_switch_cfg;
79 
80 	target_isp_cfg_t		target_isp[N_CHANNELS];
81 	input_system_config_flags_t	target_isp_flags[N_CHANNELS];
82 	target_sp_cfg_t			target_sp[N_CHANNELS];
83 	input_system_config_flags_t	target_sp_flags[N_CHANNELS];
84 	target_strm2mem_cfg_t	target_strm2mem[N_CHANNELS];
85 	input_system_config_flags_t	target_strm2mem_flags[N_CHANNELS];
86 
87 	input_system_config_flags_t		session_flags;
88 
89 };
90 
91 /*
92  * For each MIPI port
93  */
94 #define _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX			_HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX
95 #define _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX			_HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX
96 #define _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX			_HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX
97 #define _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX		    _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX
98 #define _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX			_HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX
99 /* new regs for each MIPI port w.r.t. 2300 */
100 #define _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX       _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX
101 #define _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX            _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX
102 #define _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX              _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX
103 
104 /* _HRT_CSS_RECEIVER_2400_COMP_FORMAT_REG_IDX is not defined per MIPI port but per channel */
105 /* _HRT_CSS_RECEIVER_2400_COMP_PREDICT_REG_IDX is not defined per MIPI port but per channel */
106 #define _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX        _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX
107 #define _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX      _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX
108 #define _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX      _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX
109 #define _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX        _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX
110 #define _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX        _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX
111 #define _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX        _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX
112 #define _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX			_HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX
113 #define _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX           _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX
114 #define _HRT_CSS_RECEIVER_RAW18_REG_IDX                 _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX
115 #define _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX            _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX
116 #define _HRT_CSS_RECEIVER_RAW16_REG_IDX                 _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX
117 
118 /* Previously MIPI port regs, now 2x2 logical channel regs */
119 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG0_IDX		_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX
120 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG1_IDX		_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX
121 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG0_IDX		_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX
122 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG1_IDX		_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX
123 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG0_IDX		_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX
124 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG1_IDX		_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX
125 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG0_IDX		_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX
126 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG1_IDX		_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX
127 
128 /* Second backend is at offset 0x0700 w.r.t. the first port at offset 0x0100 */
129 #define _HRT_CSS_BE_OFFSET                              448
130 #define _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX        (_HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX + _HRT_CSS_BE_OFFSET)
131 #define _HRT_CSS_RECEIVER_BE_SRST_REG_IDX               (_HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX + _HRT_CSS_BE_OFFSET)
132 #define _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX            (_HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX + _HRT_CSS_BE_OFFSET)
133 #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX       (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX + _HRT_CSS_BE_OFFSET)
134 #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX       (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX + _HRT_CSS_BE_OFFSET)
135 #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX       (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX + _HRT_CSS_BE_OFFSET)
136 #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX       (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX + _HRT_CSS_BE_OFFSET)
137 #define _HRT_CSS_RECEIVER_BE_SEL_REG_IDX                (_HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX + _HRT_CSS_BE_OFFSET)
138 #define _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX       (_HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET)
139 #define _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX       (_HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET)
140 #define _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX         (_HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX + _HRT_CSS_BE_OFFSET)
141 #define _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX         (_HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX + _HRT_CSS_BE_OFFSET)
142 #define _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX          (_HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX + _HRT_CSS_BE_OFFSET)
143 
144 #define _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT		_HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT
145 #define _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT		_HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT
146 #define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT	_HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT
147 #define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT	_HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT
148 #define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT		_HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT
149 #define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT	_HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT
150 #define _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT		_HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT
151 #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT	_HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT
152 #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT	_HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT
153 #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT	_HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT
154 #define _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT		_HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT
155 #define _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT		_HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT
156 #define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT	_HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT
157 #define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT	_HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT
158 #define _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT		_HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT
159 #define _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT		_HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT
160 #define _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT		_HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT
161 
162 #define _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX		_HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX
163 #define	_HRT_CSS_RECEIVER_DATA_TIMEOUT_IDX		_HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX
164 #define	_HRT_CSS_RECEIVER_DATA_TIMEOUT_BITS		_HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS
165 
166 typedef enum {
167 	MIPI_FORMAT_2400_RGB888 = 0,
168 	MIPI_FORMAT_2400_RGB555,
169 	MIPI_FORMAT_2400_RGB444,
170 	MIPI_FORMAT_2400_RGB565,
171 	MIPI_FORMAT_2400_RGB666,
172 	MIPI_FORMAT_2400_RAW8,		/* 5 */
173 	MIPI_FORMAT_2400_RAW10,
174 	MIPI_FORMAT_2400_RAW6,
175 	MIPI_FORMAT_2400_RAW7,
176 	MIPI_FORMAT_2400_RAW12,
177 	MIPI_FORMAT_2400_RAW14,		/* 10 */
178 	MIPI_FORMAT_2400_YUV420_8,
179 	MIPI_FORMAT_2400_YUV420_10,
180 	MIPI_FORMAT_2400_YUV422_8,
181 	MIPI_FORMAT_2400_YUV422_10,
182 	MIPI_FORMAT_2400_CUSTOM0,	/* 15 */
183 	MIPI_FORMAT_2400_YUV420_8_LEGACY,
184 	MIPI_FORMAT_2400_EMBEDDED,
185 	MIPI_FORMAT_2400_CUSTOM1,
186 	MIPI_FORMAT_2400_CUSTOM2,
187 	MIPI_FORMAT_2400_CUSTOM3,	/* 20 */
188 	MIPI_FORMAT_2400_CUSTOM4,
189 	MIPI_FORMAT_2400_CUSTOM5,
190 	MIPI_FORMAT_2400_CUSTOM6,
191 	MIPI_FORMAT_2400_CUSTOM7,
192 	MIPI_FORMAT_2400_YUV420_8_SHIFT,	/* 25 */
193 	MIPI_FORMAT_2400_YUV420_10_SHIFT,
194 	MIPI_FORMAT_2400_RAW16,
195 	MIPI_FORMAT_2400_RAW18,
196 	N_MIPI_FORMAT_2400,
197 } mipi_format_2400_t;
198 
199 #define N_MIPI_FORMAT_CUSTOM	8
200 
201 /* The number of stores for compressed format types */
202 #define	N_MIPI_COMPRESSOR_CONTEXT	(N_RX_CHANNEL_ID * N_MIPI_FORMAT_CUSTOM)
203 
204 typedef enum {
205 	RX_IRQ_INFO_BUFFER_OVERRUN   = 1UL << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT,
206 	RX_IRQ_INFO_INIT_TIMEOUT     = 1UL << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT,
207 	RX_IRQ_INFO_ENTER_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT,
208 	RX_IRQ_INFO_EXIT_SLEEP_MODE  = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT,
209 	RX_IRQ_INFO_ECC_CORRECTED    = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT,
210 	RX_IRQ_INFO_ERR_SOT          = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT,
211 	RX_IRQ_INFO_ERR_SOT_SYNC     = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT,
212 	RX_IRQ_INFO_ERR_CONTROL      = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT,
213 	RX_IRQ_INFO_ERR_ECC_DOUBLE   = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT,
214 	/*	RX_IRQ_INFO_NO_ERR           = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT, */
215 	RX_IRQ_INFO_ERR_CRC          = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT,
216 	RX_IRQ_INFO_ERR_UNKNOWN_ID   = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT,
217 	RX_IRQ_INFO_ERR_FRAME_SYNC   = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT,
218 	RX_IRQ_INFO_ERR_FRAME_DATA   = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT,
219 	RX_IRQ_INFO_ERR_DATA_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT,
220 	RX_IRQ_INFO_ERR_UNKNOWN_ESC  = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT,
221 	RX_IRQ_INFO_ERR_LINE_SYNC    = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT,
222 }  rx_irq_info_t;
223 
224 /* NOTE: The base has already an offset of 0x0100 */
225 static const hrt_address __maybe_unused MIPI_PORT_OFFSET[N_MIPI_PORT_ID] = {
226 	0x00000000UL,
227 	0x00000100UL,
228 	0x00000200UL
229 };
230 
231 static const hrt_address __maybe_unused SUB_SYSTEM_OFFSET[N_SUB_SYSTEM_ID] = {
232 	0x00001000UL,
233 	0x00002000UL,
234 	0x00003000UL,
235 	0x00004000UL,
236 	0x00005000UL,
237 	0x00009000UL,
238 	0x0000A000UL,
239 	0x0000B000UL,
240 	0x0000C000UL
241 };
242 
243 #endif /* __INPUT_SYSTEM_LOCAL_H_INCLUDED__ */
244