1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * core.h - DesignWare USB3 DRD Core Header
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #ifndef __DRIVERS_USB_DWC3_CORE_H
12 #define __DRIVERS_USB_DWC3_CORE_H
13
14 #include <linux/device.h>
15 #include <linux/spinlock.h>
16 #include <linux/mutex.h>
17 #include <linux/ioport.h>
18 #include <linux/list.h>
19 #include <linux/bitops.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/mm.h>
22 #include <linux/debugfs.h>
23 #include <linux/wait.h>
24 #include <linux/workqueue.h>
25
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/gadget.h>
28 #include <linux/usb/otg.h>
29 #include <linux/usb/role.h>
30 #include <linux/ulpi/interface.h>
31
32 #include <linux/phy/phy.h>
33
34 #include <linux/power_supply.h>
35
36 /*
37 * DWC3 Multiport controllers support up to 15 High-Speed PHYs
38 * and 4 SuperSpeed PHYs.
39 */
40 #define DWC3_USB2_MAX_PORTS 15
41 #define DWC3_USB3_MAX_PORTS 4
42
43 #define DWC3_MSG_MAX 500
44
45 /* Global constants */
46 #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
47 #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
48 #define DWC3_EP0_SETUP_SIZE 512
49 #define DWC3_ENDPOINTS_NUM 32
50 #define DWC3_XHCI_RESOURCES_NUM 2
51 #define DWC3_ISOC_MAX_RETRIES 5
52
53 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
54 #define DWC3_EVENT_BUFFERS_SIZE 4096
55 #define DWC3_EVENT_TYPE_MASK 0xfe
56
57 #define DWC3_EVENT_TYPE_DEV 0
58 #define DWC3_EVENT_TYPE_CARKIT 3
59 #define DWC3_EVENT_TYPE_I2C 4
60
61 #define DWC3_DEVICE_EVENT_DISCONNECT 0
62 #define DWC3_DEVICE_EVENT_RESET 1
63 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
64 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
65 #define DWC3_DEVICE_EVENT_WAKEUP 4
66 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
67 #define DWC3_DEVICE_EVENT_SUSPEND 6
68 #define DWC3_DEVICE_EVENT_SOF 7
69 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
70 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
71 #define DWC3_DEVICE_EVENT_OVERFLOW 11
72
73 /* Controller's role while using the OTG block */
74 #define DWC3_OTG_ROLE_IDLE 0
75 #define DWC3_OTG_ROLE_HOST 1
76 #define DWC3_OTG_ROLE_DEVICE 2
77
78 #define DWC3_GEVNTCOUNT_MASK 0xfffc
79 #define DWC3_GEVNTCOUNT_EHB BIT(31)
80 #define DWC3_GSNPSID_MASK 0xffff0000
81 #define DWC3_GSNPSREV_MASK 0xffff
82 #define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16)
83
84 /* DWC3 registers memory space boundaries */
85 #define DWC3_XHCI_REGS_START 0x0
86 #define DWC3_XHCI_REGS_END 0x7fff
87 #define DWC3_GLOBALS_REGS_START 0xc100
88 #define DWC3_GLOBALS_REGS_END 0xc6ff
89 #define DWC3_DEVICE_REGS_START 0xc700
90 #define DWC3_DEVICE_REGS_END 0xcbff
91 #define DWC3_OTG_REGS_START 0xcc00
92 #define DWC3_OTG_REGS_END 0xccff
93
94 #define DWC3_RTK_RTD_GLOBALS_REGS_START 0x8100
95
96 /* Global Registers */
97 #define DWC3_GSBUSCFG0 0xc100
98 #define DWC3_GSBUSCFG1 0xc104
99 #define DWC3_GTXTHRCFG 0xc108
100 #define DWC3_GRXTHRCFG 0xc10c
101 #define DWC3_GCTL 0xc110
102 #define DWC3_GEVTEN 0xc114
103 #define DWC3_GSTS 0xc118
104 #define DWC3_GUCTL1 0xc11c
105 #define DWC3_GSNPSID 0xc120
106 #define DWC3_GGPIO 0xc124
107 #define DWC3_GUID 0xc128
108 #define DWC3_GUCTL 0xc12c
109 #define DWC3_GBUSERRADDR0 0xc130
110 #define DWC3_GBUSERRADDR1 0xc134
111 #define DWC3_GPRTBIMAP0 0xc138
112 #define DWC3_GPRTBIMAP1 0xc13c
113 #define DWC3_GHWPARAMS0 0xc140
114 #define DWC3_GHWPARAMS1 0xc144
115 #define DWC3_GHWPARAMS2 0xc148
116 #define DWC3_GHWPARAMS3 0xc14c
117 #define DWC3_GHWPARAMS4 0xc150
118 #define DWC3_GHWPARAMS5 0xc154
119 #define DWC3_GHWPARAMS6 0xc158
120 #define DWC3_GHWPARAMS7 0xc15c
121 #define DWC3_GDBGFIFOSPACE 0xc160
122 #define DWC3_GDBGLTSSM 0xc164
123 #define DWC3_GDBGBMU 0xc16c
124 #define DWC3_GDBGLSPMUX 0xc170
125 #define DWC3_GDBGLSP 0xc174
126 #define DWC3_GDBGEPINFO0 0xc178
127 #define DWC3_GDBGEPINFO1 0xc17c
128 #define DWC3_GPRTBIMAP_HS0 0xc180
129 #define DWC3_GPRTBIMAP_HS1 0xc184
130 #define DWC3_GPRTBIMAP_FS0 0xc188
131 #define DWC3_GPRTBIMAP_FS1 0xc18c
132 #define DWC3_GUCTL2 0xc19c
133
134 #define DWC3_VER_NUMBER 0xc1a0
135 #define DWC3_VER_TYPE 0xc1a4
136
137 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
138 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
139
140 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
141
142 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
143
144 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
145 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
146
147 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
148 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
149 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
150 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
151
152 #define DWC3_GHWPARAMS8 0xc600
153 #define DWC3_GUCTL3 0xc60c
154 #define DWC3_GFLADJ 0xc630
155 #define DWC3_GHWPARAMS9 0xc6e0
156
157 /* Device Registers */
158 #define DWC3_DCFG 0xc700
159 #define DWC3_DCTL 0xc704
160 #define DWC3_DEVTEN 0xc708
161 #define DWC3_DSTS 0xc70c
162 #define DWC3_DGCMDPAR 0xc710
163 #define DWC3_DGCMD 0xc714
164 #define DWC3_DALEPENA 0xc720
165 #define DWC3_DCFG1 0xc740 /* DWC_usb32 only */
166
167 #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
168 #define DWC3_DEPCMDPAR2 0x00
169 #define DWC3_DEPCMDPAR1 0x04
170 #define DWC3_DEPCMDPAR0 0x08
171 #define DWC3_DEPCMD 0x0c
172
173 #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
174
175 /* OTG Registers */
176 #define DWC3_OCFG 0xcc00
177 #define DWC3_OCTL 0xcc04
178 #define DWC3_OEVT 0xcc08
179 #define DWC3_OEVTEN 0xcc0C
180 #define DWC3_OSTS 0xcc10
181
182 #define DWC3_LLUCTL(n) (0xd024 + ((n) * 0x80))
183
184 /* Bit fields */
185
186 /* Global SoC Bus Configuration INCRx Register 0 */
187 #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
188 #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
189 #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
190 #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
191 #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
192 #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
193 #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
194 #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
195 #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
196
197 /* Global SoC Bus Configuration Register: AHB-prot/AXI-cache/OCP-ReqInfo */
198 #define DWC3_GSBUSCFG0_REQINFO(n) (((n) & 0xffff) << 16)
199 #define DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED 0xffffffff
200
201 /* Global Debug LSP MUX Select */
202 #define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */
203 #define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
204 #define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4)
205 #define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf)
206
207 /* Global Debug Queue/FIFO Space Available Register */
208 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
209 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
210 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
211
212 #define DWC3_TXFIFO 0
213 #define DWC3_RXFIFO 1
214 #define DWC3_TXREQQ 2
215 #define DWC3_RXREQQ 3
216 #define DWC3_RXINFOQ 4
217 #define DWC3_PSTATQ 5
218 #define DWC3_DESCFETCHQ 6
219 #define DWC3_EVENTQ 7
220 #define DWC3_AUXEVENTQ 8
221
222 /* Global RX Threshold Configuration Register */
223 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
224 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
225 #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
226
227 /* Global TX Threshold Configuration Register */
228 #define DWC3_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0xff) << 16)
229 #define DWC3_GTXTHRCFG_TXPKTCNT(n) (((n) & 0xf) << 24)
230 #define DWC3_GTXTHRCFG_PKTCNTSEL BIT(29)
231
232 /* Global RX Threshold Configuration Register for DWC_usb31 only */
233 #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
234 #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
235 #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
236 #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
237 #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
238 #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
239 #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
240 #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
241
242 /* Global TX Threshold Configuration Register for DWC_usb31 only */
243 #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
244 #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
245 #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
246 #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
247 #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
248 #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
249 #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
250 #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
251
252 /* Global Configuration Register */
253 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
254 #define DWC3_GCTL_PWRDNSCALE_MASK GENMASK(31, 19)
255 #define DWC3_GCTL_U2RSTECN BIT(16)
256 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
257 #define DWC3_GCTL_CLK_BUS (0)
258 #define DWC3_GCTL_CLK_PIPE (1)
259 #define DWC3_GCTL_CLK_PIPEHALF (2)
260 #define DWC3_GCTL_CLK_MASK (3)
261
262 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
263 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
264 #define DWC3_GCTL_PRTCAP_HOST 1
265 #define DWC3_GCTL_PRTCAP_DEVICE 2
266 #define DWC3_GCTL_PRTCAP_OTG 3
267
268 #define DWC3_GCTL_CORESOFTRESET BIT(11)
269 #define DWC3_GCTL_SOFITPSYNC BIT(10)
270 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
271 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
272 #define DWC3_GCTL_DISSCRAMBLE BIT(3)
273 #define DWC3_GCTL_U2EXIT_LFPS BIT(2)
274 #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
275 #define DWC3_GCTL_DSBLCLKGTNG BIT(0)
276
277 /* Global User Control 1 Register */
278 #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
279 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
280 #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
281 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
282 #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
283 #define DWC3_GUCTL1_PARKMODE_DISABLE_HS BIT(16)
284 #define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10)
285
286 /* Global Status Register */
287 #define DWC3_GSTS_OTG_IP BIT(10)
288 #define DWC3_GSTS_BC_IP BIT(9)
289 #define DWC3_GSTS_ADP_IP BIT(8)
290 #define DWC3_GSTS_HOST_IP BIT(7)
291 #define DWC3_GSTS_DEVICE_IP BIT(6)
292 #define DWC3_GSTS_CSR_TIMEOUT BIT(5)
293 #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
294 #define DWC3_GSTS_CURMOD(n) ((n) & 0x3)
295 #define DWC3_GSTS_CURMOD_DEVICE 0
296 #define DWC3_GSTS_CURMOD_HOST 1
297
298 /* Global USB2 PHY Configuration Register */
299 #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
300 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
301 #define DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV BIT(17)
302 #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
303 #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
304 #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
305 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
306 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
307 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
308 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
309 #define USBTRDTIM_UTMI_8_BIT 9
310 #define USBTRDTIM_UTMI_16_BIT 5
311 #define UTMI_PHYIF_16_BIT 1
312 #define UTMI_PHYIF_8_BIT 0
313
314 /* Global USB2 PHY Vendor Control Register */
315 #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
316 #define DWC3_GUSB2PHYACC_DONE BIT(24)
317 #define DWC3_GUSB2PHYACC_BUSY BIT(23)
318 #define DWC3_GUSB2PHYACC_WRITE BIT(22)
319 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
320 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
321 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
322
323 /* Global USB3 PIPE Control Register */
324 #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
325 #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
326 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
327 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
328 #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
329 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
330 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
331 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
332 #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
333 #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
334 #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
335 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
336 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
337 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
338
339 /* Global TX Fifo Size Register */
340 #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
341 #define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
342 #define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff)
343 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
344
345 /* Global RX Fifo Size Register */
346 #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
347 #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff)
348
349 /* Global Event Size Registers */
350 #define DWC3_GEVNTSIZ_INTMASK BIT(31)
351 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
352
353 /* Global HWPARAMS0 Register */
354 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
355 #define DWC3_GHWPARAMS0_MODE_GADGET 0
356 #define DWC3_GHWPARAMS0_MODE_HOST 1
357 #define DWC3_GHWPARAMS0_MODE_DRD 2
358 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
359 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
360 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
361 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
362 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
363
364 /* Global HWPARAMS1 Register */
365 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
366 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
367 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
368 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
369 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
370 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
371 #define DWC3_GHWPARAMS1_ENDBC BIT(31)
372
373 /* Global HWPARAMS3 Register */
374 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
375 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
376 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
377 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
378 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
379 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
380 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
381 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
382 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
383 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
384 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
385 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
386
387 /* Global HWPARAMS4 Register */
388 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
389 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
390
391 /* Global HWPARAMS6 Register */
392 #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
393 #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
394 #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
395 #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
396 #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
397 #define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
398
399 /* DWC_usb32 only */
400 #define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8))
401
402 /* Global HWPARAMS7 Register */
403 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
404 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
405
406 /* Global HWPARAMS9 Register */
407 #define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0)
408 #define DWC3_GHWPARAMS9_DEV_MST BIT(1)
409
410 /* Global Frame Length Adjustment Register */
411 #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
412 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
413 #define DWC3_GFLADJ_REFCLK_FLADJ_MASK GENMASK(21, 8)
414 #define DWC3_GFLADJ_REFCLK_LPM_SEL BIT(23)
415 #define DWC3_GFLADJ_240MHZDECR GENMASK(30, 24)
416 #define DWC3_GFLADJ_240MHZDECR_PLS1 BIT(31)
417
418 /* Global User Control Register*/
419 #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000
420 #define DWC3_GUCTL_REFCLKPER_SEL 22
421
422 /* Global User Control Register 2 */
423 #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
424 #define DWC3_GUCTL2_LC_TIMER BIT(19)
425
426 /* Global User Control Register 3 */
427 #define DWC3_GUCTL3_SPLITDISABLE BIT(14)
428 #define DWC3_GUCTL3_USB20_RETRY_DISABLE BIT(16)
429
430 /* Device Configuration Register */
431 #define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */
432
433 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
434 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
435
436 #define DWC3_DCFG_SPEED_MASK (7 << 0)
437 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
438 #define DWC3_DCFG_SUPERSPEED (4 << 0)
439 #define DWC3_DCFG_HIGHSPEED (0 << 0)
440 #define DWC3_DCFG_FULLSPEED BIT(0)
441
442 #define DWC3_DCFG_NUMP_SHIFT 17
443 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
444 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
445 #define DWC3_DCFG_LPM_CAP BIT(22)
446 #define DWC3_DCFG_IGNSTRMPP BIT(23)
447
448 /* Device Control Register */
449 #define DWC3_DCTL_RUN_STOP BIT(31)
450 #define DWC3_DCTL_CSFTRST BIT(30)
451 #define DWC3_DCTL_LSFTRST BIT(29)
452
453 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
454 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
455
456 #define DWC3_DCTL_APPL1RES BIT(23)
457
458 /* These apply for core versions 1.87a and earlier */
459 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
460 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
461 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
462 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
463 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
464 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
465 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
466
467 /* These apply for core versions 1.94a and later */
468 #define DWC3_DCTL_NYET_THRES_MASK (0xf << 20)
469 #define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20)
470
471 #define DWC3_DCTL_KEEP_CONNECT BIT(19)
472 #define DWC3_DCTL_L1_HIBER_EN BIT(18)
473 #define DWC3_DCTL_CRS BIT(17)
474 #define DWC3_DCTL_CSS BIT(16)
475
476 #define DWC3_DCTL_INITU2ENA BIT(12)
477 #define DWC3_DCTL_ACCEPTU2ENA BIT(11)
478 #define DWC3_DCTL_INITU1ENA BIT(10)
479 #define DWC3_DCTL_ACCEPTU1ENA BIT(9)
480 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
481
482 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
483 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
484
485 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
486 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
487 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
488 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
489 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
490 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
491 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
492
493 /* Device Event Enable Register */
494 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
495 #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
496 #define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
497 #define DWC3_DEVTEN_ERRTICERREN BIT(9)
498 #define DWC3_DEVTEN_SOFEN BIT(7)
499 #define DWC3_DEVTEN_U3L2L1SUSPEN BIT(6)
500 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
501 #define DWC3_DEVTEN_WKUPEVTEN BIT(4)
502 #define DWC3_DEVTEN_ULSTCNGEN BIT(3)
503 #define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
504 #define DWC3_DEVTEN_USBRSTEN BIT(1)
505 #define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
506
507 #define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */
508
509 /* Device Status Register */
510 #define DWC3_DSTS_DCNRD BIT(29)
511
512 /* This applies for core versions 1.87a and earlier */
513 #define DWC3_DSTS_PWRUPREQ BIT(24)
514
515 /* These apply for core versions 1.94a and later */
516 #define DWC3_DSTS_RSS BIT(25)
517 #define DWC3_DSTS_SSS BIT(24)
518
519 #define DWC3_DSTS_COREIDLE BIT(23)
520 #define DWC3_DSTS_DEVCTRLHLT BIT(22)
521
522 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
523 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
524
525 #define DWC3_DSTS_RXFIFOEMPTY BIT(17)
526
527 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
528 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
529
530 #define DWC3_DSTS_CONNECTSPD (7 << 0)
531
532 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
533 #define DWC3_DSTS_SUPERSPEED (4 << 0)
534 #define DWC3_DSTS_HIGHSPEED (0 << 0)
535 #define DWC3_DSTS_FULLSPEED BIT(0)
536
537 /* Device Generic Command Register */
538 #define DWC3_DGCMD_SET_LMP 0x01
539 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
540 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
541
542 /* These apply for core versions 1.94a and later */
543 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
544 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
545
546 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
547 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
548 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
549 #define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d
550 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
551 #define DWC3_DGCMD_DEV_NOTIFICATION 0x07
552
553 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
554 #define DWC3_DGCMD_CMDACT BIT(10)
555 #define DWC3_DGCMD_CMDIOC BIT(8)
556
557 /* Device Generic Command Parameter Register */
558 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
559 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
560 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
561 #define DWC3_DGCMDPAR_TX_FIFO BIT(5)
562 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
563 #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
564 #define DWC3_DGCMDPAR_DN_FUNC_WAKE BIT(0)
565 #define DWC3_DGCMDPAR_INTF_SEL(n) ((n) << 4)
566
567 /* Device Endpoint Command Register */
568 #define DWC3_DEPCMD_PARAM_SHIFT 16
569 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
570 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
571 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
572 #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
573 #define DWC3_DEPCMD_CLEARPENDIN BIT(11)
574 #define DWC3_DEPCMD_CMDACT BIT(10)
575 #define DWC3_DEPCMD_CMDIOC BIT(8)
576
577 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
578 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
579 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
580 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
581 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
582 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
583 /* This applies for core versions 1.90a and earlier */
584 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
585 /* This applies for core versions 1.94a and later */
586 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
587 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
588 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
589
590 #define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
591
592 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
593 #define DWC3_DALEPENA_EP(n) BIT(n)
594
595 /* DWC_usb32 DCFG1 config */
596 #define DWC3_DCFG1_DIS_MST_ENH BIT(1)
597
598 #define DWC3_DEPCMD_TYPE_CONTROL 0
599 #define DWC3_DEPCMD_TYPE_ISOC 1
600 #define DWC3_DEPCMD_TYPE_BULK 2
601 #define DWC3_DEPCMD_TYPE_INTR 3
602
603 #define DWC3_DEV_IMOD_COUNT_SHIFT 16
604 #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
605 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
606 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
607
608 /* OTG Configuration Register */
609 #define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
610 #define DWC3_OCFG_HIBDISMASK BIT(4)
611 #define DWC3_OCFG_SFTRSTMASK BIT(3)
612 #define DWC3_OCFG_OTGVERSION BIT(2)
613 #define DWC3_OCFG_HNPCAP BIT(1)
614 #define DWC3_OCFG_SRPCAP BIT(0)
615
616 /* OTG CTL Register */
617 #define DWC3_OCTL_OTG3GOERR BIT(7)
618 #define DWC3_OCTL_PERIMODE BIT(6)
619 #define DWC3_OCTL_PRTPWRCTL BIT(5)
620 #define DWC3_OCTL_HNPREQ BIT(4)
621 #define DWC3_OCTL_SESREQ BIT(3)
622 #define DWC3_OCTL_TERMSELIDPULSE BIT(2)
623 #define DWC3_OCTL_DEVSETHNPEN BIT(1)
624 #define DWC3_OCTL_HSTSETHNPEN BIT(0)
625
626 /* OTG Event Register */
627 #define DWC3_OEVT_DEVICEMODE BIT(31)
628 #define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
629 #define DWC3_OEVT_DEVRUNSTPSET BIT(26)
630 #define DWC3_OEVT_HIBENTRY BIT(25)
631 #define DWC3_OEVT_CONIDSTSCHNG BIT(24)
632 #define DWC3_OEVT_HRRCONFNOTIF BIT(23)
633 #define DWC3_OEVT_HRRINITNOTIF BIT(22)
634 #define DWC3_OEVT_ADEVIDLE BIT(21)
635 #define DWC3_OEVT_ADEVBHOSTEND BIT(20)
636 #define DWC3_OEVT_ADEVHOST BIT(19)
637 #define DWC3_OEVT_ADEVHNPCHNG BIT(18)
638 #define DWC3_OEVT_ADEVSRPDET BIT(17)
639 #define DWC3_OEVT_ADEVSESSENDDET BIT(16)
640 #define DWC3_OEVT_BDEVBHOSTEND BIT(11)
641 #define DWC3_OEVT_BDEVHNPCHNG BIT(10)
642 #define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
643 #define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
644 #define DWC3_OEVT_BSESSVLD BIT(3)
645 #define DWC3_OEVT_HSTNEGSTS BIT(2)
646 #define DWC3_OEVT_SESREQSTS BIT(1)
647 #define DWC3_OEVT_ERROR BIT(0)
648
649 /* OTG Event Enable Register */
650 #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
651 #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
652 #define DWC3_OEVTEN_HIBENTRYEN BIT(25)
653 #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
654 #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
655 #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
656 #define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
657 #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
658 #define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
659 #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
660 #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
661 #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
662 #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
663 #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
664 #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
665 #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
666
667 /* OTG Status Register */
668 #define DWC3_OSTS_DEVRUNSTP BIT(13)
669 #define DWC3_OSTS_XHCIRUNSTP BIT(12)
670 #define DWC3_OSTS_PERIPHERALSTATE BIT(4)
671 #define DWC3_OSTS_XHCIPRTPOWER BIT(3)
672 #define DWC3_OSTS_BSESVLD BIT(2)
673 #define DWC3_OSTS_VBUSVLD BIT(1)
674 #define DWC3_OSTS_CONIDSTS BIT(0)
675
676 /* Force Gen1 speed on Gen2 link */
677 #define DWC3_LLUCTL_FORCE_GEN1 BIT(10)
678
679 /* Structures */
680
681 struct dwc3_trb;
682
683 /**
684 * struct dwc3_event_buffer - Software event buffer representation
685 * @buf: _THE_ buffer
686 * @cache: The buffer cache used in the threaded interrupt
687 * @length: size of this buffer
688 * @lpos: event offset
689 * @count: cache of last read event count register
690 * @flags: flags related to this event buffer
691 * @dma: dma_addr_t
692 * @dwc: pointer to DWC controller
693 */
694 struct dwc3_event_buffer {
695 void *buf;
696 void *cache;
697 unsigned int length;
698 unsigned int lpos;
699 unsigned int count;
700 unsigned int flags;
701
702 #define DWC3_EVENT_PENDING BIT(0)
703
704 dma_addr_t dma;
705
706 struct dwc3 *dwc;
707 };
708
709 #define DWC3_EP_FLAG_STALLED BIT(0)
710 #define DWC3_EP_FLAG_WEDGED BIT(1)
711
712 #define DWC3_EP_DIRECTION_TX true
713 #define DWC3_EP_DIRECTION_RX false
714
715 #define DWC3_TRB_NUM 256
716
717 /**
718 * struct dwc3_ep - device side endpoint representation
719 * @endpoint: usb endpoint
720 * @nostream_work: work for handling bulk NoStream
721 * @cancelled_list: list of cancelled requests for this endpoint
722 * @pending_list: list of pending requests for this endpoint
723 * @started_list: list of started requests on this endpoint
724 * @regs: pointer to first endpoint register
725 * @trb_pool: array of transaction buffers
726 * @trb_pool_dma: dma address of @trb_pool
727 * @trb_enqueue: enqueue 'pointer' into TRB array
728 * @trb_dequeue: dequeue 'pointer' into TRB array
729 * @dwc: pointer to DWC controller
730 * @saved_state: ep state saved during hibernation
731 * @flags: endpoint flags (wedged, stalled, ...)
732 * @number: endpoint number (1 - 15)
733 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
734 * @resource_index: Resource transfer index
735 * @frame_number: set to the frame number we want this transfer to start (ISOC)
736 * @interval: the interval on which the ISOC transfer is started
737 * @name: a human readable name e.g. ep1out-bulk
738 * @direction: true for TX, false for RX
739 * @stream_capable: true when streams are enabled
740 * @combo_num: the test combination BIT[15:14] of the frame number to test
741 * isochronous START TRANSFER command failure workaround
742 * @start_cmd_status: the status of testing START TRANSFER command with
743 * combo_num = 'b00
744 */
745 struct dwc3_ep {
746 struct usb_ep endpoint;
747 struct delayed_work nostream_work;
748 struct list_head cancelled_list;
749 struct list_head pending_list;
750 struct list_head started_list;
751
752 void __iomem *regs;
753
754 struct dwc3_trb *trb_pool;
755 dma_addr_t trb_pool_dma;
756 struct dwc3 *dwc;
757
758 u32 saved_state;
759 unsigned int flags;
760 #define DWC3_EP_ENABLED BIT(0)
761 #define DWC3_EP_STALL BIT(1)
762 #define DWC3_EP_WEDGE BIT(2)
763 #define DWC3_EP_TRANSFER_STARTED BIT(3)
764 #define DWC3_EP_END_TRANSFER_PENDING BIT(4)
765 #define DWC3_EP_PENDING_REQUEST BIT(5)
766 #define DWC3_EP_DELAY_START BIT(6)
767 #define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7)
768 #define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8)
769 #define DWC3_EP_FORCE_RESTART_STREAM BIT(9)
770 #define DWC3_EP_STREAM_PRIMED BIT(10)
771 #define DWC3_EP_PENDING_CLEAR_STALL BIT(11)
772 #define DWC3_EP_TXFIFO_RESIZED BIT(12)
773 #define DWC3_EP_DELAY_STOP BIT(13)
774 #define DWC3_EP_RESOURCE_ALLOCATED BIT(14)
775
776 /* This last one is specific to EP0 */
777 #define DWC3_EP0_DIR_IN BIT(31)
778
779 /*
780 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
781 * use a u8 type here. If anybody decides to increase number of TRBs to
782 * anything larger than 256 - I can't see why people would want to do
783 * this though - then this type needs to be changed.
784 *
785 * By using u8 types we ensure that our % operator when incrementing
786 * enqueue and dequeue get optimized away by the compiler.
787 */
788 u8 trb_enqueue;
789 u8 trb_dequeue;
790
791 u8 number;
792 u8 type;
793 u8 resource_index;
794 u32 frame_number;
795 u32 interval;
796
797 char name[20];
798
799 unsigned direction:1;
800 unsigned stream_capable:1;
801
802 /* For isochronous START TRANSFER workaround only */
803 u8 combo_num;
804 int start_cmd_status;
805 };
806
807 enum dwc3_phy {
808 DWC3_PHY_UNKNOWN = 0,
809 DWC3_PHY_USB3,
810 DWC3_PHY_USB2,
811 };
812
813 enum dwc3_ep0_next {
814 DWC3_EP0_UNKNOWN = 0,
815 DWC3_EP0_COMPLETE,
816 DWC3_EP0_NRDY_DATA,
817 DWC3_EP0_NRDY_STATUS,
818 };
819
820 enum dwc3_ep0_state {
821 EP0_UNCONNECTED = 0,
822 EP0_SETUP_PHASE,
823 EP0_DATA_PHASE,
824 EP0_STATUS_PHASE,
825 };
826
827 enum dwc3_link_state {
828 /* In SuperSpeed */
829 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
830 DWC3_LINK_STATE_U1 = 0x01,
831 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
832 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
833 DWC3_LINK_STATE_SS_DIS = 0x04,
834 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
835 DWC3_LINK_STATE_SS_INACT = 0x06,
836 DWC3_LINK_STATE_POLL = 0x07,
837 DWC3_LINK_STATE_RECOV = 0x08,
838 DWC3_LINK_STATE_HRESET = 0x09,
839 DWC3_LINK_STATE_CMPLY = 0x0a,
840 DWC3_LINK_STATE_LPBK = 0x0b,
841 DWC3_LINK_STATE_RESET = 0x0e,
842 DWC3_LINK_STATE_RESUME = 0x0f,
843 DWC3_LINK_STATE_MASK = 0x0f,
844 };
845
846 /* TRB Length, PCM and Status */
847 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
848 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
849 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
850 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
851
852 #define DWC3_TRBSTS_OK 0
853 #define DWC3_TRBSTS_MISSED_ISOC 1
854 #define DWC3_TRBSTS_SETUP_PENDING 2
855 #define DWC3_TRB_STS_XFER_IN_PROG 4
856
857 /* TRB Control */
858 #define DWC3_TRB_CTRL_HWO BIT(0)
859 #define DWC3_TRB_CTRL_LST BIT(1)
860 #define DWC3_TRB_CTRL_CHN BIT(2)
861 #define DWC3_TRB_CTRL_CSP BIT(3)
862 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
863 #define DWC3_TRB_CTRL_ISP_IMI BIT(10)
864 #define DWC3_TRB_CTRL_IOC BIT(11)
865 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
866 #define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14)
867
868 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
869 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
870 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
871 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
872 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
873 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
874 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
875 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
876 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
877
878 /**
879 * struct dwc3_trb - transfer request block (hw format)
880 * @bpl: DW0-3
881 * @bph: DW4-7
882 * @size: DW8-B
883 * @ctrl: DWC-F
884 */
885 struct dwc3_trb {
886 u32 bpl;
887 u32 bph;
888 u32 size;
889 u32 ctrl;
890 } __packed;
891
892 /**
893 * struct dwc3_hwparams - copy of HWPARAMS registers
894 * @hwparams0: GHWPARAMS0
895 * @hwparams1: GHWPARAMS1
896 * @hwparams2: GHWPARAMS2
897 * @hwparams3: GHWPARAMS3
898 * @hwparams4: GHWPARAMS4
899 * @hwparams5: GHWPARAMS5
900 * @hwparams6: GHWPARAMS6
901 * @hwparams7: GHWPARAMS7
902 * @hwparams8: GHWPARAMS8
903 * @hwparams9: GHWPARAMS9
904 */
905 struct dwc3_hwparams {
906 u32 hwparams0;
907 u32 hwparams1;
908 u32 hwparams2;
909 u32 hwparams3;
910 u32 hwparams4;
911 u32 hwparams5;
912 u32 hwparams6;
913 u32 hwparams7;
914 u32 hwparams8;
915 u32 hwparams9;
916 };
917
918 /* HWPARAMS0 */
919 #define DWC3_MODE(n) ((n) & 0x7)
920
921 /* HWPARAMS1 */
922 #define DWC3_SPRAM_TYPE(n) (((n) >> 23) & 1)
923 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
924
925 /* HWPARAMS3 */
926 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
927 #define DWC3_NUM_EPS_MASK (0x3f << 12)
928 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
929 (DWC3_NUM_EPS_MASK)) >> 12)
930 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
931 (DWC3_NUM_IN_EPS_MASK)) >> 18)
932
933 /* HWPARAMS6 */
934 #define DWC3_RAM0_DEPTH(n) (((n) & (0xffff0000)) >> 16)
935
936 /* HWPARAMS7 */
937 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
938
939 /* HWPARAMS9 */
940 #define DWC3_MST_CAPABLE(p) (!!((p)->hwparams9 & \
941 DWC3_GHWPARAMS9_DEV_MST))
942
943 /**
944 * struct dwc3_request - representation of a transfer request
945 * @request: struct usb_request to be transferred
946 * @list: a list_head used for request queueing
947 * @dep: struct dwc3_ep owning this request
948 * @start_sg: pointer to the sg which should be queued next
949 * @num_pending_sgs: counter to pending sgs
950 * @remaining: amount of data remaining
951 * @status: internal dwc3 request status tracking
952 * @epnum: endpoint number to which this request refers
953 * @trb: pointer to struct dwc3_trb
954 * @trb_dma: DMA address of @trb
955 * @num_trbs: number of TRBs used by this request
956 * @direction: IN or OUT direction flag
957 * @mapped: true when request has been dma-mapped
958 */
959 struct dwc3_request {
960 struct usb_request request;
961 struct list_head list;
962 struct dwc3_ep *dep;
963 struct scatterlist *start_sg;
964
965 unsigned int num_pending_sgs;
966 unsigned int remaining;
967
968 unsigned int status;
969 #define DWC3_REQUEST_STATUS_QUEUED 0
970 #define DWC3_REQUEST_STATUS_STARTED 1
971 #define DWC3_REQUEST_STATUS_DISCONNECTED 2
972 #define DWC3_REQUEST_STATUS_DEQUEUED 3
973 #define DWC3_REQUEST_STATUS_STALLED 4
974 #define DWC3_REQUEST_STATUS_COMPLETED 5
975 #define DWC3_REQUEST_STATUS_UNKNOWN -1
976
977 u8 epnum;
978 struct dwc3_trb *trb;
979 dma_addr_t trb_dma;
980
981 unsigned int num_trbs;
982
983 unsigned int direction:1;
984 unsigned int mapped:1;
985 };
986
987 /*
988 * struct dwc3_scratchpad_array - hibernation scratchpad array
989 * (format defined by hw)
990 */
991 struct dwc3_scratchpad_array {
992 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
993 };
994
995 /**
996 * struct dwc3 - representation of our controller
997 * @drd_work: workqueue used for role swapping
998 * @ep0_trb: trb which is used for the ctrl_req
999 * @bounce: address of bounce buffer
1000 * @setup_buf: used while precessing STD USB requests
1001 * @ep0_trb_addr: dma address of @ep0_trb
1002 * @bounce_addr: dma address of @bounce
1003 * @ep0_usb_req: dummy req used while handling STD USB requests
1004 * @ep0_in_setup: one control transfer is completed and enter setup phase
1005 * @lock: for synchronizing
1006 * @mutex: for mode switching
1007 * @dev: pointer to our struct device
1008 * @sysdev: pointer to the DMA-capable device
1009 * @xhci: pointer to our xHCI child
1010 * @xhci_resources: struct resources for our @xhci child
1011 * @ev_buf: struct dwc3_event_buffer pointer
1012 * @eps: endpoint array
1013 * @gadget: device side representation of the peripheral controller
1014 * @gadget_driver: pointer to the gadget driver
1015 * @bus_clk: clock for accessing the registers
1016 * @ref_clk: reference clock
1017 * @susp_clk: clock used when the SS phy is in low power (S3) state
1018 * @utmi_clk: clock used for USB2 PHY communication
1019 * @pipe_clk: clock used for USB3 PHY communication
1020 * @reset: reset control
1021 * @regs: base address for our registers
1022 * @regs_size: address space size
1023 * @fladj: frame length adjustment
1024 * @ref_clk_per: reference clock period configuration
1025 * @irq_gadget: peripheral controller's IRQ number
1026 * @otg_irq: IRQ number for OTG IRQs
1027 * @current_otg_role: current role of operation while using the OTG block
1028 * @desired_otg_role: desired role of operation while using the OTG block
1029 * @otg_restart_host: flag that OTG controller needs to restart host
1030 * @u1u2: only used on revisions <1.83a for workaround
1031 * @maximum_speed: maximum speed requested (mainly for testing purposes)
1032 * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count
1033 * @gadget_max_speed: maximum gadget speed requested
1034 * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling
1035 * rate and lane count.
1036 * @ip: controller's ID
1037 * @revision: controller's version of an IP
1038 * @version_type: VERSIONTYPE register contents, a sub release of a revision
1039 * @dr_mode: requested mode of operation
1040 * @current_dr_role: current role of operation when in dual-role mode
1041 * @desired_dr_role: desired role of operation when in dual-role mode
1042 * @edev: extcon handle
1043 * @edev_nb: extcon notifier
1044 * @hsphy_mode: UTMI phy mode, one of following:
1045 * - USBPHY_INTERFACE_MODE_UTMI
1046 * - USBPHY_INTERFACE_MODE_UTMIW
1047 * @role_sw: usb_role_switch handle
1048 * @role_switch_default_mode: default operation mode of controller while
1049 * usb role is USB_ROLE_NONE.
1050 * @usb_psy: pointer to power supply interface.
1051 * @usb2_phy: pointer to USB2 PHY
1052 * @usb3_phy: pointer to USB3 PHY
1053 * @usb2_generic_phy: pointer to array of USB2 PHYs
1054 * @usb3_generic_phy: pointer to array of USB3 PHYs
1055 * @num_usb2_ports: number of USB2 ports
1056 * @num_usb3_ports: number of USB3 ports
1057 * @phys_ready: flag to indicate that PHYs are ready
1058 * @ulpi: pointer to ulpi interface
1059 * @ulpi_ready: flag to indicate that ULPI is initialized
1060 * @u2sel: parameter from Set SEL request.
1061 * @u2pel: parameter from Set SEL request.
1062 * @u1sel: parameter from Set SEL request.
1063 * @u1pel: parameter from Set SEL request.
1064 * @num_eps: number of endpoints
1065 * @ep0_next_event: hold the next expected event
1066 * @ep0state: state of endpoint zero
1067 * @link_state: link state
1068 * @speed: device speed (super, high, full, low)
1069 * @hwparams: copy of hwparams registers
1070 * @regset: debugfs pointer to regdump file
1071 * @dbg_lsp_select: current debug lsp mux register selection
1072 * @test_mode: true when we're entering a USB test mode
1073 * @test_mode_nr: test feature selector
1074 * @lpm_nyet_threshold: LPM NYET response threshold
1075 * @hird_threshold: HIRD threshold
1076 * @rx_thr_num_pkt: USB receive packet count
1077 * @rx_max_burst: max USB receive burst size
1078 * @tx_thr_num_pkt: USB transmit packet count
1079 * @tx_max_burst: max USB transmit burst size
1080 * @rx_thr_num_pkt_prd: periodic ESS receive packet count
1081 * @rx_max_burst_prd: max periodic ESS receive burst size
1082 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
1083 * @tx_max_burst_prd: max periodic ESS transmit burst size
1084 * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize
1085 * @clear_stall_protocol: endpoint number that requires a delayed status phase
1086 * @hsphy_interface: "utmi" or "ulpi"
1087 * @connected: true when we're connected to a host, false otherwise
1088 * @softconnect: true when gadget connect is called, false when disconnect runs
1089 * @delayed_status: true when gadget driver asks for delayed status
1090 * @ep0_bounced: true when we used bounce buffer
1091 * @ep0_expect_in: true when we expect a DATA IN transfer
1092 * @sysdev_is_parent: true when dwc3 device has a parent driver
1093 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
1094 * there's now way for software to detect this in runtime.
1095 * @is_utmi_l1_suspend: the core asserts output signal
1096 * 0 - utmi_sleep_n
1097 * 1 - utmi_l1_suspend_n
1098 * @is_fpga: true when we are using the FPGA board
1099 * @pending_events: true when we have pending IRQs to be handled
1100 * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
1101 * @pullups_connected: true when Run/Stop bit is set
1102 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
1103 * @three_stage_setup: set if we perform a three phase setup
1104 * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is
1105 * not needed for DWC_usb31 version 1.70a-ea06 and below
1106 * @usb3_lpm_capable: set if hadrware supports Link Power Management
1107 * @usb2_lpm_disable: set to disable usb2 lpm for host
1108 * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget
1109 * @disable_scramble_quirk: set if we enable the disable scramble quirk
1110 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
1111 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
1112 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
1113 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
1114 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
1115 * @lfps_filter_quirk: set if we enable LFPS filter quirk
1116 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
1117 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
1118 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
1119 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
1120 * disabling the suspend signal to the PHY.
1121 * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled.
1122 * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled.
1123 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
1124 * @async_callbacks: if set, indicate that async callbacks will be used.
1125 *
1126 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
1127 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
1128 * provide a free-running PHY clock.
1129 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
1130 * change quirk.
1131 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
1132 * check during HS transmit.
1133 * @resume_hs_terminations: Set if we enable quirk for fixing improper crc
1134 * generation after resume from suspend.
1135 * @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin
1136 * VBUS with an external supply.
1137 * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
1138 * instances in park mode.
1139 * @parkmode_disable_hs_quirk: set if we need to disable all HishSpeed
1140 * instances in park mode.
1141 * @gfladj_refclk_lpm_sel: set if we need to enable SOF/ITP counter
1142 * running based on ref_clk
1143 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
1144 * @tx_de_emphasis: Tx de-emphasis value
1145 * 0 - -6dB de-emphasis
1146 * 1 - -3.5dB de-emphasis
1147 * 2 - No de-emphasis
1148 * 3 - Reserved
1149 * @dis_metastability_quirk: set to disable metastability quirk.
1150 * @dis_split_quirk: set to disable split boundary.
1151 * @sys_wakeup: set if the device may do system wakeup.
1152 * @wakeup_configured: set if the device is configured for remote wakeup.
1153 * @suspended: set to track suspend event due to U3/L2.
1154 * @susphy_state: state of DWC3_GUSB2PHYCFG_SUSPHY + DWC3_GUSB3PIPECTL_SUSPHY
1155 * before PM suspend.
1156 * @imod_interval: set the interrupt moderation interval in 250ns
1157 * increments or 0 to disable.
1158 * @max_cfg_eps: current max number of IN eps used across all USB configs.
1159 * @last_fifo_depth: last fifo depth used to determine next fifo ram start
1160 * address.
1161 * @num_ep_resized: carries the current number endpoints which have had its tx
1162 * fifo resized.
1163 * @debug_root: root debugfs directory for this device to put its files in.
1164 * @gsbuscfg0_reqinfo: store GSBUSCFG0.DATRDREQINFO, DESRDREQINFO,
1165 * DATWRREQINFO, and DESWRREQINFO value passed from
1166 * glue driver.
1167 */
1168 struct dwc3 {
1169 struct work_struct drd_work;
1170 struct dwc3_trb *ep0_trb;
1171 void *bounce;
1172 u8 *setup_buf;
1173 dma_addr_t ep0_trb_addr;
1174 dma_addr_t bounce_addr;
1175 struct dwc3_request ep0_usb_req;
1176 struct completion ep0_in_setup;
1177
1178 /* device lock */
1179 spinlock_t lock;
1180
1181 /* mode switching lock */
1182 struct mutex mutex;
1183
1184 struct device *dev;
1185 struct device *sysdev;
1186
1187 struct platform_device *xhci;
1188 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1189
1190 struct dwc3_event_buffer *ev_buf;
1191 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1192
1193 struct usb_gadget *gadget;
1194 struct usb_gadget_driver *gadget_driver;
1195
1196 struct clk *bus_clk;
1197 struct clk *ref_clk;
1198 struct clk *susp_clk;
1199 struct clk *utmi_clk;
1200 struct clk *pipe_clk;
1201
1202 struct reset_control *reset;
1203
1204 struct usb_phy *usb2_phy;
1205 struct usb_phy *usb3_phy;
1206
1207 struct phy *usb2_generic_phy[DWC3_USB2_MAX_PORTS];
1208 struct phy *usb3_generic_phy[DWC3_USB3_MAX_PORTS];
1209
1210 u8 num_usb2_ports;
1211 u8 num_usb3_ports;
1212
1213 bool phys_ready;
1214
1215 struct ulpi *ulpi;
1216 bool ulpi_ready;
1217
1218 void __iomem *regs;
1219 size_t regs_size;
1220
1221 enum usb_dr_mode dr_mode;
1222 u32 current_dr_role;
1223 u32 desired_dr_role;
1224 struct extcon_dev *edev;
1225 struct notifier_block edev_nb;
1226 enum usb_phy_interface hsphy_mode;
1227 struct usb_role_switch *role_sw;
1228 enum usb_dr_mode role_switch_default_mode;
1229
1230 struct power_supply *usb_psy;
1231
1232 u32 fladj;
1233 u32 ref_clk_per;
1234 u32 irq_gadget;
1235 u32 otg_irq;
1236 u32 current_otg_role;
1237 u32 desired_otg_role;
1238 bool otg_restart_host;
1239 u32 u1u2;
1240 u32 maximum_speed;
1241 u32 gadget_max_speed;
1242 enum usb_ssp_rate max_ssp_rate;
1243 enum usb_ssp_rate gadget_ssp_rate;
1244
1245 u32 ip;
1246
1247 #define DWC3_IP 0x5533
1248 #define DWC31_IP 0x3331
1249 #define DWC32_IP 0x3332
1250
1251 u32 revision;
1252
1253 #define DWC3_REVISION_ANY 0x0
1254 #define DWC3_REVISION_173A 0x5533173a
1255 #define DWC3_REVISION_175A 0x5533175a
1256 #define DWC3_REVISION_180A 0x5533180a
1257 #define DWC3_REVISION_183A 0x5533183a
1258 #define DWC3_REVISION_185A 0x5533185a
1259 #define DWC3_REVISION_187A 0x5533187a
1260 #define DWC3_REVISION_188A 0x5533188a
1261 #define DWC3_REVISION_190A 0x5533190a
1262 #define DWC3_REVISION_194A 0x5533194a
1263 #define DWC3_REVISION_200A 0x5533200a
1264 #define DWC3_REVISION_202A 0x5533202a
1265 #define DWC3_REVISION_210A 0x5533210a
1266 #define DWC3_REVISION_220A 0x5533220a
1267 #define DWC3_REVISION_230A 0x5533230a
1268 #define DWC3_REVISION_240A 0x5533240a
1269 #define DWC3_REVISION_250A 0x5533250a
1270 #define DWC3_REVISION_260A 0x5533260a
1271 #define DWC3_REVISION_270A 0x5533270a
1272 #define DWC3_REVISION_280A 0x5533280a
1273 #define DWC3_REVISION_290A 0x5533290a
1274 #define DWC3_REVISION_300A 0x5533300a
1275 #define DWC3_REVISION_310A 0x5533310a
1276 #define DWC3_REVISION_320A 0x5533320a
1277 #define DWC3_REVISION_330A 0x5533330a
1278
1279 #define DWC31_REVISION_ANY 0x0
1280 #define DWC31_REVISION_110A 0x3131302a
1281 #define DWC31_REVISION_120A 0x3132302a
1282 #define DWC31_REVISION_160A 0x3136302a
1283 #define DWC31_REVISION_170A 0x3137302a
1284 #define DWC31_REVISION_180A 0x3138302a
1285 #define DWC31_REVISION_190A 0x3139302a
1286 #define DWC31_REVISION_200A 0x3230302a
1287
1288 #define DWC32_REVISION_ANY 0x0
1289 #define DWC32_REVISION_100A 0x3130302a
1290
1291 u32 version_type;
1292
1293 #define DWC31_VERSIONTYPE_ANY 0x0
1294 #define DWC31_VERSIONTYPE_EA01 0x65613031
1295 #define DWC31_VERSIONTYPE_EA02 0x65613032
1296 #define DWC31_VERSIONTYPE_EA03 0x65613033
1297 #define DWC31_VERSIONTYPE_EA04 0x65613034
1298 #define DWC31_VERSIONTYPE_EA05 0x65613035
1299 #define DWC31_VERSIONTYPE_EA06 0x65613036
1300
1301 enum dwc3_ep0_next ep0_next_event;
1302 enum dwc3_ep0_state ep0state;
1303 enum dwc3_link_state link_state;
1304
1305 u16 u2sel;
1306 u16 u2pel;
1307 u8 u1sel;
1308 u8 u1pel;
1309
1310 u8 speed;
1311
1312 u8 num_eps;
1313
1314 struct dwc3_hwparams hwparams;
1315 struct debugfs_regset32 *regset;
1316
1317 u32 dbg_lsp_select;
1318
1319 u8 test_mode;
1320 u8 test_mode_nr;
1321 u8 lpm_nyet_threshold;
1322 u8 hird_threshold;
1323 u8 rx_thr_num_pkt;
1324 u8 rx_max_burst;
1325 u8 tx_thr_num_pkt;
1326 u8 tx_max_burst;
1327 u8 rx_thr_num_pkt_prd;
1328 u8 rx_max_burst_prd;
1329 u8 tx_thr_num_pkt_prd;
1330 u8 tx_max_burst_prd;
1331 u8 tx_fifo_resize_max_num;
1332 u8 clear_stall_protocol;
1333
1334 const char *hsphy_interface;
1335
1336 unsigned connected:1;
1337 unsigned softconnect:1;
1338 unsigned delayed_status:1;
1339 unsigned ep0_bounced:1;
1340 unsigned ep0_expect_in:1;
1341 unsigned sysdev_is_parent:1;
1342 unsigned has_lpm_erratum:1;
1343 unsigned is_utmi_l1_suspend:1;
1344 unsigned is_fpga:1;
1345 unsigned pending_events:1;
1346 unsigned do_fifo_resize:1;
1347 unsigned pullups_connected:1;
1348 unsigned setup_packet_pending:1;
1349 unsigned three_stage_setup:1;
1350 unsigned dis_start_transfer_quirk:1;
1351 unsigned usb3_lpm_capable:1;
1352 unsigned usb2_lpm_disable:1;
1353 unsigned usb2_gadget_lpm_disable:1;
1354
1355 unsigned disable_scramble_quirk:1;
1356 unsigned u2exit_lfps_quirk:1;
1357 unsigned u2ss_inp3_quirk:1;
1358 unsigned req_p1p2p3_quirk:1;
1359 unsigned del_p1p2p3_quirk:1;
1360 unsigned del_phy_power_chg_quirk:1;
1361 unsigned lfps_filter_quirk:1;
1362 unsigned rx_detect_poll_quirk:1;
1363 unsigned dis_u3_susphy_quirk:1;
1364 unsigned dis_u2_susphy_quirk:1;
1365 unsigned dis_enblslpm_quirk:1;
1366 unsigned dis_u1_entry_quirk:1;
1367 unsigned dis_u2_entry_quirk:1;
1368 unsigned dis_rxdet_inp3_quirk:1;
1369 unsigned dis_u2_freeclk_exists_quirk:1;
1370 unsigned dis_del_phy_power_chg_quirk:1;
1371 unsigned dis_tx_ipgap_linecheck_quirk:1;
1372 unsigned resume_hs_terminations:1;
1373 unsigned ulpi_ext_vbus_drv:1;
1374 unsigned parkmode_disable_ss_quirk:1;
1375 unsigned parkmode_disable_hs_quirk:1;
1376 unsigned gfladj_refclk_lpm_sel:1;
1377
1378 unsigned tx_de_emphasis_quirk:1;
1379 unsigned tx_de_emphasis:2;
1380
1381 unsigned dis_metastability_quirk:1;
1382
1383 unsigned dis_split_quirk:1;
1384 unsigned async_callbacks:1;
1385 unsigned sys_wakeup:1;
1386 unsigned wakeup_configured:1;
1387 unsigned suspended:1;
1388 unsigned susphy_state:1;
1389
1390 u16 imod_interval;
1391
1392 int max_cfg_eps;
1393 int last_fifo_depth;
1394 int num_ep_resized;
1395 struct dentry *debug_root;
1396 u32 gsbuscfg0_reqinfo;
1397 };
1398
1399 #define INCRX_BURST_MODE 0
1400 #define INCRX_UNDEF_LENGTH_BURST_MODE 1
1401
1402 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1403
1404 /* -------------------------------------------------------------------------- */
1405
1406 struct dwc3_event_type {
1407 u32 is_devspec:1;
1408 u32 type:7;
1409 u32 reserved8_31:24;
1410 } __packed;
1411
1412 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
1413 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
1414 #define DWC3_DEPEVT_XFERNOTREADY 0x03
1415 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1416 #define DWC3_DEPEVT_STREAMEVT 0x06
1417 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
1418
1419 /**
1420 * struct dwc3_event_depevt - Device Endpoint Events
1421 * @one_bit: indicates this is an endpoint event (not used)
1422 * @endpoint_number: number of the endpoint
1423 * @endpoint_event: The event we have:
1424 * 0x00 - Reserved
1425 * 0x01 - XferComplete
1426 * 0x02 - XferInProgress
1427 * 0x03 - XferNotReady
1428 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1429 * 0x05 - Reserved
1430 * 0x06 - StreamEvt
1431 * 0x07 - EPCmdCmplt
1432 * @reserved11_10: Reserved, don't use.
1433 * @status: Indicates the status of the event. Refer to databook for
1434 * more information.
1435 * @parameters: Parameters of the current event. Refer to databook for
1436 * more information.
1437 */
1438 struct dwc3_event_depevt {
1439 u32 one_bit:1;
1440 u32 endpoint_number:5;
1441 u32 endpoint_event:4;
1442 u32 reserved11_10:2;
1443 u32 status:4;
1444
1445 /* Within XferNotReady */
1446 #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1447
1448 /* Within XferComplete or XferInProgress */
1449 #define DEPEVT_STATUS_BUSERR BIT(0)
1450 #define DEPEVT_STATUS_SHORT BIT(1)
1451 #define DEPEVT_STATUS_IOC BIT(2)
1452 #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */
1453 #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */
1454
1455 /* Stream event only */
1456 #define DEPEVT_STREAMEVT_FOUND 1
1457 #define DEPEVT_STREAMEVT_NOTFOUND 2
1458
1459 /* Stream event parameter */
1460 #define DEPEVT_STREAM_PRIME 0xfffe
1461 #define DEPEVT_STREAM_NOSTREAM 0x0
1462
1463 /* Control-only Status */
1464 #define DEPEVT_STATUS_CONTROL_DATA 1
1465 #define DEPEVT_STATUS_CONTROL_STATUS 2
1466 #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1467
1468 /* In response to Start Transfer */
1469 #define DEPEVT_TRANSFER_NO_RESOURCE 1
1470 #define DEPEVT_TRANSFER_BUS_EXPIRY 2
1471
1472 u32 parameters:16;
1473
1474 /* For Command Complete Events */
1475 #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1476 } __packed;
1477
1478 /**
1479 * struct dwc3_event_devt - Device Events
1480 * @one_bit: indicates this is a non-endpoint event (not used)
1481 * @device_event: indicates it's a device event. Should read as 0x00
1482 * @type: indicates the type of device event.
1483 * 0 - DisconnEvt
1484 * 1 - USBRst
1485 * 2 - ConnectDone
1486 * 3 - ULStChng
1487 * 4 - WkUpEvt
1488 * 5 - Reserved
1489 * 6 - Suspend (EOPF on revisions 2.10a and prior)
1490 * 7 - SOF
1491 * 8 - Reserved
1492 * 9 - ErrticErr
1493 * 10 - CmdCmplt
1494 * 11 - EvntOverflow
1495 * 12 - VndrDevTstRcved
1496 * @reserved15_12: Reserved, not used
1497 * @event_info: Information about this event
1498 * @reserved31_25: Reserved, not used
1499 */
1500 struct dwc3_event_devt {
1501 u32 one_bit:1;
1502 u32 device_event:7;
1503 u32 type:4;
1504 u32 reserved15_12:4;
1505 u32 event_info:9;
1506 u32 reserved31_25:7;
1507 } __packed;
1508
1509 /**
1510 * struct dwc3_event_gevt - Other Core Events
1511 * @one_bit: indicates this is a non-endpoint event (not used)
1512 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1513 * @phy_port_number: self-explanatory
1514 * @reserved31_12: Reserved, not used.
1515 */
1516 struct dwc3_event_gevt {
1517 u32 one_bit:1;
1518 u32 device_event:7;
1519 u32 phy_port_number:4;
1520 u32 reserved31_12:20;
1521 } __packed;
1522
1523 /**
1524 * union dwc3_event - representation of Event Buffer contents
1525 * @raw: raw 32-bit event
1526 * @type: the type of the event
1527 * @depevt: Device Endpoint Event
1528 * @devt: Device Event
1529 * @gevt: Global Event
1530 */
1531 union dwc3_event {
1532 u32 raw;
1533 struct dwc3_event_type type;
1534 struct dwc3_event_depevt depevt;
1535 struct dwc3_event_devt devt;
1536 struct dwc3_event_gevt gevt;
1537 };
1538
1539 /**
1540 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1541 * parameters
1542 * @param2: third parameter
1543 * @param1: second parameter
1544 * @param0: first parameter
1545 */
1546 struct dwc3_gadget_ep_cmd_params {
1547 u32 param2;
1548 u32 param1;
1549 u32 param0;
1550 };
1551
1552 /*
1553 * DWC3 Features to be used as Driver Data
1554 */
1555
1556 #define DWC3_HAS_PERIPHERAL BIT(0)
1557 #define DWC3_HAS_XHCI BIT(1)
1558 #define DWC3_HAS_OTG BIT(3)
1559
1560 /* prototypes */
1561 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy);
1562 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1563 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1564
1565 #define DWC3_IP_IS(_ip) \
1566 (dwc->ip == _ip##_IP)
1567
1568 #define DWC3_VER_IS(_ip, _ver) \
1569 (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1570
1571 #define DWC3_VER_IS_PRIOR(_ip, _ver) \
1572 (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
1573
1574 #define DWC3_VER_IS_WITHIN(_ip, _from, _to) \
1575 (DWC3_IP_IS(_ip) && \
1576 dwc->revision >= _ip##_REVISION_##_from && \
1577 (!(_ip##_REVISION_##_to) || \
1578 dwc->revision <= _ip##_REVISION_##_to))
1579
1580 #define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \
1581 (DWC3_VER_IS(_ip, _ver) && \
1582 dwc->version_type >= _ip##_VERSIONTYPE_##_from && \
1583 (!(_ip##_VERSIONTYPE_##_to) || \
1584 dwc->version_type <= _ip##_VERSIONTYPE_##_to))
1585
1586 /**
1587 * dwc3_mdwidth - get MDWIDTH value in bits
1588 * @dwc: pointer to our context structure
1589 *
1590 * Return MDWIDTH configuration value in bits.
1591 */
dwc3_mdwidth(struct dwc3 * dwc)1592 static inline u32 dwc3_mdwidth(struct dwc3 *dwc)
1593 {
1594 u32 mdwidth;
1595
1596 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1597 if (DWC3_IP_IS(DWC32))
1598 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
1599
1600 return mdwidth;
1601 }
1602
1603 bool dwc3_has_imod(struct dwc3 *dwc);
1604
1605 int dwc3_event_buffers_setup(struct dwc3 *dwc);
1606 void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1607
1608 int dwc3_core_soft_reset(struct dwc3 *dwc);
1609 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable);
1610
1611 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1612 int dwc3_host_init(struct dwc3 *dwc);
1613 void dwc3_host_exit(struct dwc3 *dwc);
1614 #else
dwc3_host_init(struct dwc3 * dwc)1615 static inline int dwc3_host_init(struct dwc3 *dwc)
1616 { return 0; }
dwc3_host_exit(struct dwc3 * dwc)1617 static inline void dwc3_host_exit(struct dwc3 *dwc)
1618 { }
1619 #endif
1620
1621 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1622 int dwc3_gadget_init(struct dwc3 *dwc);
1623 void dwc3_gadget_exit(struct dwc3 *dwc);
1624 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1625 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1626 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1627 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1628 struct dwc3_gadget_ep_cmd_params *params);
1629 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
1630 u32 param);
1631 void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
1632 void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status);
1633 #else
dwc3_gadget_init(struct dwc3 * dwc)1634 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1635 { return 0; }
dwc3_gadget_exit(struct dwc3 * dwc)1636 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1637 { }
dwc3_gadget_set_test_mode(struct dwc3 * dwc,int mode)1638 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1639 { return 0; }
dwc3_gadget_get_link_state(struct dwc3 * dwc)1640 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1641 { return 0; }
dwc3_gadget_set_link_state(struct dwc3 * dwc,enum dwc3_link_state state)1642 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1643 enum dwc3_link_state state)
1644 { return 0; }
1645
dwc3_send_gadget_ep_cmd(struct dwc3_ep * dep,unsigned int cmd,struct dwc3_gadget_ep_cmd_params * params)1646 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1647 struct dwc3_gadget_ep_cmd_params *params)
1648 { return 0; }
dwc3_send_gadget_generic_command(struct dwc3 * dwc,int cmd,u32 param)1649 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1650 int cmd, u32 param)
1651 { return 0; }
dwc3_gadget_clear_tx_fifos(struct dwc3 * dwc)1652 static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
1653 { }
1654 #endif
1655
1656 #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1657 int dwc3_drd_init(struct dwc3 *dwc);
1658 void dwc3_drd_exit(struct dwc3 *dwc);
1659 void dwc3_otg_init(struct dwc3 *dwc);
1660 void dwc3_otg_exit(struct dwc3 *dwc);
1661 void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1662 void dwc3_otg_host_init(struct dwc3 *dwc);
1663 #else
dwc3_drd_init(struct dwc3 * dwc)1664 static inline int dwc3_drd_init(struct dwc3 *dwc)
1665 { return 0; }
dwc3_drd_exit(struct dwc3 * dwc)1666 static inline void dwc3_drd_exit(struct dwc3 *dwc)
1667 { }
dwc3_otg_init(struct dwc3 * dwc)1668 static inline void dwc3_otg_init(struct dwc3 *dwc)
1669 { }
dwc3_otg_exit(struct dwc3 * dwc)1670 static inline void dwc3_otg_exit(struct dwc3 *dwc)
1671 { }
dwc3_otg_update(struct dwc3 * dwc,bool ignore_idstatus)1672 static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1673 { }
dwc3_otg_host_init(struct dwc3 * dwc)1674 static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1675 { }
1676 #endif
1677
1678 /* power management interface */
1679 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1680 int dwc3_gadget_suspend(struct dwc3 *dwc);
1681 int dwc3_gadget_resume(struct dwc3 *dwc);
1682 #else
dwc3_gadget_suspend(struct dwc3 * dwc)1683 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1684 {
1685 return 0;
1686 }
1687
dwc3_gadget_resume(struct dwc3 * dwc)1688 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1689 {
1690 return 0;
1691 }
1692
1693 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1694
1695 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1696 int dwc3_ulpi_init(struct dwc3 *dwc);
1697 void dwc3_ulpi_exit(struct dwc3 *dwc);
1698 #else
dwc3_ulpi_init(struct dwc3 * dwc)1699 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1700 { return 0; }
dwc3_ulpi_exit(struct dwc3 * dwc)1701 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1702 { }
1703 #endif
1704
1705 #endif /* __DRIVERS_USB_DWC3_CORE_H */
1706