1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #ifndef ADF_ACCEL_DEVICES_H_
4 #define ADF_ACCEL_DEVICES_H_
5 #include <linux/interrupt.h>
6 #include <linux/module.h>
7 #include <linux/list.h>
8 #include <linux/io.h>
9 #include <linux/pci.h>
10 #include <linux/ratelimit.h>
11 #include <linux/types.h>
12 #include <linux/qat/qat_mig_dev.h>
13 #include <linux/wordpart.h>
14 #include "adf_anti_rb.h"
15 #include "adf_cfg_common.h"
16 #include "adf_dc.h"
17 #include "adf_kpt.h"
18 #include "adf_rl.h"
19 #include "adf_telemetry.h"
20 #include "adf_pfvf_msg.h"
21 #include "icp_qat_hw.h"
22
23 #define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
24 #define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf"
25 #define ADF_C62X_DEVICE_NAME "c6xx"
26 #define ADF_C62XVF_DEVICE_NAME "c6xxvf"
27 #define ADF_C3XXX_DEVICE_NAME "c3xxx"
28 #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
29 #define ADF_4XXX_DEVICE_NAME "4xxx"
30 #define ADF_420XX_DEVICE_NAME "420xx"
31 #define ADF_6XXX_DEVICE_NAME "6xxx"
32 #define PCI_DEVICE_ID_INTEL_QAT_4XXXIOV 0x4941
33 #define PCI_DEVICE_ID_INTEL_QAT_401XXIOV 0x4943
34 #define PCI_DEVICE_ID_INTEL_QAT_402XXIOV 0x4945
35 #define PCI_DEVICE_ID_INTEL_QAT_420XXIOV 0x4947
36 #define PCI_DEVICE_ID_INTEL_QAT_6XXX_IOV 0x4949
37
38 #define ADF_DEVICE_FUSECTL_OFFSET 0x40
39 #define ADF_DEVICE_LEGFUSE_OFFSET 0x4C
40 #define ADF_DEVICE_FUSECTL_MASK 0x80000000
41 #define ADF_PCI_MAX_BARS 3
42 #define ADF_DEVICE_NAME_LENGTH 32
43 #define ADF_ETR_MAX_RINGS_PER_BANK 16
44 #define ADF_MAX_MSIX_VECTOR_NAME 48
45 #define ADF_DEVICE_NAME_PREFIX "qat_"
46
47 enum adf_accel_capabilities {
48 ADF_ACCEL_CAPABILITIES_NULL = 0,
49 ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1,
50 ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2,
51 ADF_ACCEL_CAPABILITIES_CIPHER = 4,
52 ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8,
53 ADF_ACCEL_CAPABILITIES_COMPRESSION = 32,
54 ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION = 64,
55 ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128
56 };
57
58 enum adf_accel_capabilities_ext {
59 ADF_ACCEL_CAPABILITIES_EXT_ZSTD_LZ4S = BIT(0),
60 ADF_ACCEL_CAPABILITIES_EXT_ZSTD = BIT(1),
61 };
62
63 enum adf_fuses {
64 ADF_FUSECTL0,
65 ADF_FUSECTL1,
66 ADF_FUSECTL2,
67 ADF_FUSECTL3,
68 ADF_FUSECTL4,
69 ADF_FUSECTL5,
70 ADF_MAX_FUSES
71 };
72
73 struct adf_bar {
74 resource_size_t base_addr;
75 void __iomem *virt_addr;
76 resource_size_t size;
77 };
78
79 struct adf_irq {
80 bool enabled;
81 char name[ADF_MAX_MSIX_VECTOR_NAME];
82 };
83
84 struct adf_accel_msix {
85 struct adf_irq *irqs;
86 u32 num_entries;
87 };
88
89 struct adf_accel_pci {
90 struct pci_dev *pci_dev;
91 struct adf_accel_msix msix_entries;
92 struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
93 u8 revid;
94 u8 sku;
95 };
96
97 enum dev_state {
98 DEV_DOWN = 0,
99 DEV_UP
100 };
101
102 enum dev_sku_info {
103 DEV_SKU_1 = 0,
104 DEV_SKU_2,
105 DEV_SKU_3,
106 DEV_SKU_4,
107 DEV_SKU_VF,
108 DEV_SKU_UNKNOWN,
109 };
110
111 enum ras_errors {
112 ADF_RAS_CORR,
113 ADF_RAS_UNCORR,
114 ADF_RAS_FATAL,
115 ADF_RAS_ERRORS,
116 };
117
118 struct adf_error_counters {
119 atomic_t counter[ADF_RAS_ERRORS];
120 bool sysfs_added;
121 bool enabled;
122 };
123
get_sku_info(enum dev_sku_info info)124 static inline const char *get_sku_info(enum dev_sku_info info)
125 {
126 switch (info) {
127 case DEV_SKU_1:
128 return "SKU1";
129 case DEV_SKU_2:
130 return "SKU2";
131 case DEV_SKU_3:
132 return "SKU3";
133 case DEV_SKU_4:
134 return "SKU4";
135 case DEV_SKU_VF:
136 return "SKUVF";
137 case DEV_SKU_UNKNOWN:
138 default:
139 break;
140 }
141 return "Unknown SKU";
142 }
143
144 struct adf_hw_device_class {
145 const char *name;
146 const enum adf_device_type type;
147 u32 instances;
148 };
149
150 struct arb_info {
151 u32 arb_cfg;
152 u32 arb_offset;
153 u32 wt2sam_offset;
154 };
155
156 struct admin_info {
157 u32 admin_msg_ur;
158 u32 admin_msg_lr;
159 u32 mailbox_offset;
160 };
161
162 struct adf_bank_state;
163
164 struct adf_hw_csr_ops {
165 u64 (*build_csr_ring_base_addr)(dma_addr_t addr, u32 size);
166 u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
167 u32 ring);
168 void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
169 u32 ring, u32 value);
170 u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
171 u32 ring);
172 void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
173 u32 ring, u32 value);
174 u32 (*read_csr_stat)(void __iomem *csr_base_addr, u32 bank);
175 u32 (*read_csr_uo_stat)(void __iomem *csr_base_addr, u32 bank);
176 u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
177 u32 (*read_csr_ne_stat)(void __iomem *csr_base_addr, u32 bank);
178 u32 (*read_csr_nf_stat)(void __iomem *csr_base_addr, u32 bank);
179 u32 (*read_csr_f_stat)(void __iomem *csr_base_addr, u32 bank);
180 u32 (*read_csr_c_stat)(void __iomem *csr_base_addr, u32 bank);
181 u32 (*read_csr_exp_stat)(void __iomem *csr_base_addr, u32 bank);
182 u32 (*read_csr_exp_int_en)(void __iomem *csr_base_addr, u32 bank);
183 void (*write_csr_exp_int_en)(void __iomem *csr_base_addr, u32 bank,
184 u32 value);
185 u32 (*read_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
186 u32 ring);
187 void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
188 u32 ring, u32 value);
189 dma_addr_t (*read_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
190 u32 ring);
191 void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
192 u32 ring, dma_addr_t addr);
193 u32 (*read_csr_int_en)(void __iomem *csr_base_addr, u32 bank);
194 void (*write_csr_int_en)(void __iomem *csr_base_addr, u32 bank,
195 u32 value);
196 u32 (*read_csr_int_flag)(void __iomem *csr_base_addr, u32 bank);
197 void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
198 u32 value);
199 u32 (*read_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
200 void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
201 void (*write_csr_int_srcsel_w_val)(void __iomem *csr_base_addr,
202 u32 bank, u32 value);
203 u32 (*read_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank);
204 void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
205 u32 value);
206 u32 (*read_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank);
207 void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,
208 u32 value);
209 u32 (*read_csr_int_flag_and_col)(void __iomem *csr_base_addr,
210 u32 bank);
211 void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr,
212 u32 bank, u32 value);
213 u32 (*read_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank);
214 void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,
215 u32 value);
216 u32 (*get_int_col_ctl_enable_mask)(void);
217 };
218
219 struct adf_cfg_device_data;
220 struct adf_accel_dev;
221 struct adf_etr_data;
222 struct adf_etr_ring_data;
223
224 struct adf_ras_ops {
225 void (*enable_ras_errors)(struct adf_accel_dev *accel_dev);
226 void (*disable_ras_errors)(struct adf_accel_dev *accel_dev);
227 bool (*handle_interrupt)(struct adf_accel_dev *accel_dev,
228 bool *reset_required);
229 };
230
231 struct adf_pfvf_ops {
232 int (*enable_comms)(struct adf_accel_dev *accel_dev);
233 u32 (*get_pf2vf_offset)(u32 i);
234 u32 (*get_vf2pf_offset)(u32 i);
235 void (*enable_vf2pf_interrupts)(void __iomem *pmisc_addr, u32 vf_mask);
236 void (*disable_all_vf2pf_interrupts)(void __iomem *pmisc_addr);
237 u32 (*disable_pending_vf2pf_interrupts)(void __iomem *pmisc_addr);
238 int (*send_msg)(struct adf_accel_dev *accel_dev, struct pfvf_message msg,
239 u32 pfvf_offset, struct mutex *csr_lock);
240 struct pfvf_message (*recv_msg)(struct adf_accel_dev *accel_dev,
241 u32 pfvf_offset, u8 compat_ver);
242 };
243
244 struct adf_dc_ops {
245 int (*build_comp_block)(void *ctx, enum adf_dc_algo algo);
246 int (*build_decomp_block)(void *ctx, enum adf_dc_algo algo);
247 };
248
249 struct qat_migdev_ops {
250 int (*init)(struct qat_mig_dev *mdev);
251 void (*cleanup)(struct qat_mig_dev *mdev);
252 void (*reset)(struct qat_mig_dev *mdev);
253 int (*open)(struct qat_mig_dev *mdev);
254 void (*close)(struct qat_mig_dev *mdev);
255 int (*suspend)(struct qat_mig_dev *mdev);
256 int (*resume)(struct qat_mig_dev *mdev);
257 int (*save_state)(struct qat_mig_dev *mdev);
258 int (*save_setup)(struct qat_mig_dev *mdev);
259 int (*load_state)(struct qat_mig_dev *mdev);
260 int (*load_setup)(struct qat_mig_dev *mdev, int size);
261 };
262
263 struct adf_dev_err_mask {
264 u32 cppagentcmdpar_mask;
265 u32 parerr_ath_cph_mask;
266 u32 parerr_cpr_xlt_mask;
267 u32 parerr_dcpr_ucs_mask;
268 u32 parerr_pke_mask;
269 u32 parerr_wat_wcp_mask;
270 u32 ssmfeatren_mask;
271 };
272
273 struct adf_hw_device_data {
274 struct adf_hw_device_class *dev_class;
275 u32 (*get_accel_mask)(struct adf_hw_device_data *self);
276 u32 (*get_ae_mask)(struct adf_hw_device_data *self);
277 u32 (*get_accel_cap)(struct adf_accel_dev *accel_dev);
278 u32 (*get_sram_bar_id)(struct adf_hw_device_data *self);
279 u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
280 u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
281 u32 (*get_num_aes)(struct adf_hw_device_data *self);
282 u32 (*get_num_accels)(struct adf_hw_device_data *self);
283 void (*get_arb_info)(struct arb_info *arb_csrs_info);
284 void (*get_admin_info)(struct admin_info *admin_csrs_info);
285 enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
286 u16 (*get_ring_to_svc_map)(struct adf_accel_dev *accel_dev);
287 int (*alloc_irq)(struct adf_accel_dev *accel_dev);
288 void (*free_irq)(struct adf_accel_dev *accel_dev);
289 void (*enable_error_correction)(struct adf_accel_dev *accel_dev);
290 int (*init_admin_comms)(struct adf_accel_dev *accel_dev);
291 void (*exit_admin_comms)(struct adf_accel_dev *accel_dev);
292 int (*send_admin_init)(struct adf_accel_dev *accel_dev);
293 int (*start_timer)(struct adf_accel_dev *accel_dev);
294 void (*stop_timer)(struct adf_accel_dev *accel_dev);
295 void (*check_hb_ctrs)(struct adf_accel_dev *accel_dev);
296 uint32_t (*get_hb_clock)(struct adf_hw_device_data *self);
297 int (*measure_clock)(struct adf_accel_dev *accel_dev);
298 int (*init_arb)(struct adf_accel_dev *accel_dev);
299 void (*exit_arb)(struct adf_accel_dev *accel_dev);
300 const u32 *(*get_arb_mapping)(struct adf_accel_dev *accel_dev);
301 int (*init_device)(struct adf_accel_dev *accel_dev);
302 int (*enable_pm)(struct adf_accel_dev *accel_dev);
303 bool (*handle_pm_interrupt)(struct adf_accel_dev *accel_dev);
304 void (*disable_iov)(struct adf_accel_dev *accel_dev);
305 void (*configure_iov_threads)(struct adf_accel_dev *accel_dev,
306 bool enable);
307 void (*enable_ints)(struct adf_accel_dev *accel_dev);
308 void (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);
309 int (*ring_pair_reset)(struct adf_accel_dev *accel_dev, u32 bank_nr);
310 int (*bank_state_save)(struct adf_accel_dev *accel_dev, u32 bank_number,
311 struct adf_bank_state *state);
312 int (*bank_state_restore)(struct adf_accel_dev *accel_dev,
313 u32 bank_number, struct adf_bank_state *state);
314 void (*reset_device)(struct adf_accel_dev *accel_dev);
315 void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
316 const char *(*uof_get_name)(struct adf_accel_dev *accel_dev, u32 obj_num);
317 u32 (*uof_get_num_objs)(struct adf_accel_dev *accel_dev);
318 int (*uof_get_obj_type)(struct adf_accel_dev *accel_dev, u32 obj_num);
319 u32 (*uof_get_ae_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);
320 int (*get_rp_group)(struct adf_accel_dev *accel_dev, u32 ae_mask);
321 u32 (*get_ena_thd_mask)(struct adf_accel_dev *accel_dev, u32 obj_num);
322 int (*dev_config)(struct adf_accel_dev *accel_dev);
323 bool (*services_supported)(unsigned long mask);
324 u32 (*get_svc_slice_cnt)(struct adf_accel_dev *accel_dev,
325 enum adf_base_services svc);
326 struct adf_pfvf_ops pfvf_ops;
327 struct adf_hw_csr_ops csr_ops;
328 struct adf_dc_ops dc_ops;
329 struct adf_ras_ops ras_ops;
330 struct adf_dev_err_mask dev_err_mask;
331 struct adf_rl_hw_data rl_data;
332 struct adf_tl_hw_data tl_data;
333 struct adf_anti_rb_hw_data anti_rb_data;
334 struct adf_kpt_hw_data kpt_data;
335 struct qat_migdev_ops vfmig_ops;
336 const char *fw_name;
337 const char *fw_mmp_name;
338 u32 fuses[ADF_MAX_FUSES];
339 u32 straps;
340 u32 accel_capabilities_mask;
341 u32 accel_capabilities_ext_mask;
342 u32 extended_dc_capabilities;
343 u16 fw_capabilities;
344 u32 clock_frequency;
345 u32 instance_id;
346 u16 accel_mask;
347 u32 ae_mask;
348 u32 admin_ae_mask;
349 u16 tx_rings_mask;
350 u16 ring_to_svc_map;
351 u32 thd_to_arb_map[ICP_QAT_HW_AE_DELIMITER];
352 u8 tx_rx_gap;
353 u8 num_banks;
354 u16 num_banks_per_vf;
355 u8 num_rings_per_bank;
356 u8 num_accel;
357 u8 num_logical_accel;
358 u8 num_engines;
359 u32 num_hb_ctrs;
360 u8 num_rps;
361 };
362
363 /* CSR write macro */
364 #define ADF_CSR_WR(csr_base, csr_offset, val) \
365 __raw_writel(val, csr_base + csr_offset)
366 /*
367 * CSR write macro to handle cases where the high and low
368 * offsets are sparsely located.
369 */
370 #define ADF_CSR_WR64_LO_HI(csr_base, csr_low_offset, csr_high_offset, val) \
371 do { \
372 ADF_CSR_WR(csr_base, csr_low_offset, lower_32_bits(val)); \
373 ADF_CSR_WR(csr_base, csr_high_offset, upper_32_bits(val)); \
374 } while (0)
375
376 /* CSR read macro */
377 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
378
379 #define ADF_CFG_NUM_SERVICES 4
380 #define ADF_SRV_TYPE_BIT_LEN 3
381 #define ADF_SRV_TYPE_MASK 0x7
382 #define ADF_AE_ADMIN_THREAD 7
383 #define ADF_NUM_THREADS_PER_AE 8
384 #define ADF_NUM_PKE_STRAND 2
385 #define ADF_AE_STRAND0_THREAD 8
386 #define ADF_AE_STRAND1_THREAD 9
387
388 #define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev)
389 #define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
390 #define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
391 #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
392 #define GET_NUM_RINGS_PER_BANK(accel_dev) \
393 GET_HW_DATA(accel_dev)->num_rings_per_bank
394 #define GET_SRV_TYPE(accel_dev, idx) \
395 (((GET_HW_DATA(accel_dev)->ring_to_svc_map) >> (ADF_SRV_TYPE_BIT_LEN * (idx))) \
396 & ADF_SRV_TYPE_MASK)
397 #define GET_ERR_MASK(accel_dev) (&GET_HW_DATA(accel_dev)->dev_err_mask)
398 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
399 #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)
400 #define GET_PFVF_OPS(accel_dev) (&(accel_dev)->hw_device->pfvf_ops)
401 #define GET_DC_OPS(accel_dev) (&(accel_dev)->hw_device->dc_ops)
402 #define GET_VFMIG_OPS(accel_dev) (&(accel_dev)->hw_device->vfmig_ops)
403 #define GET_TL_DATA(accel_dev) GET_HW_DATA(accel_dev)->tl_data
404 #define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
405
406 struct adf_admin_comms;
407 struct icp_qat_fw_loader_handle;
408 struct adf_fw_loader_data {
409 struct icp_qat_fw_loader_handle *fw_loader;
410 const struct firmware *uof_fw;
411 const struct firmware *mmp_fw;
412 };
413
414 struct adf_accel_vf_info {
415 struct adf_accel_dev *accel_dev;
416 struct mutex pf2vf_lock; /* protect CSR access for PF2VF messages */
417 struct mutex pfvf_mig_lock; /* protects PFVF state for migration */
418 struct ratelimit_state vf2pf_ratelimit;
419 u32 vf_nr;
420 bool init;
421 bool restarting;
422 u8 vf_compat_ver;
423 /*
424 * Private area used for device migration.
425 * Memory allocation and free is managed by migration driver.
426 */
427 void *mig_priv;
428 };
429
430 struct adf_dc_data {
431 u8 *ovf_buff;
432 size_t ovf_buff_sz;
433 dma_addr_t ovf_buff_p;
434 };
435
436 struct adf_pm {
437 struct dentry *debugfs_pm_status;
438 bool present;
439 int idle_irq_counters;
440 int throttle_irq_counters;
441 int fw_irq_counters;
442 int host_ack_counter;
443 int host_nack_counter;
444 ssize_t (*print_pm_status)(struct adf_accel_dev *accel_dev,
445 char __user *buf, size_t count, loff_t *pos);
446 };
447
448 struct adf_sysfs {
449 int ring_num;
450 struct rw_semaphore lock; /* protects access to the fields in this struct */
451 };
452
453 struct adf_accel_dev {
454 struct adf_etr_data *transport;
455 struct adf_hw_device_data *hw_device;
456 struct adf_cfg_device_data *cfg;
457 struct adf_fw_loader_data *fw_loader;
458 struct adf_admin_comms *admin;
459 struct adf_telemetry *telemetry;
460 struct adf_dc_data *dc_data;
461 struct adf_pm power_management;
462 struct list_head crypto_list;
463 struct list_head compression_list;
464 unsigned long status;
465 atomic_t ref_count;
466 struct dentry *debugfs_dir;
467 struct dentry *fw_cntr_dbgfile;
468 struct dentry *cnv_dbgfile;
469 struct list_head list;
470 struct module *owner;
471 struct adf_accel_pci accel_pci_dev;
472 struct adf_timer *timer;
473 struct adf_heartbeat *heartbeat;
474 struct adf_rl *rate_limiting;
475 struct adf_sysfs sysfs;
476 union {
477 struct {
478 /* protects VF2PF interrupts access */
479 spinlock_t vf2pf_ints_lock;
480 /* prevents VF2PF handling from racing with VF state teardown */
481 bool vf2pf_disabled;
482 /* vf_info is non-zero when SR-IOV is init'ed */
483 struct adf_accel_vf_info *vf_info;
484 } pf;
485 struct {
486 bool irq_enabled;
487 char irq_name[ADF_MAX_MSIX_VECTOR_NAME];
488 struct tasklet_struct pf2vf_bh_tasklet;
489 struct mutex vf2pf_lock; /* protect CSR access */
490 struct completion msg_received;
491 struct pfvf_message response; /* temp field holding pf2vf response */
492 u8 pf_compat_ver;
493 } vf;
494 };
495 struct adf_error_counters ras_errors;
496 struct mutex state_lock; /* protect state of the device */
497 bool is_vf;
498 bool autoreset_on_error;
499 u32 accel_id;
500 };
501 #endif
502