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Searched refs:gen_speed (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr_ppt.h96 uint8_t gen_speed; member
H A Dvega20_hwmgr.c3381 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega20_emit_clock_levels() local
3494 gen_speed = pptable->PcieGenSpeed[i]; in vega20_emit_clock_levels()
3499 (gen_speed == 0) ? "2.5GT/s," : in vega20_emit_clock_levels()
3500 (gen_speed == 1) ? "5.0GT/s," : in vega20_emit_clock_levels()
3501 (gen_speed == 2) ? "8.0GT/s," : in vega20_emit_clock_levels()
3502 (gen_speed == 3) ? "16.0GT/s," : in vega20_emit_clock_levels()
3512 (current_gen_speed == gen_speed) && in vega20_emit_clock_levels()
H A Dprocess_pptables_v1_0.c516 pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed; in get_pcie_table()
553 pcie_record->gen_speed = atom_pcie_record->ucPCIEGenSpeed; in get_pcie_table()
H A Dvega10_hwmgr.c1277 bios_pcie_table->entries[i].gen_speed; in vega10_setup_default_pcie_table()
4690 uint32_t gen_speed, lane_width, current_gen_speed, current_lane_width; in vega10_emit_clock_levels() local
4763 gen_speed = pptable->PcieGenSpeed[i]; in vega10_emit_clock_levels()
4767 (gen_speed == 0) ? "2.5GT/s," : in vega10_emit_clock_levels()
4768 (gen_speed == 1) ? "5.0GT/s," : in vega10_emit_clock_levels()
4769 (gen_speed == 2) ? "8.0GT/s," : in vega10_emit_clock_levels()
4770 (gen_speed == 3) ? "16.0GT/s," : "", in vega10_emit_clock_levels()
4777 (current_gen_speed == gen_speed) && in vega10_emit_clock_levels()
H A Dvega10_processpptables.c812 pcie_table->entries[i].gen_speed = in get_pcie_table()
H A Dsmu7_hwmgr.c675 pcie_table->entries[i].gen_speed), in smu7_setup_default_pcie_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_2_ppt.c1041 uint32_t gen_speed, lane_width; in smu_v14_0_2_emit_clk_levels() local
1078 &gen_speed); in smu_v14_0_2_emit_clk_levels()
1090 SMU_DPM_PCIE_GEN_IDX(gen_speed), in smu_v14_0_2_emit_clk_levels()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_7_ppt.c1221 uint32_t gen_speed, lane_width; in smu_v13_0_7_emit_clk_levels() local
1257 &gen_speed); in smu_v13_0_7_emit_clk_levels()
1269 SMU_DPM_PCIE_GEN_IDX(gen_speed), in smu_v13_0_7_emit_clk_levels()
H A Dsmu_v13_0_0_ppt.c1211 uint32_t gen_speed, lane_width; in smu_v13_0_0_emit_clk_levels() local
1247 &gen_speed); in smu_v13_0_0_emit_clk_levels()
1259 SMU_DPM_PCIE_GEN_IDX(gen_speed), in smu_v13_0_0_emit_clk_levels()