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Searched refs:gb_addr_config (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dni.c867 u32 gb_addr_config = 0; in cayman_gpu_init() local
900 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN; in cayman_gpu_init()
974 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN; in cayman_gpu_init()
1005 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT; in cayman_gpu_init()
1007 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT; in cayman_gpu_init()
1009 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT; in cayman_gpu_init()
1011 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT; in cayman_gpu_init()
1013 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT; in cayman_gpu_init()
1015 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT; in cayman_gpu_init()
1061 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; in cayman_gpu_init()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c1646 u32 gb_addr_config = 0; in gfx_v6_0_constants_init() local
1668 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1685 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1702 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1719 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1736 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN; in gfx_v6_0_constants_init()
1762 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK; in gfx_v6_0_constants_init()
1766 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; in gfx_v6_0_constants_init()
1769 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; in gfx_v6_0_constants_init()
1772 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT; in gfx_v6_0_constants_init()
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H A Djpeg_v5_3_0.c345 adev->gfx.config.gb_addr_config, indirect); in jpeg_v5_3_0_start_dpg_mode()
348 adev->gfx.config.gb_addr_config, 1); in jpeg_v5_3_0_start_dpg_mode()
431 adev->gfx.config.gb_addr_config); in jpeg_v5_3_0_start()
H A Djpeg_v5_0_0.c362 adev->gfx.config.gb_addr_config, indirect); in jpeg_v5_0_0_start_dpg_mode()
365 adev->gfx.config.gb_addr_config, 1); in jpeg_v5_0_0_start_dpg_mode()
448 adev->gfx.config.gb_addr_config); in jpeg_v5_0_0_start()
H A Duvd_v3_1.c274 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
275 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
276 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in uvd_v3_1_mc_resume()
H A Djpeg_v3_0.c369 adev->gfx.config.gb_addr_config); in jpeg_v3_0_start()
371 adev->gfx.config.gb_addr_config); in jpeg_v3_0_start()
H A Djpeg_v4_0_5.c452 adev->gfx.config.gb_addr_config, indirect); in jpeg_v4_0_5_start_dpg_mode()
537 adev->gfx.config.gb_addr_config); in jpeg_v4_0_5_start()
H A Dvcn_v5_0_2.c484 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
731 adev->gfx.config.gb_addr_config); in vcn_v5_0_2_start()
H A Djpeg_v4_0_3.c563 adev->gfx.config.gb_addr_config); in jpeg_v4_0_3_start_inst()
565 adev->gfx.config.gb_addr_config); in jpeg_v4_0_3_start_inst()
H A Djpeg_v2_0.c351 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in jpeg_v2_0_start()
H A Djpeg_v4_0.c406 adev->gfx.config.gb_addr_config); in jpeg_v4_0_start()
H A Dvcn_v2_5.c740 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1236 adev->gfx.config.gb_addr_config); in vcn_v2_5_start()
1238 adev->gfx.config.gb_addr_config); in vcn_v2_5_start()
H A Djpeg_v5_0_2.c336 adev->gfx.config.gb_addr_config); in jpeg_v5_0_2_init_inst()
H A Dvcn_v4_0_5.c565 adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
1133 adev->gfx.config.gb_addr_config); in vcn_v4_0_5_start()
H A Dvcn_v2_0.c435 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); in vcn_v2_0_mc_resume()
533 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
H A Djpeg_v5_0_1.c380 adev->gfx.config.gb_addr_config); in jpeg_v5_0_1_init_inst()
H A Dvcn_v4_0.c608 adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1221 adev->gfx.config.gb_addr_config); in vcn_v4_0_start()
H A Dvcn_v3_0.c668 UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1276 adev->gfx.config.gb_addr_config); in vcn_v3_0_start()