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Searched refs:gate_clks (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/clk/samsung/
H A Dclk-exynosautov9.c953 .gate_clks = top_gate_clks,
1013 .gate_clks = busmc_gate_clks,
1071 .gate_clks = core_gate_clks,
1150 .gate_clks = dpum_gate_clks,
1390 .gate_clks = fsys0_gate_clks,
1517 .gate_clks = fsys1_gate_clks,
1584 .gate_clks = fsys2_gate_clks,
1839 .gate_clks = peric0_gate_clks,
2094 .gate_clks = peric1_gate_clks,
2141 .gate_clks = peris_gate_clks,
H A Dclk-exynos850.c569 .gate_clks = top_gate_clks,
713 .gate_clks = apm_gate_clks,
996 .gate_clks = aud_gate_clks,
1099 .gate_clks = cmgp_gate_clks,
1301 .gate_clks = cpucl0_gate_clks,
1456 .gate_clks = cpucl1_gate_clks,
1564 .gate_clks = g3d_gate_clks,
1666 .gate_clks = hsi_gate_clks,
1798 .gate_clks = is_gate_clks,
1907 .gate_clks = mfcmscl_gate_clks,
[all …]
H A Dclk-exynos5-subcmu.c66 exynos5_subcmu_defer_gate(ctx, (*_cmu)->gate_clks, in exynos5_subcmus_init()
110 samsung_clk_register_gate(ctx, info->gate_clks, info->nr_gate_clks); in exynos5_subcmu_probe()
H A Dclk-exynos5-subcmu.h16 const struct samsung_gate_clock *gate_clks; member
H A Dclk-exynos7885.c349 .gate_clks = top_gate_clks,
568 .gate_clks = peri_gate_clks,
677 .gate_clks = core_gate_clks,
802 .gate_clks = fsys_gate_clks,
H A Dclk-exynos7870.c730 .gate_clks = mif_gate_clks,
1008 .gate_clks = dispaud_gate_clks,
1129 .gate_clks = fsys_gate_clks,
1245 .gate_clks = g3d_gate_clks,
1432 .gate_clks = isp_gate_clks,
1521 .gate_clks = mfcmscl_gate_clks,
1771 .gate_clks = peri_gate_clks,
H A Dclk-exynos5433.c815 .gate_clks = top_gate_clks,
898 .gate_clks = cpif_gate_clks,
1550 .gate_clks = mif_gate_clks,
1751 .gate_clks = peric_gate_clks,
1945 .gate_clks = peris_gate_clks,
2355 .gate_clks = fsys_gate_clks,
2480 .gate_clks = g2d_gate_clks,
2904 .gate_clks = disp_gate_clks,
3076 .gate_clks = aud_gate_clks,
3210 .gate_clks = bus##id##_gate_clks, \
[all …]
H A Dclk-exynos3250.c431 static const struct samsung_gate_clock gate_clks[] __initconst = { variable
806 .gate_clks = gate_clks,
807 .nr_gate_clks = ARRAY_SIZE(gate_clks),
1070 .gate_clks = isp_gate_clks,
H A Dclk-fsd.c309 .gate_clks = cmu_gate_clks,
672 .gate_clks = peric_gate_clks,
971 .gate_clks = fsys0_gate_clks,
1143 .gate_clks = fsys1_gate_clks,
1422 .gate_clks = imem_gate_clks,
1547 .gate_clks = mfc_gate_clks,
1751 .gate_clks = cam_csi_gate_clks,
H A Dclk-artpec8.c550 .gate_clks = cmu_cpucl_gate_clks,
780 .gate_clks = cmu_fsys_gate_clks,
830 .gate_clks = cmu_imem_gate_clks,
982 .gate_clks = cmu_peri_gate_clks,
H A Dclk-exynos5420.c1332 .gate_clks = exynos5x_disp_gate_clks,
1342 .gate_clks = exynos5x_gsc_gate_clks,
1350 .gate_clks = exynos5x_g3d_gate_clks,
1360 .gate_clks = exynos5x_mfc_gate_clks,
1370 .gate_clks = exynos5x_mscl_gate_clks,
1378 .gate_clks = exynos5800_mau_gate_clks,
H A Dclk-exynos8895.c1296 .gate_clks = top_gate_clks,
1530 .gate_clks = peris_gate_clks,
1820 .gate_clks = fsys0_gate_clks,
2119 .gate_clks = fsys1_gate_clks,
2308 .gate_clks = peric0_gate_clks,
2753 .gate_clks = peric1_gate_clks,
H A Dclk-exynos990.c1168 .gate_clks = top_gate_clks,
1347 .gate_clks = hsi0_gate_clks,
1872 .gate_clks = peric0_gate_clks,
2470 .gate_clks = peric1_gate_clks,
2642 .gate_clks = peris_gate_clks,
H A Dclk.c478 if (cmu->gate_clks) in samsung_cmu_register_clocks()
479 samsung_clk_register_gate(ctx, cmu->gate_clks, in samsung_cmu_register_clocks()
H A Dclk-gs101.c1435 .gate_clks = top_gate_clks,
1920 .gate_clks = apm_gate_clks,
2200 .gate_clks = dpu_gate_clks,
2668 .gate_clks = hsi0_gate_clks,
3165 .gate_clks = hsi2_gate_clks,
3732 .gate_clks = misc_gate_clks,
4340 .gate_clks = peric0_gate_clks,
4694 .gate_clks = peric1_gate_clks,
H A Dclk.h371 const struct samsung_gate_clock *gate_clks; member
H A Dclk-exynos4.c1276 .gate_clks = exynos4_gate_clks,
1289 .gate_clks = exynos4210_gate_clks,
1304 .gate_clks = exynos4x12_gate_clks,
H A Dclk-exynos5250.c680 .gate_clks = exynos5250_disp_gate_clks,
/linux/drivers/clk/sophgo/
H A Dclk-sg2042-rpgate.c194 const struct sg2042_rpgate_clock gate_clks[], in sg2042_clk_register_rpgates() argument
202 gate = &gate_clks[i]; in sg2042_clk_register_rpgates()
/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c772 static struct tegra_periph_init_data gate_clks[] = { variable
894 for (i = 0; i < ARRAY_SIZE(gate_clks); i++) { in gate_clk_init()
897 data = gate_clks + i; in gate_clk_init()