1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #include <linux/debugfs.h> 8 #include <linux/highmem.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/errno.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/slab.h> 15 #include <linux/bitmap.h> 16 #include <linux/log2.h> 17 #include <linux/sched.h> 18 #include <linux/sched/mm.h> 19 #include <linux/sched/task.h> 20 #include <linux/delay.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/ib_addr.h> 23 #include <rdma/ib_cache.h> 24 #include <linux/mlx5/port.h> 25 #include <linux/mlx5/vport.h> 26 #include <linux/mlx5/fs.h> 27 #include <linux/mlx5/eswitch.h> 28 #include <linux/mlx5/driver.h> 29 #include <linux/list.h> 30 #include <rdma/ib_smi.h> 31 #include <rdma/ib_umem_odp.h> 32 #include <rdma/lag.h> 33 #include <linux/in.h> 34 #include <linux/etherdevice.h> 35 #include "mlx5_ib.h" 36 #include "ib_rep.h" 37 #include "cmd.h" 38 #include "devx.h" 39 #include "dm.h" 40 #include "fs.h" 41 #include "srq.h" 42 #include "qp.h" 43 #include "wr.h" 44 #include "restrack.h" 45 #include "counters.h" 46 #include "umr.h" 47 #include <rdma/uverbs_std_types.h> 48 #include <rdma/uverbs_ioctl.h> 49 #include <rdma/mlx5_user_ioctl_verbs.h> 50 #include <rdma/mlx5_user_ioctl_cmds.h> 51 #include <rdma/ib_ucaps.h> 52 #include "macsec.h" 53 #include "data_direct.h" 54 #include "dmah.h" 55 56 #define UVERBS_MODULE_NAME mlx5_ib 57 #include <rdma/uverbs_named_ioctl.h> 58 59 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 60 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 61 MODULE_LICENSE("Dual BSD/GPL"); 62 63 struct mlx5_ib_event_work { 64 struct work_struct work; 65 union { 66 struct mlx5_ib_dev *dev; 67 struct mlx5_ib_multiport_info *mpi; 68 }; 69 bool is_slave; 70 unsigned int event; 71 void *param; 72 }; 73 74 enum { 75 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 76 }; 77 78 static struct workqueue_struct *mlx5_ib_event_wq; 79 static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 80 static LIST_HEAD(mlx5_ib_dev_list); 81 /* 82 * This mutex should be held when accessing either of the above lists 83 */ 84 static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 85 86 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 87 { 88 struct mlx5_ib_dev *dev; 89 90 mutex_lock(&mlx5_ib_multiport_mutex); 91 dev = mpi->ibdev; 92 mutex_unlock(&mlx5_ib_multiport_mutex); 93 return dev; 94 } 95 96 static enum rdma_link_layer 97 mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 98 { 99 switch (port_type_cap) { 100 case MLX5_CAP_PORT_TYPE_IB: 101 return IB_LINK_LAYER_INFINIBAND; 102 case MLX5_CAP_PORT_TYPE_ETH: 103 return IB_LINK_LAYER_ETHERNET; 104 default: 105 return IB_LINK_LAYER_UNSPECIFIED; 106 } 107 } 108 109 static enum rdma_link_layer 110 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 111 { 112 struct mlx5_ib_dev *dev = to_mdev(device); 113 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 114 115 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 116 } 117 118 static int get_port_state(struct ib_device *ibdev, 119 u32 port_num, 120 enum ib_port_state *state) 121 { 122 struct ib_port_attr attr; 123 int ret; 124 125 memset(&attr, 0, sizeof(attr)); 126 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 127 if (!ret) 128 *state = attr.state; 129 return ret; 130 } 131 132 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 133 struct net_device *ndev, 134 struct net_device *upper, 135 u32 *port_num) 136 { 137 struct net_device *rep_ndev; 138 struct mlx5_ib_port *port; 139 int i; 140 141 for (i = 0; i < dev->num_ports; i++) { 142 port = &dev->port[i]; 143 if (!port->rep) 144 continue; 145 146 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 147 *port_num = i + 1; 148 return &port->roce; 149 } 150 151 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 152 continue; 153 rep_ndev = ib_device_get_netdev(&dev->ib_dev, i + 1); 154 if (rep_ndev && rep_ndev == ndev) { 155 dev_put(rep_ndev); 156 *port_num = i + 1; 157 return &port->roce; 158 } 159 160 dev_put(rep_ndev); 161 } 162 163 return NULL; 164 } 165 166 static bool mlx5_netdev_send_event(struct mlx5_ib_dev *dev, 167 struct net_device *ndev, 168 struct net_device *upper, 169 struct net_device *ib_ndev) 170 { 171 if (!dev->ib_active) 172 return false; 173 174 /* Event is about our upper device */ 175 if (upper == ndev) 176 return true; 177 178 /* RDMA device is not in lag and not in switchdev */ 179 if (!dev->is_rep && !upper && ndev == ib_ndev) 180 return true; 181 182 /* RDMA devie is in switchdev */ 183 if (dev->is_rep && ndev == ib_ndev) 184 return true; 185 186 return false; 187 } 188 189 static struct net_device *mlx5_ib_get_rep_uplink_netdev(struct mlx5_ib_dev *ibdev) 190 { 191 struct mlx5_ib_port *port; 192 int i; 193 194 for (i = 0; i < ibdev->num_ports; i++) { 195 port = &ibdev->port[i]; 196 if (port->rep && port->rep->vport == MLX5_VPORT_UPLINK) { 197 return ib_device_get_netdev(&ibdev->ib_dev, i + 1); 198 } 199 } 200 201 return NULL; 202 } 203 204 static int mlx5_netdev_event(struct notifier_block *this, 205 unsigned long event, void *ptr) 206 { 207 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 208 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 209 u32 port_num = roce->native_port_num; 210 struct net_device *ib_ndev = NULL; 211 struct mlx5_core_dev *mdev; 212 struct mlx5_ib_dev *ibdev; 213 214 ibdev = roce->dev; 215 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 216 if (!mdev) 217 return NOTIFY_DONE; 218 219 switch (event) { 220 case NETDEV_REGISTER: 221 /* Should already be registered during the load */ 222 if (ibdev->is_rep) 223 break; 224 225 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 226 /* Exit if already registered */ 227 if (ib_ndev) 228 goto put_ndev; 229 230 if (ndev->dev.parent == mdev->device) 231 ib_device_set_netdev(&ibdev->ib_dev, ndev, port_num); 232 break; 233 234 case NETDEV_UNREGISTER: 235 /* In case of reps, ib device goes away before the netdevs */ 236 if (ibdev->is_rep) 237 break; 238 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 239 if (ib_ndev == ndev) 240 ib_device_set_netdev(&ibdev->ib_dev, NULL, port_num); 241 goto put_ndev; 242 243 case NETDEV_CHANGE: 244 case NETDEV_UP: 245 case NETDEV_DOWN: { 246 struct net_device *upper = NULL; 247 248 if (!netif_is_lag_master(ndev) && !netif_is_lag_port(ndev) && 249 !mlx5_core_mp_enabled(mdev)) 250 return NOTIFY_DONE; 251 252 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 253 struct net_device *lag_ndev; 254 255 if(mlx5_lag_is_roce(mdev)) 256 lag_ndev = ib_device_get_netdev(&ibdev->ib_dev, 1); 257 else /* sriov lag */ 258 lag_ndev = mlx5_ib_get_rep_uplink_netdev(ibdev); 259 260 if (lag_ndev) { 261 upper = netdev_master_upper_dev_get(lag_ndev); 262 dev_put(lag_ndev); 263 } else { 264 goto done; 265 } 266 } 267 268 if (ibdev->is_rep) 269 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 270 if (!roce) 271 return NOTIFY_DONE; 272 273 ib_ndev = ib_device_get_netdev(&ibdev->ib_dev, port_num); 274 275 if (mlx5_netdev_send_event(ibdev, ndev, upper, ib_ndev)) { 276 struct ib_event ibev = { }; 277 enum ib_port_state port_state; 278 279 if (get_port_state(&ibdev->ib_dev, port_num, 280 &port_state)) 281 goto put_ndev; 282 283 if (roce->last_port_state == port_state) 284 goto put_ndev; 285 286 roce->last_port_state = port_state; 287 ibev.device = &ibdev->ib_dev; 288 if (port_state == IB_PORT_DOWN) 289 ibev.event = IB_EVENT_PORT_ERR; 290 else if (port_state == IB_PORT_ACTIVE) 291 ibev.event = IB_EVENT_PORT_ACTIVE; 292 else 293 goto put_ndev; 294 295 ibev.element.port_num = port_num; 296 ib_dispatch_event(&ibev); 297 } 298 break; 299 } 300 301 default: 302 break; 303 } 304 put_ndev: 305 dev_put(ib_ndev); 306 done: 307 mlx5_ib_put_native_port_mdev(ibdev, port_num); 308 return NOTIFY_DONE; 309 } 310 311 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 312 u32 ib_port_num, 313 u32 *native_port_num) 314 { 315 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 316 ib_port_num); 317 struct mlx5_core_dev *mdev = NULL; 318 struct mlx5_ib_multiport_info *mpi; 319 struct mlx5_ib_port *port; 320 321 if (ibdev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 322 if (native_port_num) 323 *native_port_num = smi_to_native_portnum(ibdev, 324 ib_port_num); 325 return ibdev->mdev; 326 327 } 328 329 if (!mlx5_core_mp_enabled(ibdev->mdev) || 330 ll != IB_LINK_LAYER_ETHERNET) { 331 if (native_port_num) 332 *native_port_num = ib_port_num; 333 return ibdev->mdev; 334 } 335 336 if (native_port_num) 337 *native_port_num = 1; 338 339 port = &ibdev->port[ib_port_num - 1]; 340 spin_lock(&port->mp.mpi_lock); 341 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 342 if (mpi && !mpi->unaffiliate) { 343 mdev = mpi->mdev; 344 /* If it's the master no need to refcount, it'll exist 345 * as long as the ib_dev exists. 346 */ 347 if (!mpi->is_master) 348 mpi->mdev_refcnt++; 349 } 350 spin_unlock(&port->mp.mpi_lock); 351 352 return mdev; 353 } 354 355 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 356 { 357 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 358 port_num); 359 struct mlx5_ib_multiport_info *mpi; 360 struct mlx5_ib_port *port; 361 362 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 363 return; 364 365 port = &ibdev->port[port_num - 1]; 366 367 spin_lock(&port->mp.mpi_lock); 368 mpi = ibdev->port[port_num - 1].mp.mpi; 369 if (mpi->is_master) 370 goto out; 371 372 mpi->mdev_refcnt--; 373 if (mpi->unaffiliate) 374 complete(&mpi->unref_comp); 375 out: 376 spin_unlock(&port->mp.mpi_lock); 377 } 378 379 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 380 u16 *active_speed, u8 *active_width) 381 { 382 switch (eth_proto_oper) { 383 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 384 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 385 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 386 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 387 *active_width = IB_WIDTH_1X; 388 *active_speed = IB_SPEED_SDR; 389 break; 390 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 391 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 392 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 393 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 394 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 395 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 396 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 397 *active_width = IB_WIDTH_1X; 398 *active_speed = IB_SPEED_QDR; 399 break; 400 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 401 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 402 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 403 *active_width = IB_WIDTH_1X; 404 *active_speed = IB_SPEED_EDR; 405 break; 406 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 407 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 408 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 409 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 410 *active_width = IB_WIDTH_4X; 411 *active_speed = IB_SPEED_QDR; 412 break; 413 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 414 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 415 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 416 *active_width = IB_WIDTH_1X; 417 *active_speed = IB_SPEED_HDR; 418 break; 419 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 420 *active_width = IB_WIDTH_4X; 421 *active_speed = IB_SPEED_FDR; 422 break; 423 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 424 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 425 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 426 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 427 *active_width = IB_WIDTH_4X; 428 *active_speed = IB_SPEED_EDR; 429 break; 430 default: 431 return -EINVAL; 432 } 433 434 return 0; 435 } 436 437 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 438 u8 *active_width) 439 { 440 switch (eth_proto_oper) { 441 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 442 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 443 *active_width = IB_WIDTH_1X; 444 *active_speed = IB_SPEED_SDR; 445 break; 446 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 447 *active_width = IB_WIDTH_1X; 448 *active_speed = IB_SPEED_DDR; 449 break; 450 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 451 *active_width = IB_WIDTH_1X; 452 *active_speed = IB_SPEED_QDR; 453 break; 454 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 455 *active_width = IB_WIDTH_4X; 456 *active_speed = IB_SPEED_QDR; 457 break; 458 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 459 *active_width = IB_WIDTH_1X; 460 *active_speed = IB_SPEED_EDR; 461 break; 462 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 463 *active_width = IB_WIDTH_2X; 464 *active_speed = IB_SPEED_EDR; 465 break; 466 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 467 *active_width = IB_WIDTH_1X; 468 *active_speed = IB_SPEED_HDR; 469 break; 470 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 471 *active_width = IB_WIDTH_4X; 472 *active_speed = IB_SPEED_EDR; 473 break; 474 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 475 *active_width = IB_WIDTH_2X; 476 *active_speed = IB_SPEED_HDR; 477 break; 478 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 479 *active_width = IB_WIDTH_1X; 480 *active_speed = IB_SPEED_NDR; 481 break; 482 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 483 *active_width = IB_WIDTH_4X; 484 *active_speed = IB_SPEED_HDR; 485 break; 486 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 487 *active_width = IB_WIDTH_2X; 488 *active_speed = IB_SPEED_NDR; 489 break; 490 case MLX5E_PROT_MASK(MLX5E_200GAUI_1_200GBASE_CR1_KR1): 491 *active_width = IB_WIDTH_1X; 492 *active_speed = IB_SPEED_XDR; 493 break; 494 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 495 *active_width = IB_WIDTH_8X; 496 *active_speed = IB_SPEED_HDR; 497 break; 498 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 499 *active_width = IB_WIDTH_4X; 500 *active_speed = IB_SPEED_NDR; 501 break; 502 case MLX5E_PROT_MASK(MLX5E_400GAUI_2_400GBASE_CR2_KR2): 503 *active_width = IB_WIDTH_2X; 504 *active_speed = IB_SPEED_XDR; 505 break; 506 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 507 *active_width = IB_WIDTH_8X; 508 *active_speed = IB_SPEED_NDR; 509 break; 510 case MLX5E_PROT_MASK(MLX5E_800GAUI_4_800GBASE_CR4_KR4): 511 *active_width = IB_WIDTH_4X; 512 *active_speed = IB_SPEED_XDR; 513 break; 514 case MLX5E_PROT_MASK(MLX5E_1600GAUI_8_1600GBASE_CR8_KR8): 515 *active_width = IB_WIDTH_8X; 516 *active_speed = IB_SPEED_XDR; 517 break; 518 default: 519 return -EINVAL; 520 } 521 522 return 0; 523 } 524 525 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 526 u8 *active_width, bool ext) 527 { 528 return ext ? 529 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 530 active_width) : 531 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 532 active_width); 533 } 534 535 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 536 struct ib_port_attr *props) 537 { 538 struct mlx5_ib_dev *dev = to_mdev(device); 539 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 540 struct mlx5_core_dev *mdev; 541 struct net_device *ndev, *upper; 542 enum ib_mtu ndev_ib_mtu; 543 bool put_mdev = true; 544 u32 eth_prot_oper; 545 u32 mdev_port_num; 546 bool ext; 547 int err; 548 549 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 550 if (!mdev) { 551 /* This means the port isn't affiliated yet. Get the 552 * info for the master port instead. 553 */ 554 put_mdev = false; 555 mdev = dev->mdev; 556 mdev_port_num = 1; 557 port_num = 1; 558 } 559 560 /* Possible bad flows are checked before filling out props so in case 561 * of an error it will still be zeroed out. 562 * Use native port in case of reps 563 */ 564 if (dev->is_rep) { 565 struct mlx5_eswitch_rep *rep; 566 567 rep = dev->port[port_num - 1].rep; 568 if (rep) { 569 mdev = mlx5_eswitch_get_core_dev(rep->esw); 570 WARN_ON(!mdev); 571 } 572 mdev_port_num = 1; 573 } 574 575 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 576 mdev_port_num, 0); 577 578 if (err) 579 goto out; 580 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 581 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 582 583 props->active_width = IB_WIDTH_4X; 584 props->active_speed = IB_SPEED_QDR; 585 586 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 587 &props->active_width, ext); 588 589 if (!dev->is_rep && dev->mdev->roce.roce_en) { 590 u16 qkey_viol_cntr; 591 592 props->port_cap_flags |= IB_PORT_CM_SUP; 593 props->ip_gids = true; 594 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 595 roce_address_table_size); 596 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 597 props->qkey_viol_cntr = qkey_viol_cntr; 598 } 599 props->max_mtu = IB_MTU_4096; 600 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 601 props->pkey_tbl_len = 1; 602 props->state = IB_PORT_DOWN; 603 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 604 605 /* If this is a stub query for an unaffiliated port stop here */ 606 if (!put_mdev) 607 goto out; 608 609 ndev = ib_device_get_netdev(device, port_num); 610 if (!ndev) 611 goto out; 612 613 if (mlx5_lag_is_roce(mdev) || mlx5_lag_is_sriov(mdev)) { 614 rcu_read_lock(); 615 upper = netdev_master_upper_dev_get_rcu(ndev); 616 if (upper) { 617 dev_put(ndev); 618 ndev = upper; 619 dev_hold(ndev); 620 } 621 rcu_read_unlock(); 622 } 623 624 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 625 props->state = IB_PORT_ACTIVE; 626 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 627 } 628 629 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 630 631 dev_put(ndev); 632 633 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 634 out: 635 if (put_mdev) 636 mlx5_ib_put_native_port_mdev(dev, port_num); 637 return err; 638 } 639 640 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 641 unsigned int index, const union ib_gid *gid, 642 const struct ib_gid_attr *attr) 643 { 644 enum ib_gid_type gid_type; 645 u16 vlan_id = 0xffff; 646 u8 roce_version = 0; 647 u8 roce_l3_type = 0; 648 u8 mac[ETH_ALEN]; 649 int ret; 650 651 gid_type = attr->gid_type; 652 if (gid) { 653 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 654 if (ret) 655 return ret; 656 } 657 658 switch (gid_type) { 659 case IB_GID_TYPE_ROCE: 660 roce_version = MLX5_ROCE_VERSION_1; 661 break; 662 case IB_GID_TYPE_ROCE_UDP_ENCAP: 663 roce_version = MLX5_ROCE_VERSION_2; 664 if (gid && ipv6_addr_v4mapped((void *)gid)) 665 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 666 else 667 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 668 break; 669 670 default: 671 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 672 } 673 674 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 675 roce_l3_type, gid->raw, mac, 676 vlan_id < VLAN_CFI_MASK, vlan_id, 677 port_num); 678 } 679 680 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 681 __always_unused void **context) 682 { 683 int ret; 684 685 ret = mlx5r_add_gid_macsec_operations(attr); 686 if (ret) 687 return ret; 688 689 return set_roce_addr(to_mdev(attr->device), attr->port_num, 690 attr->index, &attr->gid, attr); 691 } 692 693 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 694 __always_unused void **context) 695 { 696 int ret; 697 698 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 699 attr->index, NULL, attr); 700 if (ret) 701 return ret; 702 703 mlx5r_del_gid_macsec_operations(attr); 704 return 0; 705 } 706 707 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 708 const struct ib_gid_attr *attr) 709 { 710 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 711 return 0; 712 713 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 714 } 715 716 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 717 { 718 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 719 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 720 return 0; 721 } 722 723 enum { 724 MLX5_VPORT_ACCESS_METHOD_MAD, 725 MLX5_VPORT_ACCESS_METHOD_HCA, 726 MLX5_VPORT_ACCESS_METHOD_NIC, 727 }; 728 729 static int mlx5_get_vport_access_method(struct ib_device *ibdev) 730 { 731 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 732 return MLX5_VPORT_ACCESS_METHOD_MAD; 733 734 if (mlx5_ib_port_link_layer(ibdev, 1) == 735 IB_LINK_LAYER_ETHERNET) 736 return MLX5_VPORT_ACCESS_METHOD_NIC; 737 738 return MLX5_VPORT_ACCESS_METHOD_HCA; 739 } 740 741 static void get_atomic_caps(struct mlx5_ib_dev *dev, 742 u8 atomic_size_qp, 743 struct ib_device_attr *props) 744 { 745 u8 tmp; 746 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 747 u8 atomic_req_8B_endianness_mode = 748 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 749 750 /* Check if HW supports 8 bytes standard atomic operations and capable 751 * of host endianness respond 752 */ 753 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 754 if (((atomic_operations & tmp) == tmp) && 755 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 756 (atomic_req_8B_endianness_mode)) { 757 props->atomic_cap = IB_ATOMIC_HCA; 758 } else { 759 props->atomic_cap = IB_ATOMIC_NONE; 760 } 761 } 762 763 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 764 struct ib_device_attr *props) 765 { 766 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 767 768 get_atomic_caps(dev, atomic_size_qp, props); 769 } 770 771 static int mlx5_query_system_image_guid(struct ib_device *ibdev, 772 __be64 *sys_image_guid) 773 { 774 struct mlx5_ib_dev *dev = to_mdev(ibdev); 775 struct mlx5_core_dev *mdev = dev->mdev; 776 u64 tmp; 777 int err; 778 779 switch (mlx5_get_vport_access_method(ibdev)) { 780 case MLX5_VPORT_ACCESS_METHOD_MAD: 781 return mlx5_query_mad_ifc_system_image_guid(ibdev, 782 sys_image_guid); 783 784 case MLX5_VPORT_ACCESS_METHOD_HCA: 785 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 786 break; 787 788 case MLX5_VPORT_ACCESS_METHOD_NIC: 789 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 790 break; 791 792 default: 793 return -EINVAL; 794 } 795 796 if (!err) 797 *sys_image_guid = cpu_to_be64(tmp); 798 799 return err; 800 801 } 802 803 static int mlx5_query_max_pkeys(struct ib_device *ibdev, 804 u16 *max_pkeys) 805 { 806 struct mlx5_ib_dev *dev = to_mdev(ibdev); 807 struct mlx5_core_dev *mdev = dev->mdev; 808 809 switch (mlx5_get_vport_access_method(ibdev)) { 810 case MLX5_VPORT_ACCESS_METHOD_MAD: 811 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 812 813 case MLX5_VPORT_ACCESS_METHOD_HCA: 814 case MLX5_VPORT_ACCESS_METHOD_NIC: 815 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 816 pkey_table_size)); 817 return 0; 818 819 default: 820 return -EINVAL; 821 } 822 } 823 824 static int mlx5_query_vendor_id(struct ib_device *ibdev, 825 u32 *vendor_id) 826 { 827 struct mlx5_ib_dev *dev = to_mdev(ibdev); 828 829 switch (mlx5_get_vport_access_method(ibdev)) { 830 case MLX5_VPORT_ACCESS_METHOD_MAD: 831 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 832 833 case MLX5_VPORT_ACCESS_METHOD_HCA: 834 case MLX5_VPORT_ACCESS_METHOD_NIC: 835 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 836 837 default: 838 return -EINVAL; 839 } 840 } 841 842 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 843 __be64 *node_guid) 844 { 845 u64 tmp; 846 int err; 847 848 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 849 case MLX5_VPORT_ACCESS_METHOD_MAD: 850 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 851 852 case MLX5_VPORT_ACCESS_METHOD_HCA: 853 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 854 break; 855 856 case MLX5_VPORT_ACCESS_METHOD_NIC: 857 err = mlx5_query_nic_vport_node_guid(dev->mdev, 0, false, &tmp); 858 break; 859 860 default: 861 return -EINVAL; 862 } 863 864 if (!err) 865 *node_guid = cpu_to_be64(tmp); 866 867 return err; 868 } 869 870 struct mlx5_reg_node_desc { 871 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 872 }; 873 874 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 875 { 876 struct mlx5_reg_node_desc in; 877 878 if (mlx5_use_mad_ifc(dev)) 879 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 880 881 memset(&in, 0, sizeof(in)); 882 883 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 884 sizeof(struct mlx5_reg_node_desc), 885 MLX5_REG_NODE_DESC, 0, 0); 886 } 887 888 static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev, 889 struct mlx5_ib_query_device_resp *resp) 890 { 891 struct mlx5_eswitch *esw = mdev->priv.eswitch; 892 u16 vport = mlx5_eswitch_manager_vport(mdev); 893 894 resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw, 895 vport); 896 resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask(); 897 } 898 899 /* 900 * Calculate maximum SQ overhead across all QP types. 901 * Other QP types (REG_UMR, UC, RC, UD/SMI/GSI, XRC_TGT) 902 * have smaller overhead than the types calculated below, 903 * so they are implicitly included. 904 */ 905 static u32 mlx5_ib_calc_max_sq_overhead(void) 906 { 907 u32 max_overhead_xrc, overhead_ud_lso, a, b; 908 909 /* XRC_INI */ 910 max_overhead_xrc = sizeof(struct mlx5_wqe_xrc_seg); 911 max_overhead_xrc += sizeof(struct mlx5_wqe_ctrl_seg); 912 a = sizeof(struct mlx5_wqe_atomic_seg) + 913 sizeof(struct mlx5_wqe_raddr_seg); 914 b = sizeof(struct mlx5_wqe_umr_ctrl_seg) + 915 sizeof(struct mlx5_mkey_seg) + 916 MLX5_IB_SQ_UMR_INLINE_THRESHOLD / MLX5_IB_UMR_OCTOWORD; 917 max_overhead_xrc += max(a, b); 918 919 /* UD with LSO */ 920 overhead_ud_lso = sizeof(struct mlx5_wqe_ctrl_seg); 921 overhead_ud_lso += sizeof(struct mlx5_wqe_eth_pad); 922 overhead_ud_lso += sizeof(struct mlx5_wqe_eth_seg); 923 overhead_ud_lso += sizeof(struct mlx5_wqe_datagram_seg); 924 925 return max(max_overhead_xrc, overhead_ud_lso); 926 } 927 928 static u32 mlx5_ib_calc_max_qp_wr(struct mlx5_ib_dev *dev) 929 { 930 struct mlx5_core_dev *mdev = dev->mdev; 931 u32 max_wqe_bb_units = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 932 u32 max_wqe_size; 933 /* max QP overhead + 1 SGE, no inline, no special features */ 934 max_wqe_size = mlx5_ib_calc_max_sq_overhead() + 935 sizeof(struct mlx5_wqe_data_seg); 936 937 max_wqe_size = roundup_pow_of_two(max_wqe_size); 938 939 max_wqe_size = ALIGN(max_wqe_size, MLX5_SEND_WQE_BB); 940 941 return (max_wqe_bb_units * MLX5_SEND_WQE_BB) / max_wqe_size; 942 } 943 944 static int mlx5_ib_query_device(struct ib_device *ibdev, 945 struct ib_device_attr *props, 946 struct ib_udata *uhw) 947 { 948 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 949 struct mlx5_ib_dev *dev = to_mdev(ibdev); 950 struct mlx5_core_dev *mdev = dev->mdev; 951 int err = -ENOMEM; 952 int max_sq_desc; 953 int max_rq_sg; 954 int max_sq_sg; 955 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 956 bool raw_support = !mlx5_core_mp_enabled(mdev); 957 struct mlx5_ib_query_device_resp resp = {}; 958 size_t resp_len; 959 u64 max_tso; 960 961 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 962 if (uhw_outlen && uhw_outlen < resp_len) 963 return -EINVAL; 964 965 resp.response_length = resp_len; 966 967 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 968 return -EINVAL; 969 970 memset(props, 0, sizeof(*props)); 971 err = mlx5_query_system_image_guid(ibdev, 972 &props->sys_image_guid); 973 if (err) 974 return err; 975 976 props->max_pkeys = dev->pkey_table_len; 977 978 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 979 if (err) 980 return err; 981 982 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 983 (fw_rev_min(dev->mdev) << 16) | 984 fw_rev_sub(dev->mdev); 985 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 986 IB_DEVICE_PORT_ACTIVE_EVENT | 987 IB_DEVICE_SYS_IMAGE_GUID | 988 IB_DEVICE_RC_RNR_NAK_GEN; 989 990 if (MLX5_CAP_GEN(mdev, pkv)) 991 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 992 if (MLX5_CAP_GEN(mdev, qkv)) 993 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 994 if (MLX5_CAP_GEN(mdev, apm)) 995 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 996 if (MLX5_CAP_GEN(mdev, xrc)) 997 props->device_cap_flags |= IB_DEVICE_XRC; 998 if (MLX5_CAP_GEN(mdev, imaicl)) { 999 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 1000 IB_DEVICE_MEM_WINDOW_TYPE_2B; 1001 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1002 /* We support 'Gappy' memory registration too */ 1003 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 1004 } 1005 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 1006 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 1007 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 1008 if (MLX5_CAP_GEN(mdev, sho)) { 1009 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 1010 /* At this stage no support for signature handover */ 1011 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 1012 IB_PROT_T10DIF_TYPE_2 | 1013 IB_PROT_T10DIF_TYPE_3; 1014 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 1015 IB_GUARD_T10DIF_CSUM; 1016 } 1017 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 1018 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 1019 1020 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 1021 if (MLX5_CAP_ETH(mdev, csum_cap)) { 1022 /* Legacy bit to support old userspace libraries */ 1023 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 1024 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 1025 } 1026 1027 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 1028 props->raw_packet_caps |= 1029 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 1030 1031 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 1032 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 1033 if (max_tso) { 1034 resp.tso_caps.max_tso = 1 << max_tso; 1035 resp.tso_caps.supported_qpts |= 1036 1 << IB_QPT_RAW_PACKET; 1037 resp.response_length += sizeof(resp.tso_caps); 1038 } 1039 } 1040 1041 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 1042 resp.rss_caps.rx_hash_function = 1043 MLX5_RX_HASH_FUNC_TOEPLITZ; 1044 resp.rss_caps.rx_hash_fields_mask = 1045 MLX5_RX_HASH_SRC_IPV4 | 1046 MLX5_RX_HASH_DST_IPV4 | 1047 MLX5_RX_HASH_SRC_IPV6 | 1048 MLX5_RX_HASH_DST_IPV6 | 1049 MLX5_RX_HASH_SRC_PORT_TCP | 1050 MLX5_RX_HASH_DST_PORT_TCP | 1051 MLX5_RX_HASH_SRC_PORT_UDP | 1052 MLX5_RX_HASH_DST_PORT_UDP | 1053 MLX5_RX_HASH_INNER; 1054 resp.response_length += sizeof(resp.rss_caps); 1055 } 1056 } else { 1057 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 1058 resp.response_length += sizeof(resp.tso_caps); 1059 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 1060 resp.response_length += sizeof(resp.rss_caps); 1061 } 1062 1063 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 1064 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1065 props->kernel_cap_flags |= IBK_UD_TSO; 1066 } 1067 1068 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 1069 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 1070 raw_support) 1071 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 1072 1073 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 1074 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 1075 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 1076 1077 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 1078 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 1079 raw_support) { 1080 /* Legacy bit to support old userspace libraries */ 1081 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 1082 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 1083 } 1084 1085 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 1086 props->max_dm_size = 1087 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 1088 } 1089 1090 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 1091 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 1092 1093 if (MLX5_CAP_GEN(mdev, end_pad)) 1094 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 1095 1096 props->vendor_part_id = mdev->pdev->device; 1097 props->hw_ver = mdev->pdev->revision; 1098 1099 props->max_mr_size = ~0ull; 1100 props->page_size_cap = ~(min_page_size - 1); 1101 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 1102 props->max_qp_wr = mlx5_ib_calc_max_qp_wr(dev); 1103 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 1104 sizeof(struct mlx5_wqe_data_seg); 1105 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 1106 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 1107 sizeof(struct mlx5_wqe_raddr_seg)) / 1108 sizeof(struct mlx5_wqe_data_seg); 1109 props->max_send_sge = max_sq_sg; 1110 props->max_recv_sge = max_rq_sg; 1111 props->max_sge_rd = MLX5_MAX_SGE_RD; 1112 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 1113 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 1114 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1115 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 1116 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 1117 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 1118 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 1119 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 1120 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 1121 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 1122 props->max_srq_sge = max_rq_sg - 1; 1123 props->max_fast_reg_page_list_len = 1124 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1125 props->max_pi_fast_reg_page_list_len = 1126 props->max_fast_reg_page_list_len / 2; 1127 props->max_sgl_rd = 1128 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1129 get_atomic_caps_qp(dev, props); 1130 props->masked_atomic_cap = IB_ATOMIC_NONE; 1131 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1132 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1133 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1134 props->max_mcast_grp; 1135 props->max_ah = INT_MAX; 1136 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1137 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1138 1139 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1140 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1141 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1142 props->odp_caps = dev->odp_caps; 1143 if (!uhw) { 1144 /* ODP for kernel QPs is not implemented for receive 1145 * WQEs and SRQ WQEs 1146 */ 1147 props->odp_caps.per_transport_caps.rc_odp_caps &= 1148 ~(IB_ODP_SUPPORT_READ | 1149 IB_ODP_SUPPORT_SRQ_RECV); 1150 props->odp_caps.per_transport_caps.uc_odp_caps &= 1151 ~(IB_ODP_SUPPORT_READ | 1152 IB_ODP_SUPPORT_SRQ_RECV); 1153 props->odp_caps.per_transport_caps.ud_odp_caps &= 1154 ~(IB_ODP_SUPPORT_READ | 1155 IB_ODP_SUPPORT_SRQ_RECV); 1156 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1157 ~(IB_ODP_SUPPORT_READ | 1158 IB_ODP_SUPPORT_SRQ_RECV); 1159 } 1160 } 1161 1162 if (mlx5_core_is_vf(mdev)) 1163 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1164 1165 if (mlx5_ib_port_link_layer(ibdev, 1) == 1166 IB_LINK_LAYER_ETHERNET && raw_support) { 1167 props->rss_caps.max_rwq_indirection_tables = 1168 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1169 props->rss_caps.max_rwq_indirection_table_size = 1170 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1171 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1172 props->max_wq_type_rq = 1173 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1174 } 1175 1176 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1177 props->tm_caps.max_num_tags = 1178 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1179 props->tm_caps.max_ops = 1180 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1181 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1182 } 1183 1184 if (MLX5_CAP_GEN(mdev, tag_matching) && 1185 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1186 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1187 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1188 } 1189 1190 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1191 props->cq_caps.max_cq_moderation_count = 1192 MLX5_MAX_CQ_COUNT; 1193 props->cq_caps.max_cq_moderation_period = 1194 MLX5_MAX_CQ_PERIOD; 1195 } 1196 1197 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1198 resp.response_length += sizeof(resp.cqe_comp_caps); 1199 1200 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1201 resp.cqe_comp_caps.max_num = 1202 MLX5_CAP_GEN(dev->mdev, 1203 cqe_compression_max_num); 1204 1205 resp.cqe_comp_caps.supported_format = 1206 MLX5_IB_CQE_RES_FORMAT_HASH | 1207 MLX5_IB_CQE_RES_FORMAT_CSUM; 1208 1209 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1210 resp.cqe_comp_caps.supported_format |= 1211 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1212 } 1213 } 1214 1215 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1216 raw_support) { 1217 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1218 MLX5_CAP_GEN(mdev, qos)) { 1219 resp.packet_pacing_caps.qp_rate_limit_max = 1220 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1221 resp.packet_pacing_caps.qp_rate_limit_min = 1222 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1223 resp.packet_pacing_caps.supported_qpts |= 1224 1 << IB_QPT_RAW_PACKET; 1225 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1226 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1227 resp.packet_pacing_caps.cap_flags |= 1228 MLX5_IB_PP_SUPPORT_BURST; 1229 } 1230 resp.response_length += sizeof(resp.packet_pacing_caps); 1231 } 1232 1233 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1234 uhw_outlen) { 1235 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1236 resp.mlx5_ib_support_multi_pkt_send_wqes = 1237 MLX5_IB_ALLOW_MPW; 1238 1239 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1240 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1241 MLX5_IB_SUPPORT_EMPW; 1242 1243 resp.response_length += 1244 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1245 } 1246 1247 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1248 resp.response_length += sizeof(resp.flags); 1249 1250 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1251 resp.flags |= 1252 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1253 1254 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1255 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1256 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1257 resp.flags |= 1258 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1259 1260 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1261 1262 if (MLX5_CAP_GEN_2(mdev, dp_ordering_force) && 1263 (MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_xrc) || 1264 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_dc) || 1265 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_rc) || 1266 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_ud) || 1267 MLX5_CAP_GEN(mdev, dp_ordering_ooo_all_uc))) 1268 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_OOO_DP; 1269 } 1270 1271 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1272 resp.response_length += sizeof(resp.sw_parsing_caps); 1273 if (MLX5_CAP_ETH(mdev, swp)) { 1274 resp.sw_parsing_caps.sw_parsing_offloads |= 1275 MLX5_IB_SW_PARSING; 1276 1277 if (MLX5_CAP_ETH(mdev, swp_csum)) 1278 resp.sw_parsing_caps.sw_parsing_offloads |= 1279 MLX5_IB_SW_PARSING_CSUM; 1280 1281 if (MLX5_CAP_ETH(mdev, swp_lso)) 1282 resp.sw_parsing_caps.sw_parsing_offloads |= 1283 MLX5_IB_SW_PARSING_LSO; 1284 1285 if (resp.sw_parsing_caps.sw_parsing_offloads) 1286 resp.sw_parsing_caps.supported_qpts = 1287 BIT(IB_QPT_RAW_PACKET); 1288 } 1289 } 1290 1291 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1292 raw_support) { 1293 resp.response_length += sizeof(resp.striding_rq_caps); 1294 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1295 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1296 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1297 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1298 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1299 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1300 resp.striding_rq_caps 1301 .min_single_wqe_log_num_of_strides = 1302 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1303 else 1304 resp.striding_rq_caps 1305 .min_single_wqe_log_num_of_strides = 1306 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1307 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1308 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1309 resp.striding_rq_caps.supported_qpts = 1310 BIT(IB_QPT_RAW_PACKET); 1311 } 1312 } 1313 1314 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1315 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1316 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1317 resp.tunnel_offloads_caps |= 1318 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1319 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1320 resp.tunnel_offloads_caps |= 1321 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1322 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1323 resp.tunnel_offloads_caps |= 1324 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1325 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1326 resp.tunnel_offloads_caps |= 1327 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1328 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1329 resp.tunnel_offloads_caps |= 1330 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1331 } 1332 1333 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1334 resp.response_length += sizeof(resp.dci_streams_caps); 1335 1336 resp.dci_streams_caps.max_log_num_concurent = 1337 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1338 1339 resp.dci_streams_caps.max_log_num_errored = 1340 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1341 } 1342 1343 if (offsetofend(typeof(resp), reserved) <= uhw_outlen) 1344 resp.response_length += sizeof(resp.reserved); 1345 1346 if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) { 1347 struct mlx5_eswitch *esw = mdev->priv.eswitch; 1348 1349 resp.response_length += sizeof(resp.reg_c0); 1350 1351 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS && 1352 mlx5_eswitch_vport_match_metadata_enabled(esw)) 1353 fill_esw_mgr_reg_c0(mdev, &resp); 1354 } 1355 1356 if (uhw_outlen) { 1357 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1358 1359 if (err) 1360 return err; 1361 } 1362 1363 return 0; 1364 } 1365 1366 static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1367 u8 *ib_width) 1368 { 1369 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1370 1371 if (active_width & MLX5_PTYS_WIDTH_1X) 1372 *ib_width = IB_WIDTH_1X; 1373 else if (active_width & MLX5_PTYS_WIDTH_2X) 1374 *ib_width = IB_WIDTH_2X; 1375 else if (active_width & MLX5_PTYS_WIDTH_4X) 1376 *ib_width = IB_WIDTH_4X; 1377 else if (active_width & MLX5_PTYS_WIDTH_8X) 1378 *ib_width = IB_WIDTH_8X; 1379 else if (active_width & MLX5_PTYS_WIDTH_12X) 1380 *ib_width = IB_WIDTH_12X; 1381 else { 1382 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1383 active_width); 1384 *ib_width = IB_WIDTH_4X; 1385 } 1386 1387 return; 1388 } 1389 1390 static int mlx5_mtu_to_ib_mtu(int mtu) 1391 { 1392 switch (mtu) { 1393 case 256: return 1; 1394 case 512: return 2; 1395 case 1024: return 3; 1396 case 2048: return 4; 1397 case 4096: return 5; 1398 default: 1399 pr_warn("invalid mtu\n"); 1400 return -1; 1401 } 1402 } 1403 1404 enum ib_max_vl_num { 1405 __IB_MAX_VL_0 = 1, 1406 __IB_MAX_VL_0_1 = 2, 1407 __IB_MAX_VL_0_3 = 3, 1408 __IB_MAX_VL_0_7 = 4, 1409 __IB_MAX_VL_0_14 = 5, 1410 }; 1411 1412 enum mlx5_vl_hw_cap { 1413 MLX5_VL_HW_0 = 1, 1414 MLX5_VL_HW_0_1 = 2, 1415 MLX5_VL_HW_0_2 = 3, 1416 MLX5_VL_HW_0_3 = 4, 1417 MLX5_VL_HW_0_4 = 5, 1418 MLX5_VL_HW_0_5 = 6, 1419 MLX5_VL_HW_0_6 = 7, 1420 MLX5_VL_HW_0_7 = 8, 1421 MLX5_VL_HW_0_14 = 15 1422 }; 1423 1424 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1425 u8 *max_vl_num) 1426 { 1427 switch (vl_hw_cap) { 1428 case MLX5_VL_HW_0: 1429 *max_vl_num = __IB_MAX_VL_0; 1430 break; 1431 case MLX5_VL_HW_0_1: 1432 *max_vl_num = __IB_MAX_VL_0_1; 1433 break; 1434 case MLX5_VL_HW_0_3: 1435 *max_vl_num = __IB_MAX_VL_0_3; 1436 break; 1437 case MLX5_VL_HW_0_7: 1438 *max_vl_num = __IB_MAX_VL_0_7; 1439 break; 1440 case MLX5_VL_HW_0_14: 1441 *max_vl_num = __IB_MAX_VL_0_14; 1442 break; 1443 1444 default: 1445 return -EINVAL; 1446 } 1447 1448 return 0; 1449 } 1450 1451 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1452 struct ib_port_attr *props) 1453 { 1454 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1455 struct mlx5_core_dev *mdev = dev->mdev; 1456 struct mlx5_hca_vport_context *rep; 1457 u8 vl_hw_cap, plane_index = 0; 1458 u16 max_mtu; 1459 u16 oper_mtu; 1460 int err; 1461 u16 ib_link_width_oper; 1462 1463 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1464 if (!rep) { 1465 err = -ENOMEM; 1466 goto out; 1467 } 1468 1469 /* props being zeroed by the caller, avoid zeroing it here */ 1470 1471 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) { 1472 plane_index = port; 1473 port = smi_to_native_portnum(dev, port); 1474 } 1475 1476 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1477 if (err) 1478 goto out; 1479 1480 props->lid = rep->lid; 1481 props->lmc = rep->lmc; 1482 props->sm_lid = rep->sm_lid; 1483 props->sm_sl = rep->sm_sl; 1484 props->state = rep->vport_state; 1485 props->phys_state = rep->port_physical_state; 1486 1487 props->port_cap_flags = rep->cap_mask1; 1488 if (dev->num_plane) { 1489 props->port_cap_flags |= IB_PORT_SM_DISABLED; 1490 props->port_cap_flags &= ~IB_PORT_SM; 1491 } else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 1492 props->port_cap_flags &= ~IB_PORT_CM_SUP; 1493 1494 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1495 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1496 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1497 props->bad_pkey_cntr = rep->pkey_violation_counter; 1498 props->qkey_viol_cntr = rep->qkey_violation_counter; 1499 props->subnet_timeout = rep->subnet_timeout; 1500 props->init_type_reply = rep->init_type_reply; 1501 1502 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1503 props->port_cap_flags2 = rep->cap_mask2; 1504 1505 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1506 &props->active_speed, port, plane_index); 1507 if (err) 1508 goto out; 1509 1510 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1511 1512 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1513 1514 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1515 1516 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1517 1518 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1519 1520 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1521 if (err) 1522 goto out; 1523 1524 err = translate_max_vl_num(ibdev, vl_hw_cap, 1525 &props->max_vl_num); 1526 out: 1527 kfree(rep); 1528 return err; 1529 } 1530 1531 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1532 struct ib_port_attr *props) 1533 { 1534 unsigned int count; 1535 int ret; 1536 1537 switch (mlx5_get_vport_access_method(ibdev)) { 1538 case MLX5_VPORT_ACCESS_METHOD_MAD: 1539 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1540 break; 1541 1542 case MLX5_VPORT_ACCESS_METHOD_HCA: 1543 ret = mlx5_query_hca_port(ibdev, port, props); 1544 break; 1545 1546 case MLX5_VPORT_ACCESS_METHOD_NIC: 1547 ret = mlx5_query_port_roce(ibdev, port, props); 1548 break; 1549 1550 default: 1551 ret = -EINVAL; 1552 } 1553 1554 if (!ret && props) { 1555 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1556 struct mlx5_core_dev *mdev; 1557 bool put_mdev = true; 1558 1559 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1560 if (!mdev) { 1561 /* If the port isn't affiliated yet query the master. 1562 * The master and slave will have the same values. 1563 */ 1564 mdev = dev->mdev; 1565 port = 1; 1566 put_mdev = false; 1567 } 1568 count = mlx5_core_reserved_gids_count(mdev); 1569 if (put_mdev) 1570 mlx5_ib_put_native_port_mdev(dev, port); 1571 props->gid_tbl_len -= count; 1572 } 1573 return ret; 1574 } 1575 1576 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1577 struct ib_port_attr *props) 1578 { 1579 return mlx5_query_port_roce(ibdev, port, props); 1580 } 1581 1582 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1583 u16 *pkey) 1584 { 1585 /* Default special Pkey for representor device port as per the 1586 * IB specification 1.3 section 10.9.1.2. 1587 */ 1588 *pkey = 0xffff; 1589 return 0; 1590 } 1591 1592 static int mlx5_ib_query_port_speed_from_port(struct mlx5_ib_dev *dev, 1593 u32 port_num, u64 *speed) 1594 { 1595 struct ib_port_speed_info speed_info; 1596 struct ib_port_attr attr = {}; 1597 int err; 1598 1599 err = mlx5_ib_query_port(&dev->ib_dev, port_num, &attr); 1600 if (err) 1601 return err; 1602 1603 if (attr.state == IB_PORT_DOWN) { 1604 *speed = 0; 1605 return 0; 1606 } 1607 1608 err = ib_port_attr_to_speed_info(&attr, &speed_info); 1609 if (err) 1610 return err; 1611 1612 *speed = speed_info.rate; 1613 return 0; 1614 } 1615 1616 static int mlx5_ib_query_port_speed_from_vport(struct mlx5_core_dev *mdev, 1617 u8 op_mod, u16 vport, 1618 u8 other_vport, u64 *speed, 1619 struct mlx5_ib_dev *dev, 1620 u32 port_num) 1621 { 1622 u32 max_tx_speed; 1623 int err; 1624 1625 err = mlx5_query_vport_max_tx_speed(mdev, op_mod, vport, other_vport, 1626 &max_tx_speed); 1627 if (err) 1628 return err; 1629 1630 if (max_tx_speed == 0) 1631 /* Value 0 indicates field not supported, fallback */ 1632 return mlx5_ib_query_port_speed_from_port(dev, port_num, 1633 speed); 1634 1635 *speed = max_tx_speed; 1636 return 0; 1637 } 1638 1639 static int mlx5_ib_query_port_speed_from_bond(struct mlx5_ib_dev *dev, 1640 u32 port_num, u64 *speed) 1641 { 1642 struct mlx5_core_dev *mdev = dev->mdev; 1643 u32 bond_speed; 1644 int err; 1645 1646 err = mlx5_lag_query_bond_speed(mdev, &bond_speed); 1647 if (err) 1648 return err; 1649 1650 *speed = bond_speed / MLX5_MAX_TX_SPEED_UNIT; 1651 1652 return 0; 1653 } 1654 1655 static int mlx5_ib_query_port_speed_non_rep(struct mlx5_ib_dev *dev, 1656 u32 port_num, u64 *speed) 1657 { 1658 u16 op_mod = MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT; 1659 1660 if (mlx5_lag_is_roce(dev->mdev)) 1661 return mlx5_ib_query_port_speed_from_bond(dev, port_num, 1662 speed); 1663 1664 return mlx5_ib_query_port_speed_from_vport(dev->mdev, op_mod, 0, false, 1665 speed, dev, port_num); 1666 } 1667 1668 static int mlx5_ib_query_port_speed_rep(struct mlx5_ib_dev *dev, u32 port_num, 1669 u64 *speed) 1670 { 1671 struct mlx5_eswitch_rep *rep; 1672 struct mlx5_core_dev *mdev; 1673 u16 op_mod; 1674 1675 if (!dev->port[port_num - 1].rep) { 1676 mlx5_ib_warn(dev, "Representor doesn't exist for port %u\n", 1677 port_num); 1678 return -EINVAL; 1679 } 1680 1681 rep = dev->port[port_num - 1].rep; 1682 mdev = mlx5_eswitch_get_core_dev(rep->esw); 1683 if (!mdev) 1684 return -ENODEV; 1685 1686 if (rep->vport == MLX5_VPORT_UPLINK) { 1687 if (mlx5_lag_is_sriov(mdev)) 1688 return mlx5_ib_query_port_speed_from_bond(dev, 1689 port_num, 1690 speed); 1691 1692 return mlx5_ib_query_port_speed_from_port(dev, port_num, 1693 speed); 1694 } 1695 1696 op_mod = MLX5_VPORT_STATE_OP_MOD_ESW_VPORT; 1697 return mlx5_ib_query_port_speed_from_vport(dev->mdev, op_mod, 1698 rep->vport, true, speed, dev, 1699 port_num); 1700 } 1701 1702 int mlx5_ib_query_port_speed(struct ib_device *ibdev, u32 port_num, u64 *speed) 1703 { 1704 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1705 1706 if (mlx5_ib_port_link_layer(ibdev, port_num) == 1707 IB_LINK_LAYER_INFINIBAND || mlx5_core_mp_enabled(dev->mdev)) 1708 return mlx5_ib_query_port_speed_from_port(dev, port_num, speed); 1709 else if (!dev->is_rep) 1710 return mlx5_ib_query_port_speed_non_rep(dev, port_num, speed); 1711 else 1712 return mlx5_ib_query_port_speed_rep(dev, port_num, speed); 1713 } 1714 1715 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1716 union ib_gid *gid) 1717 { 1718 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1719 struct mlx5_core_dev *mdev = dev->mdev; 1720 1721 switch (mlx5_get_vport_access_method(ibdev)) { 1722 case MLX5_VPORT_ACCESS_METHOD_MAD: 1723 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1724 1725 case MLX5_VPORT_ACCESS_METHOD_HCA: 1726 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1727 1728 default: 1729 return -EINVAL; 1730 } 1731 1732 } 1733 1734 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1735 u16 index, u16 *pkey) 1736 { 1737 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1738 struct mlx5_core_dev *mdev; 1739 bool put_mdev = true; 1740 u32 mdev_port_num; 1741 int err; 1742 1743 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1744 if (!mdev) { 1745 /* The port isn't affiliated yet, get the PKey from the master 1746 * port. For RoCE the PKey tables will be the same. 1747 */ 1748 put_mdev = false; 1749 mdev = dev->mdev; 1750 mdev_port_num = 1; 1751 } 1752 1753 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1754 index, pkey); 1755 if (put_mdev) 1756 mlx5_ib_put_native_port_mdev(dev, port); 1757 1758 return err; 1759 } 1760 1761 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1762 u16 *pkey) 1763 { 1764 switch (mlx5_get_vport_access_method(ibdev)) { 1765 case MLX5_VPORT_ACCESS_METHOD_MAD: 1766 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1767 1768 case MLX5_VPORT_ACCESS_METHOD_HCA: 1769 case MLX5_VPORT_ACCESS_METHOD_NIC: 1770 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1771 default: 1772 return -EINVAL; 1773 } 1774 } 1775 1776 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1777 struct ib_device_modify *props) 1778 { 1779 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1780 struct mlx5_reg_node_desc in; 1781 struct mlx5_reg_node_desc out; 1782 int err; 1783 1784 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1785 return -EOPNOTSUPP; 1786 1787 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1788 return 0; 1789 1790 /* 1791 * If possible, pass node desc to FW, so it can generate 1792 * a 144 trap. If cmd fails, just ignore. 1793 */ 1794 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1795 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1796 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1797 if (err) 1798 return err; 1799 1800 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1801 1802 return err; 1803 } 1804 1805 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1806 u32 value) 1807 { 1808 struct mlx5_hca_vport_context ctx = {}; 1809 struct mlx5_core_dev *mdev; 1810 u32 mdev_port_num; 1811 int err; 1812 1813 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1814 if (!mdev) 1815 return -ENODEV; 1816 1817 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1818 if (err) 1819 goto out; 1820 1821 if (~ctx.cap_mask1_perm & mask) { 1822 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1823 mask, ctx.cap_mask1_perm); 1824 err = -EINVAL; 1825 goto out; 1826 } 1827 1828 ctx.cap_mask1 = value; 1829 ctx.cap_mask1_perm = mask; 1830 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1831 0, &ctx); 1832 1833 out: 1834 mlx5_ib_put_native_port_mdev(dev, port_num); 1835 1836 return err; 1837 } 1838 1839 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1840 struct ib_port_modify *props) 1841 { 1842 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1843 struct ib_port_attr attr; 1844 u32 tmp; 1845 int err; 1846 u32 change_mask; 1847 u32 value; 1848 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1849 IB_LINK_LAYER_INFINIBAND); 1850 1851 /* CM layer calls ib_modify_port() regardless of the link layer. For 1852 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1853 */ 1854 if (!is_ib) 1855 return 0; 1856 1857 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1858 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1859 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1860 return set_port_caps_atomic(dev, port, change_mask, value); 1861 } 1862 1863 mutex_lock(&dev->cap_mask_mutex); 1864 1865 err = ib_query_port(ibdev, port, &attr); 1866 if (err) 1867 goto out; 1868 1869 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1870 ~props->clr_port_cap_mask; 1871 1872 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1873 1874 out: 1875 mutex_unlock(&dev->cap_mask_mutex); 1876 return err; 1877 } 1878 1879 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1880 { 1881 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1882 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1883 } 1884 1885 static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1886 { 1887 /* Large page with non 4k uar support might limit the dynamic size */ 1888 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1889 return MLX5_MIN_DYN_BFREGS; 1890 1891 return MLX5_MAX_DYN_BFREGS; 1892 } 1893 1894 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1895 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1896 struct mlx5_bfreg_info *bfregi) 1897 { 1898 int uars_per_sys_page; 1899 int bfregs_per_sys_page; 1900 int ref_bfregs = req->total_num_bfregs; 1901 1902 if (req->total_num_bfregs == 0) 1903 return -EINVAL; 1904 1905 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1906 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1907 1908 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1909 return -ENOMEM; 1910 1911 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1912 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1913 /* This holds the required static allocation asked by the user */ 1914 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1915 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1916 return -EINVAL; 1917 1918 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1919 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1920 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1921 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1922 1923 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1924 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1925 lib_uar_4k ? "yes" : "no", ref_bfregs, 1926 req->total_num_bfregs, bfregi->total_num_bfregs, 1927 bfregi->num_sys_pages); 1928 1929 return 0; 1930 } 1931 1932 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1933 { 1934 struct mlx5_bfreg_info *bfregi; 1935 int err; 1936 int i; 1937 1938 bfregi = &context->bfregi; 1939 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1940 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1941 context->devx_uid); 1942 if (err) 1943 goto error; 1944 1945 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1946 } 1947 1948 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1949 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1950 1951 return 0; 1952 1953 error: 1954 for (--i; i >= 0; i--) 1955 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1956 context->devx_uid)) 1957 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1958 1959 return err; 1960 } 1961 1962 static void deallocate_uars(struct mlx5_ib_dev *dev, 1963 struct mlx5_ib_ucontext *context) 1964 { 1965 struct mlx5_bfreg_info *bfregi; 1966 int i; 1967 1968 bfregi = &context->bfregi; 1969 for (i = 0; i < bfregi->num_sys_pages; i++) 1970 if (i < bfregi->num_static_sys_pages || 1971 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1972 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1973 context->devx_uid); 1974 } 1975 1976 static int mlx5_ib_enable_lb_mp(struct mlx5_core_dev *master, 1977 struct mlx5_core_dev *slave, 1978 struct mlx5_ib_lb_state *lb_state) 1979 { 1980 int err; 1981 1982 err = mlx5_nic_vport_update_local_lb(master, true); 1983 if (err) 1984 return err; 1985 1986 err = mlx5_nic_vport_update_local_lb(slave, true); 1987 if (err) 1988 goto out; 1989 1990 lb_state->force_enable = true; 1991 return 0; 1992 1993 out: 1994 mlx5_nic_vport_update_local_lb(master, false); 1995 return err; 1996 } 1997 1998 static void mlx5_ib_disable_lb_mp(struct mlx5_core_dev *master, 1999 struct mlx5_core_dev *slave, 2000 struct mlx5_ib_lb_state *lb_state) 2001 { 2002 mlx5_nic_vport_update_local_lb(slave, false); 2003 mlx5_nic_vport_update_local_lb(master, false); 2004 2005 lb_state->force_enable = false; 2006 } 2007 2008 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 2009 { 2010 int err = 0; 2011 2012 if (dev->lb.force_enable) 2013 return 0; 2014 2015 mutex_lock(&dev->lb.mutex); 2016 if (td) 2017 dev->lb.user_td++; 2018 if (qp) 2019 dev->lb.qps++; 2020 2021 if (dev->lb.user_td == 2 || 2022 dev->lb.qps == 1) { 2023 if (!dev->lb.enabled) { 2024 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 2025 dev->lb.enabled = true; 2026 } 2027 } 2028 2029 mutex_unlock(&dev->lb.mutex); 2030 2031 return err; 2032 } 2033 2034 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 2035 { 2036 if (dev->lb.force_enable) 2037 return; 2038 2039 mutex_lock(&dev->lb.mutex); 2040 if (td) 2041 dev->lb.user_td--; 2042 if (qp) 2043 dev->lb.qps--; 2044 2045 if (dev->lb.user_td == 1 && 2046 dev->lb.qps == 0) { 2047 if (dev->lb.enabled) { 2048 mlx5_nic_vport_update_local_lb(dev->mdev, false); 2049 dev->lb.enabled = false; 2050 } 2051 } 2052 2053 mutex_unlock(&dev->lb.mutex); 2054 } 2055 2056 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 2057 u16 uid) 2058 { 2059 int err; 2060 2061 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 2062 return 0; 2063 2064 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 2065 if (err) 2066 return err; 2067 2068 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 2069 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 2070 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 2071 return err; 2072 2073 return mlx5_ib_enable_lb(dev, true, false); 2074 } 2075 2076 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 2077 u16 uid) 2078 { 2079 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 2080 return; 2081 2082 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 2083 2084 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 2085 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 2086 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 2087 return; 2088 2089 mlx5_ib_disable_lb(dev, true, false); 2090 } 2091 2092 static int set_ucontext_resp(struct ib_ucontext *uctx, 2093 struct mlx5_ib_alloc_ucontext_resp *resp) 2094 { 2095 struct ib_device *ibdev = uctx->device; 2096 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2097 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 2098 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2099 2100 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 2101 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 2102 resp->comp_mask |= 2103 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 2104 } 2105 2106 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 2107 if (mlx5_wc_support_get(dev->mdev)) 2108 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 2109 log_bf_reg_size); 2110 resp->cache_line_size = cache_line_size(); 2111 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 2112 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 2113 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 2114 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 2115 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 2116 resp->cqe_version = context->cqe_version; 2117 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2118 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 2119 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2120 MLX5_CAP_GEN(dev->mdev, 2121 num_of_uars_per_page) : 1; 2122 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 2123 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 2124 resp->num_ports = dev->num_ports; 2125 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 2126 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 2127 2128 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 2129 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 2130 resp->eth_min_inline++; 2131 } 2132 2133 if (dev->mdev->clock_info) 2134 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 2135 2136 /* 2137 * We don't want to expose information from the PCI bar that is located 2138 * after 4096 bytes, so if the arch only supports larger pages, let's 2139 * pretend we don't support reading the HCA's core clock. This is also 2140 * forced by mmap function. 2141 */ 2142 if (PAGE_SIZE <= 4096) { 2143 resp->comp_mask |= 2144 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 2145 resp->hca_core_clock_offset = 2146 offsetof(struct mlx5_init_seg, 2147 internal_timer_h) % PAGE_SIZE; 2148 } 2149 2150 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 2151 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 2152 2153 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 2154 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 2155 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 2156 resp->comp_mask |= 2157 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 2158 2159 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 2160 2161 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 2162 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 2163 2164 resp->comp_mask |= 2165 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 2166 2167 return 0; 2168 } 2169 2170 static bool uctx_rdma_ctrl_is_enabled(u64 enabled_caps) 2171 { 2172 return UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_LOCAL) || 2173 UCAP_ENABLED(enabled_caps, RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 2174 } 2175 2176 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 2177 struct ib_udata *udata) 2178 { 2179 struct ib_device *ibdev = uctx->device; 2180 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2181 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 2182 struct mlx5_ib_alloc_ucontext_resp resp = {}; 2183 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 2184 struct mlx5_bfreg_info *bfregi; 2185 int ver; 2186 int err; 2187 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 2188 max_cqe_version); 2189 bool lib_uar_4k; 2190 bool lib_uar_dyn; 2191 2192 if (!dev->ib_active) 2193 return -EAGAIN; 2194 2195 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 2196 ver = 0; 2197 else if (udata->inlen >= min_req_v2) 2198 ver = 2; 2199 else 2200 return -EINVAL; 2201 2202 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 2203 if (err) 2204 return err; 2205 2206 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 2207 return -EOPNOTSUPP; 2208 2209 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 2210 return -EOPNOTSUPP; 2211 2212 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 2213 MLX5_NON_FP_BFREGS_PER_UAR); 2214 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 2215 return -EINVAL; 2216 2217 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 2218 err = mlx5_ib_devx_create(dev, true, uctx->enabled_caps); 2219 if (err < 0) 2220 goto out_ctx; 2221 context->devx_uid = err; 2222 2223 if (uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) { 2224 err = mlx5_cmd_add_privileged_uid(dev->mdev, 2225 context->devx_uid); 2226 if (err) 2227 goto out_devx; 2228 } 2229 } 2230 2231 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 2232 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 2233 bfregi = &context->bfregi; 2234 2235 if (lib_uar_dyn) { 2236 bfregi->lib_uar_dyn = lib_uar_dyn; 2237 goto uar_done; 2238 } 2239 2240 /* updates req->total_num_bfregs */ 2241 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 2242 if (err) 2243 goto out_ucap; 2244 2245 mutex_init(&bfregi->lock); 2246 bfregi->lib_uar_4k = lib_uar_4k; 2247 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 2248 GFP_KERNEL); 2249 if (!bfregi->count) { 2250 err = -ENOMEM; 2251 goto out_ucap; 2252 } 2253 2254 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 2255 sizeof(*bfregi->sys_pages), 2256 GFP_KERNEL); 2257 if (!bfregi->sys_pages) { 2258 err = -ENOMEM; 2259 goto out_count; 2260 } 2261 2262 err = allocate_uars(dev, context); 2263 if (err) 2264 goto out_sys_pages; 2265 2266 uar_done: 2267 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 2268 context->devx_uid); 2269 if (err) 2270 goto out_uars; 2271 2272 INIT_LIST_HEAD(&context->db_page_list); 2273 mutex_init(&context->db_page_mutex); 2274 2275 context->cqe_version = min_t(__u8, 2276 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 2277 req.max_cqe_version); 2278 2279 err = set_ucontext_resp(uctx, &resp); 2280 if (err) 2281 goto out_mdev; 2282 2283 resp.response_length = min(udata->outlen, sizeof(resp)); 2284 err = ib_copy_to_udata(udata, &resp, resp.response_length); 2285 if (err) 2286 goto out_mdev; 2287 2288 bfregi->ver = ver; 2289 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 2290 context->lib_caps = req.lib_caps; 2291 print_lib_caps(dev, context->lib_caps); 2292 2293 if (mlx5_ib_lag_should_assign_affinity(dev)) { 2294 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 2295 2296 atomic_set(&context->tx_port_affinity, 2297 atomic_add_return( 2298 1, &dev->port[port].roce.tx_port_affinity)); 2299 } 2300 2301 return 0; 2302 2303 out_mdev: 2304 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2305 2306 out_uars: 2307 deallocate_uars(dev, context); 2308 2309 out_sys_pages: 2310 kfree(bfregi->sys_pages); 2311 2312 out_count: 2313 kfree(bfregi->count); 2314 2315 out_ucap: 2316 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX && 2317 uctx_rdma_ctrl_is_enabled(uctx->enabled_caps)) 2318 mlx5_cmd_remove_privileged_uid(dev->mdev, context->devx_uid); 2319 2320 out_devx: 2321 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 2322 mlx5_ib_devx_destroy(dev, context->devx_uid); 2323 2324 out_ctx: 2325 return err; 2326 } 2327 2328 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 2329 struct uverbs_attr_bundle *attrs) 2330 { 2331 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 2332 int ret; 2333 2334 ret = set_ucontext_resp(ibcontext, &uctx_resp); 2335 if (ret) 2336 return ret; 2337 2338 uctx_resp.response_length = 2339 min_t(size_t, 2340 uverbs_attr_get_len(attrs, 2341 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2342 sizeof(uctx_resp)); 2343 2344 ret = uverbs_copy_to_struct_or_zero(attrs, 2345 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2346 &uctx_resp, 2347 sizeof(uctx_resp)); 2348 return ret; 2349 } 2350 2351 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2352 { 2353 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2354 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2355 struct mlx5_bfreg_info *bfregi; 2356 2357 bfregi = &context->bfregi; 2358 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2359 2360 deallocate_uars(dev, context); 2361 kfree(bfregi->sys_pages); 2362 kfree(bfregi->count); 2363 2364 if (context->devx_uid) { 2365 if (uctx_rdma_ctrl_is_enabled(ibcontext->enabled_caps)) 2366 mlx5_cmd_remove_privileged_uid(dev->mdev, 2367 context->devx_uid); 2368 mlx5_ib_devx_destroy(dev, context->devx_uid); 2369 } 2370 } 2371 2372 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2373 int uar_idx) 2374 { 2375 int fw_uars_per_page; 2376 2377 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2378 2379 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2380 } 2381 2382 static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2383 int uar_idx) 2384 { 2385 unsigned int fw_uars_per_page; 2386 2387 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2388 MLX5_UARS_IN_PAGE : 1; 2389 2390 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2391 } 2392 2393 static int get_command(unsigned long offset) 2394 { 2395 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2396 } 2397 2398 static int get_arg(unsigned long offset) 2399 { 2400 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2401 } 2402 2403 static int get_index(unsigned long offset) 2404 { 2405 return get_arg(offset); 2406 } 2407 2408 /* Index resides in an extra byte to enable larger values than 255 */ 2409 static int get_extended_index(unsigned long offset) 2410 { 2411 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2412 } 2413 2414 2415 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2416 { 2417 } 2418 2419 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2420 { 2421 switch (cmd) { 2422 case MLX5_IB_MMAP_WC_PAGE: 2423 return "WC"; 2424 case MLX5_IB_MMAP_REGULAR_PAGE: 2425 return "best effort WC"; 2426 case MLX5_IB_MMAP_NC_PAGE: 2427 return "NC"; 2428 case MLX5_IB_MMAP_DEVICE_MEM: 2429 return "Device Memory"; 2430 default: 2431 return "Unknown"; 2432 } 2433 } 2434 2435 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2436 struct vm_area_struct *vma, 2437 struct mlx5_ib_ucontext *context) 2438 { 2439 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2440 !(vma->vm_flags & VM_SHARED)) 2441 return -EINVAL; 2442 2443 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2444 return -EOPNOTSUPP; 2445 2446 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2447 return -EPERM; 2448 vm_flags_clear(vma, VM_MAYWRITE); 2449 2450 if (!dev->mdev->clock_info) 2451 return -EOPNOTSUPP; 2452 2453 return vm_insert_page(vma, vma->vm_start, 2454 virt_to_page(dev->mdev->clock_info)); 2455 } 2456 2457 static int phys_addr_to_bar(struct pci_dev *pdev, phys_addr_t pa) 2458 { 2459 resource_size_t start, end; 2460 int bar; 2461 2462 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { 2463 /* Skip BARs not present or not memory-mapped */ 2464 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) 2465 continue; 2466 2467 start = pci_resource_start(pdev, bar); 2468 end = pci_resource_end(pdev, bar); 2469 2470 if (!start || !end) 2471 continue; 2472 2473 if (pa >= start && pa <= end) 2474 return bar; 2475 } 2476 2477 return -1; 2478 } 2479 2480 static int mlx5_ib_mmap_get_pfns(struct rdma_user_mmap_entry *entry, 2481 struct phys_vec *phys_vec, 2482 struct p2pdma_provider **provider) 2483 { 2484 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2485 struct pci_dev *pdev = to_mdev(entry->ucontext->device)->mdev->pdev; 2486 int bar; 2487 2488 phys_vec->paddr = mentry->address; 2489 phys_vec->len = entry->npages * PAGE_SIZE; 2490 2491 bar = phys_addr_to_bar(pdev, phys_vec->paddr); 2492 if (bar < 0) 2493 return -EINVAL; 2494 2495 *provider = pcim_p2pdma_provider(pdev, bar); 2496 /* If the kernel was not compiled with CONFIG_PCI_P2PDMA the 2497 * functionality is not supported. 2498 */ 2499 if (!*provider) 2500 return -EOPNOTSUPP; 2501 2502 return 0; 2503 } 2504 2505 static struct rdma_user_mmap_entry * 2506 mlx5_ib_pgoff_to_mmap_entry(struct ib_ucontext *ucontext, off_t pg_off) 2507 { 2508 unsigned long entry_pgoff; 2509 unsigned long idx; 2510 u8 command; 2511 2512 pg_off = pg_off >> PAGE_SHIFT; 2513 command = get_command(pg_off); 2514 idx = get_extended_index(pg_off); 2515 2516 entry_pgoff = command << 16 | idx; 2517 2518 return rdma_user_mmap_entry_get_pgoff(ucontext, entry_pgoff); 2519 } 2520 2521 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2522 { 2523 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2524 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2525 struct mlx5_var_table *var_table = &dev->var_table; 2526 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2527 2528 switch (mentry->mmap_flag) { 2529 case MLX5_IB_MMAP_TYPE_MEMIC: 2530 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2531 mlx5_ib_dm_mmap_free(dev, mentry); 2532 break; 2533 case MLX5_IB_MMAP_TYPE_VAR: 2534 mutex_lock(&var_table->bitmap_lock); 2535 clear_bit(mentry->page_idx, var_table->bitmap); 2536 mutex_unlock(&var_table->bitmap_lock); 2537 kfree(mentry); 2538 break; 2539 case MLX5_IB_MMAP_TYPE_UAR_WC: 2540 case MLX5_IB_MMAP_TYPE_UAR_NC: 2541 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2542 context->devx_uid); 2543 kfree(mentry); 2544 break; 2545 default: 2546 WARN_ON(true); 2547 } 2548 } 2549 2550 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2551 struct vm_area_struct *vma, 2552 struct mlx5_ib_ucontext *context) 2553 { 2554 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2555 int err; 2556 unsigned long idx; 2557 phys_addr_t pfn; 2558 pgprot_t prot; 2559 u32 bfreg_dyn_idx = 0; 2560 u32 uar_index; 2561 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2562 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2563 bfregi->num_static_sys_pages; 2564 2565 if (bfregi->lib_uar_dyn) 2566 return -EINVAL; 2567 2568 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2569 return -EINVAL; 2570 2571 if (dyn_uar) 2572 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2573 else 2574 idx = get_index(vma->vm_pgoff); 2575 2576 if (idx >= max_valid_idx) { 2577 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2578 idx, max_valid_idx); 2579 return -EINVAL; 2580 } 2581 2582 switch (cmd) { 2583 case MLX5_IB_MMAP_WC_PAGE: 2584 case MLX5_IB_MMAP_ALLOC_WC: 2585 case MLX5_IB_MMAP_REGULAR_PAGE: 2586 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2587 prot = pgprot_writecombine(vma->vm_page_prot); 2588 break; 2589 case MLX5_IB_MMAP_NC_PAGE: 2590 prot = pgprot_noncached(vma->vm_page_prot); 2591 break; 2592 default: 2593 return -EINVAL; 2594 } 2595 2596 if (dyn_uar) { 2597 int uars_per_page; 2598 2599 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2600 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2601 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2602 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2603 bfreg_dyn_idx, bfregi->total_num_bfregs); 2604 return -EINVAL; 2605 } 2606 2607 mutex_lock(&bfregi->lock); 2608 /* Fail if uar already allocated, first bfreg index of each 2609 * page holds its count. 2610 */ 2611 if (bfregi->count[bfreg_dyn_idx]) { 2612 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2613 mutex_unlock(&bfregi->lock); 2614 return -EINVAL; 2615 } 2616 2617 bfregi->count[bfreg_dyn_idx]++; 2618 mutex_unlock(&bfregi->lock); 2619 2620 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2621 context->devx_uid); 2622 if (err) { 2623 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2624 goto free_bfreg; 2625 } 2626 } else { 2627 uar_index = bfregi->sys_pages[idx]; 2628 } 2629 2630 pfn = uar_index2pfn(dev, uar_index); 2631 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2632 2633 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2634 prot, NULL); 2635 if (err) { 2636 mlx5_ib_err(dev, 2637 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2638 err, mmap_cmd2str(cmd)); 2639 goto err; 2640 } 2641 2642 if (dyn_uar) 2643 bfregi->sys_pages[idx] = uar_index; 2644 return 0; 2645 2646 err: 2647 if (!dyn_uar) 2648 return err; 2649 2650 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2651 2652 free_bfreg: 2653 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2654 2655 return err; 2656 } 2657 2658 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2659 { 2660 unsigned long idx; 2661 u8 command; 2662 2663 command = get_command(vma->vm_pgoff); 2664 idx = get_extended_index(vma->vm_pgoff); 2665 2666 return (command << 16 | idx); 2667 } 2668 2669 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2670 struct vm_area_struct *vma, 2671 struct ib_ucontext *ucontext) 2672 { 2673 struct mlx5_user_mmap_entry *mentry; 2674 struct rdma_user_mmap_entry *entry; 2675 unsigned long pgoff; 2676 pgprot_t prot; 2677 phys_addr_t pfn; 2678 int ret; 2679 2680 pgoff = mlx5_vma_to_pgoff(vma); 2681 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2682 if (!entry) 2683 return -EINVAL; 2684 2685 mentry = to_mmmap(entry); 2686 pfn = (mentry->address >> PAGE_SHIFT); 2687 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2688 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2689 prot = pgprot_noncached(vma->vm_page_prot); 2690 else 2691 prot = pgprot_writecombine(vma->vm_page_prot); 2692 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2693 entry->npages * PAGE_SIZE, 2694 prot, 2695 entry); 2696 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2697 return ret; 2698 } 2699 2700 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2701 { 2702 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2703 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2704 2705 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2706 (index & 0xFF)) << PAGE_SHIFT; 2707 } 2708 2709 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2710 { 2711 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2712 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2713 unsigned long command; 2714 phys_addr_t pfn; 2715 2716 command = get_command(vma->vm_pgoff); 2717 switch (command) { 2718 case MLX5_IB_MMAP_WC_PAGE: 2719 case MLX5_IB_MMAP_ALLOC_WC: 2720 if (!mlx5_wc_support_get(dev->mdev)) 2721 return -EPERM; 2722 fallthrough; 2723 case MLX5_IB_MMAP_NC_PAGE: 2724 case MLX5_IB_MMAP_REGULAR_PAGE: 2725 return uar_mmap(dev, command, vma, context); 2726 2727 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2728 return -ENOSYS; 2729 2730 case MLX5_IB_MMAP_CORE_CLOCK: 2731 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2732 return -EINVAL; 2733 2734 if (vma->vm_flags & VM_WRITE) 2735 return -EPERM; 2736 vm_flags_clear(vma, VM_MAYWRITE); 2737 2738 /* Don't expose to user-space information it shouldn't have */ 2739 if (PAGE_SIZE > 4096) 2740 return -EOPNOTSUPP; 2741 2742 pfn = (dev->mdev->iseg_base + 2743 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2744 PAGE_SHIFT; 2745 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2746 PAGE_SIZE, 2747 pgprot_noncached(vma->vm_page_prot), 2748 NULL); 2749 case MLX5_IB_MMAP_CLOCK_INFO: 2750 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2751 2752 default: 2753 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2754 } 2755 2756 return 0; 2757 } 2758 2759 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2760 { 2761 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2762 struct ib_device *ibdev = ibpd->device; 2763 struct mlx5_ib_alloc_pd_resp resp; 2764 int err; 2765 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2766 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2767 u16 uid = 0; 2768 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2769 udata, struct mlx5_ib_ucontext, ibucontext); 2770 2771 uid = context ? context->devx_uid : 0; 2772 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2773 MLX5_SET(alloc_pd_in, in, uid, uid); 2774 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2775 if (err) 2776 return err; 2777 2778 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2779 pd->uid = uid; 2780 if (udata) { 2781 resp.pdn = pd->pdn; 2782 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2783 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2784 return -EFAULT; 2785 } 2786 } 2787 2788 return 0; 2789 } 2790 2791 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2792 { 2793 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2794 struct mlx5_ib_pd *mpd = to_mpd(pd); 2795 2796 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2797 } 2798 2799 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2800 { 2801 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2802 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2803 int err; 2804 u16 uid; 2805 2806 uid = ibqp->pd ? 2807 to_mpd(ibqp->pd)->uid : 0; 2808 2809 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2810 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2811 return -EOPNOTSUPP; 2812 } 2813 2814 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2815 if (err) 2816 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2817 ibqp->qp_num, gid->raw); 2818 2819 return err; 2820 } 2821 2822 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2823 { 2824 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2825 int err; 2826 u16 uid; 2827 2828 uid = ibqp->pd ? 2829 to_mpd(ibqp->pd)->uid : 0; 2830 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2831 if (err) 2832 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2833 ibqp->qp_num, gid->raw); 2834 2835 return err; 2836 } 2837 2838 static int init_node_data(struct mlx5_ib_dev *dev) 2839 { 2840 int err; 2841 2842 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2843 if (err) 2844 return err; 2845 2846 dev->mdev->rev_id = dev->mdev->pdev->revision; 2847 2848 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2849 } 2850 2851 static ssize_t fw_pages_show(struct device *device, 2852 struct device_attribute *attr, char *buf) 2853 { 2854 struct mlx5_ib_dev *dev = 2855 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2856 2857 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2858 } 2859 static DEVICE_ATTR_RO(fw_pages); 2860 2861 static ssize_t reg_pages_show(struct device *device, 2862 struct device_attribute *attr, char *buf) 2863 { 2864 struct mlx5_ib_dev *dev = 2865 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2866 2867 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2868 } 2869 static DEVICE_ATTR_RO(reg_pages); 2870 2871 static ssize_t hca_type_show(struct device *device, 2872 struct device_attribute *attr, char *buf) 2873 { 2874 struct mlx5_ib_dev *dev = 2875 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2876 2877 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2878 } 2879 static DEVICE_ATTR_RO(hca_type); 2880 2881 static ssize_t hw_rev_show(struct device *device, 2882 struct device_attribute *attr, char *buf) 2883 { 2884 struct mlx5_ib_dev *dev = 2885 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2886 2887 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2888 } 2889 static DEVICE_ATTR_RO(hw_rev); 2890 2891 static ssize_t board_id_show(struct device *device, 2892 struct device_attribute *attr, char *buf) 2893 { 2894 struct mlx5_ib_dev *dev = 2895 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2896 2897 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2898 dev->mdev->board_id); 2899 } 2900 static DEVICE_ATTR_RO(board_id); 2901 2902 static struct attribute *mlx5_class_attributes[] = { 2903 &dev_attr_hw_rev.attr, 2904 &dev_attr_hca_type.attr, 2905 &dev_attr_board_id.attr, 2906 &dev_attr_fw_pages.attr, 2907 &dev_attr_reg_pages.attr, 2908 NULL, 2909 }; 2910 2911 static const struct attribute_group mlx5_attr_group = { 2912 .attrs = mlx5_class_attributes, 2913 }; 2914 2915 static void pkey_change_handler(struct work_struct *work) 2916 { 2917 struct mlx5_ib_port_resources *ports = 2918 container_of(work, struct mlx5_ib_port_resources, 2919 pkey_change_work); 2920 2921 if (!ports->gsi) 2922 /* 2923 * We got this event before device was fully configured 2924 * and MAD registration code wasn't called/finished yet. 2925 */ 2926 return; 2927 2928 mlx5_ib_gsi_pkey_change(ports->gsi); 2929 } 2930 2931 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2932 { 2933 struct mlx5_ib_qp *mqp; 2934 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2935 struct mlx5_core_cq *mcq; 2936 struct list_head cq_armed_list; 2937 unsigned long flags_qp; 2938 unsigned long flags_cq; 2939 unsigned long flags; 2940 2941 INIT_LIST_HEAD(&cq_armed_list); 2942 2943 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2944 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2945 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2946 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2947 if (mqp->sq.tail != mqp->sq.head) { 2948 send_mcq = to_mcq(mqp->ibqp.send_cq); 2949 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2950 if (send_mcq->mcq.comp && 2951 mqp->ibqp.send_cq->comp_handler) { 2952 if (!send_mcq->mcq.reset_notify_added) { 2953 send_mcq->mcq.reset_notify_added = 1; 2954 list_add_tail(&send_mcq->mcq.reset_notify, 2955 &cq_armed_list); 2956 } 2957 } 2958 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2959 } 2960 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2961 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2962 /* no handling is needed for SRQ */ 2963 if (!mqp->ibqp.srq) { 2964 if (mqp->rq.tail != mqp->rq.head) { 2965 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2966 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2967 if (recv_mcq->mcq.comp && 2968 mqp->ibqp.recv_cq->comp_handler) { 2969 if (!recv_mcq->mcq.reset_notify_added) { 2970 recv_mcq->mcq.reset_notify_added = 1; 2971 list_add_tail(&recv_mcq->mcq.reset_notify, 2972 &cq_armed_list); 2973 } 2974 } 2975 spin_unlock_irqrestore(&recv_mcq->lock, 2976 flags_cq); 2977 } 2978 } 2979 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2980 } 2981 /*At that point all inflight post send were put to be executed as of we 2982 * lock/unlock above locks Now need to arm all involved CQs. 2983 */ 2984 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2985 mcq->comp(mcq, NULL); 2986 } 2987 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2988 } 2989 2990 static void delay_drop_handler(struct work_struct *work) 2991 { 2992 int err; 2993 struct mlx5_ib_delay_drop *delay_drop = 2994 container_of(work, struct mlx5_ib_delay_drop, 2995 delay_drop_work); 2996 2997 atomic_inc(&delay_drop->events_cnt); 2998 2999 mutex_lock(&delay_drop->lock); 3000 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 3001 if (err) { 3002 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 3003 delay_drop->timeout); 3004 delay_drop->activate = false; 3005 } 3006 mutex_unlock(&delay_drop->lock); 3007 } 3008 3009 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 3010 struct ib_event *ibev) 3011 { 3012 u32 port = (eqe->data.port.port >> 4) & 0xf; 3013 3014 switch (eqe->sub_type) { 3015 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 3016 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 3017 IB_LINK_LAYER_ETHERNET) 3018 schedule_work(&ibdev->delay_drop.delay_drop_work); 3019 break; 3020 default: /* do nothing */ 3021 return; 3022 } 3023 } 3024 3025 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 3026 struct ib_event *ibev) 3027 { 3028 u32 port = (eqe->data.port.port >> 4) & 0xf; 3029 3030 ibev->element.port_num = port; 3031 3032 switch (eqe->sub_type) { 3033 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 3034 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 3035 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 3036 if (ibdev->ib_active) { 3037 struct ib_event speed_event = {}; 3038 3039 speed_event.device = &ibdev->ib_dev; 3040 speed_event.event = IB_EVENT_DEVICE_SPEED_CHANGE; 3041 ib_dispatch_event(&speed_event); 3042 } 3043 3044 /* In RoCE, port up/down events are handled in 3045 * mlx5_netdev_event(). 3046 */ 3047 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 3048 IB_LINK_LAYER_ETHERNET) 3049 return -EINVAL; 3050 3051 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 3052 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 3053 break; 3054 3055 case MLX5_PORT_CHANGE_SUBTYPE_LID: 3056 ibev->event = IB_EVENT_LID_CHANGE; 3057 break; 3058 3059 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 3060 ibev->event = IB_EVENT_PKEY_CHANGE; 3061 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 3062 break; 3063 3064 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 3065 ibev->event = IB_EVENT_GID_CHANGE; 3066 break; 3067 3068 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 3069 ibev->event = IB_EVENT_CLIENT_REREGISTER; 3070 break; 3071 default: 3072 return -EINVAL; 3073 } 3074 3075 return 0; 3076 } 3077 3078 static void mlx5_ib_handle_event(struct work_struct *_work) 3079 { 3080 struct mlx5_ib_event_work *work = 3081 container_of(_work, struct mlx5_ib_event_work, work); 3082 struct mlx5_ib_dev *ibdev; 3083 struct ib_event ibev; 3084 3085 if (work->is_slave) { 3086 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 3087 if (!ibdev) 3088 goto out; 3089 } else { 3090 ibdev = work->dev; 3091 } 3092 3093 switch (work->event) { 3094 case MLX5_EVENT_TYPE_PORT_CHANGE: 3095 if (handle_port_change(ibdev, work->param, &ibev)) 3096 goto out; 3097 break; 3098 case MLX5_EVENT_TYPE_GENERAL_EVENT: 3099 handle_general_event(ibdev, work->param, &ibev); 3100 fallthrough; 3101 default: 3102 goto out; 3103 } 3104 3105 ibev.device = &ibdev->ib_dev; 3106 3107 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 3108 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 3109 goto out; 3110 } 3111 3112 if (ibdev->ib_active) 3113 ib_dispatch_event(&ibev); 3114 3115 out: 3116 kfree(work); 3117 } 3118 3119 static int mlx5_ib_event(struct notifier_block *nb, 3120 unsigned long event, void *param) 3121 { 3122 struct mlx5_ib_event_work *work; 3123 3124 work = kmalloc(sizeof(*work), GFP_ATOMIC); 3125 if (!work) 3126 return NOTIFY_DONE; 3127 3128 INIT_WORK(&work->work, mlx5_ib_handle_event); 3129 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 3130 work->is_slave = false; 3131 work->param = param; 3132 work->event = event; 3133 3134 queue_work(mlx5_ib_event_wq, &work->work); 3135 3136 return NOTIFY_OK; 3137 } 3138 3139 static int mlx5_ib_event_slave_port(struct notifier_block *nb, 3140 unsigned long event, void *param) 3141 { 3142 struct mlx5_ib_event_work *work; 3143 3144 work = kmalloc(sizeof(*work), GFP_ATOMIC); 3145 if (!work) 3146 return NOTIFY_DONE; 3147 3148 INIT_WORK(&work->work, mlx5_ib_handle_event); 3149 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 3150 work->is_slave = true; 3151 work->param = param; 3152 work->event = event; 3153 queue_work(mlx5_ib_event_wq, &work->work); 3154 3155 return NOTIFY_OK; 3156 } 3157 3158 static void mlx5_ib_handle_sys_error_event(struct work_struct *_work) 3159 { 3160 struct mlx5_ib_event_work *work = 3161 container_of(_work, struct mlx5_ib_event_work, work); 3162 struct mlx5_ib_dev *ibdev = work->dev; 3163 struct ib_event ibev; 3164 3165 ibev.event = IB_EVENT_DEVICE_FATAL; 3166 mlx5_ib_handle_internal_error(ibdev); 3167 ibev.element.port_num = (u8)(unsigned long)work->param; 3168 ibev.device = &ibdev->ib_dev; 3169 3170 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 3171 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 3172 goto out; 3173 } 3174 3175 if (ibdev->ib_active) 3176 ib_dispatch_event(&ibev); 3177 3178 ibdev->ib_active = false; 3179 out: 3180 kfree(work); 3181 } 3182 3183 static int mlx5_ib_sys_error_event(struct notifier_block *nb, 3184 unsigned long event, void *param) 3185 { 3186 struct mlx5_ib_event_work *work; 3187 3188 if (event != MLX5_DEV_EVENT_SYS_ERROR) 3189 return NOTIFY_DONE; 3190 3191 work = kmalloc(sizeof(*work), GFP_ATOMIC); 3192 if (!work) 3193 return NOTIFY_DONE; 3194 3195 INIT_WORK(&work->work, mlx5_ib_handle_sys_error_event); 3196 work->dev = container_of(nb, struct mlx5_ib_dev, sys_error_events); 3197 work->is_slave = false; 3198 work->param = param; 3199 work->event = event; 3200 3201 queue_work(mlx5_ib_event_wq, &work->work); 3202 3203 return NOTIFY_OK; 3204 } 3205 3206 static int mlx5_ib_stage_sys_error_notifier_init(struct mlx5_ib_dev *dev) 3207 { 3208 dev->sys_error_events.notifier_call = mlx5_ib_sys_error_event; 3209 mlx5_notifier_register(dev->mdev, &dev->sys_error_events); 3210 return 0; 3211 } 3212 3213 static void mlx5_ib_stage_sys_error_notifier_cleanup(struct mlx5_ib_dev *dev) 3214 { 3215 mlx5_notifier_unregister(dev->mdev, &dev->sys_error_events); 3216 } 3217 3218 static int mlx5_ib_get_plane_num(struct mlx5_core_dev *mdev, u8 *num_plane) 3219 { 3220 struct mlx5_hca_vport_context vport_ctx; 3221 int err; 3222 3223 *num_plane = 0; 3224 if (!MLX5_CAP_GEN(mdev, ib_virt) || !MLX5_CAP_GEN_2(mdev, multiplane)) 3225 return 0; 3226 3227 err = mlx5_query_hca_vport_context(mdev, 0, 1, 0, &vport_ctx); 3228 if (err) 3229 return err; 3230 3231 *num_plane = vport_ctx.num_plane; 3232 return 0; 3233 } 3234 3235 static int set_has_smi_cap(struct mlx5_ib_dev *dev) 3236 { 3237 struct mlx5_hca_vport_context vport_ctx; 3238 int err; 3239 int port; 3240 3241 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 3242 return 0; 3243 3244 for (port = 1; port <= dev->num_ports; port++) { 3245 if (dev->num_plane) { 3246 dev->port_caps[port - 1].has_smi = false; 3247 continue; 3248 } else if (!MLX5_CAP_GEN(dev->mdev, ib_virt) || 3249 dev->ib_dev.type == RDMA_DEVICE_TYPE_SMI) { 3250 dev->port_caps[port - 1].has_smi = true; 3251 continue; 3252 } 3253 3254 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 3255 &vport_ctx); 3256 if (err) { 3257 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 3258 port, err); 3259 return err; 3260 } 3261 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 3262 } 3263 3264 return 0; 3265 } 3266 3267 static void get_ext_port_caps(struct mlx5_ib_dev *dev) 3268 { 3269 unsigned int port; 3270 3271 rdma_for_each_port (&dev->ib_dev, port) 3272 mlx5_query_ext_port_caps(dev, port); 3273 } 3274 3275 static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 3276 { 3277 switch (umr_fence_cap) { 3278 case MLX5_CAP_UMR_FENCE_NONE: 3279 return MLX5_FENCE_MODE_NONE; 3280 case MLX5_CAP_UMR_FENCE_SMALL: 3281 return MLX5_FENCE_MODE_INITIATOR_SMALL; 3282 default: 3283 return MLX5_FENCE_MODE_STRONG_ORDERING; 3284 } 3285 } 3286 3287 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev) 3288 { 3289 struct mlx5_ib_resources *devr = &dev->devr; 3290 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 3291 struct ib_device *ibdev; 3292 struct ib_pd *pd; 3293 struct ib_cq *cq; 3294 int ret = 0; 3295 3296 3297 /* 3298 * devr->c0 is set once, never changed until device unload. 3299 * Avoid taking the mutex if initialization is already done. 3300 */ 3301 if (devr->c0) 3302 return 0; 3303 3304 mutex_lock(&devr->cq_lock); 3305 if (devr->c0) 3306 goto unlock; 3307 3308 ibdev = &dev->ib_dev; 3309 pd = ib_alloc_pd(ibdev, 0); 3310 if (IS_ERR(pd)) { 3311 ret = PTR_ERR(pd); 3312 mlx5_ib_err(dev, "Couldn't allocate PD for res init, err=%pe\n", 3313 pd); 3314 goto unlock; 3315 } 3316 3317 cq = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 3318 if (IS_ERR(cq)) { 3319 ret = PTR_ERR(cq); 3320 mlx5_ib_err(dev, "Couldn't create CQ for res init, err=%pe\n", 3321 cq); 3322 ib_dealloc_pd(pd); 3323 goto unlock; 3324 } 3325 3326 devr->p0 = pd; 3327 devr->c0 = cq; 3328 3329 unlock: 3330 mutex_unlock(&devr->cq_lock); 3331 return ret; 3332 } 3333 3334 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev) 3335 { 3336 struct mlx5_ib_resources *devr = &dev->devr; 3337 struct ib_srq_init_attr attr; 3338 struct ib_srq *s0, *s1; 3339 int ret = 0; 3340 3341 /* 3342 * devr->s1 is set once, never changed until device unload. 3343 * Avoid taking the mutex if initialization is already done. 3344 */ 3345 if (devr->s1) 3346 return 0; 3347 3348 mutex_lock(&devr->srq_lock); 3349 if (devr->s1) 3350 goto unlock; 3351 3352 ret = mlx5_ib_dev_res_cq_init(dev); 3353 if (ret) 3354 goto unlock; 3355 3356 memset(&attr, 0, sizeof(attr)); 3357 attr.attr.max_sge = 1; 3358 attr.attr.max_wr = 1; 3359 attr.srq_type = IB_SRQT_XRC; 3360 attr.ext.cq = devr->c0; 3361 3362 s0 = ib_create_srq(devr->p0, &attr); 3363 if (IS_ERR(s0)) { 3364 ret = PTR_ERR(s0); 3365 mlx5_ib_err(dev, 3366 "Couldn't create SRQ 0 for res init, err=%pe\n", 3367 s0); 3368 goto unlock; 3369 } 3370 3371 memset(&attr, 0, sizeof(attr)); 3372 attr.attr.max_sge = 1; 3373 attr.attr.max_wr = 1; 3374 attr.srq_type = IB_SRQT_BASIC; 3375 3376 s1 = ib_create_srq(devr->p0, &attr); 3377 if (IS_ERR(s1)) { 3378 ret = PTR_ERR(s1); 3379 mlx5_ib_err(dev, 3380 "Couldn't create SRQ 1 for res init, err=%pe\n", 3381 s1); 3382 ib_destroy_srq(s0); 3383 } 3384 3385 devr->s0 = s0; 3386 devr->s1 = s1; 3387 3388 unlock: 3389 mutex_unlock(&devr->srq_lock); 3390 return ret; 3391 } 3392 3393 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 3394 { 3395 struct mlx5_ib_resources *devr = &dev->devr; 3396 int ret; 3397 3398 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 3399 return -EOPNOTSUPP; 3400 3401 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 3402 if (ret) 3403 return ret; 3404 3405 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 3406 if (ret) { 3407 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3408 return ret; 3409 } 3410 3411 mutex_init(&devr->cq_lock); 3412 mutex_init(&devr->srq_lock); 3413 3414 return 0; 3415 } 3416 3417 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 3418 { 3419 struct mlx5_ib_resources *devr = &dev->devr; 3420 3421 /* After s0/s1 init, they are not unset during the device lifetime. */ 3422 if (devr->s1) { 3423 ib_destroy_srq(devr->s1); 3424 ib_destroy_srq(devr->s0); 3425 } 3426 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 3427 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 3428 /* After p0/c0 init, they are not unset during the device lifetime. */ 3429 if (devr->c0) { 3430 ib_destroy_cq(devr->c0); 3431 ib_dealloc_pd(devr->p0); 3432 } 3433 mutex_destroy(&devr->cq_lock); 3434 mutex_destroy(&devr->srq_lock); 3435 } 3436 3437 static int 3438 mlx5_ib_create_data_direct_resources(struct mlx5_ib_dev *dev) 3439 { 3440 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); 3441 struct mlx5_core_dev *mdev = dev->mdev; 3442 bool ro_supp = false; 3443 void *mkc; 3444 u32 mkey; 3445 u32 pdn; 3446 u32 *in; 3447 int err; 3448 3449 err = mlx5_core_alloc_pd(mdev, &pdn); 3450 if (err) 3451 return err; 3452 3453 in = kvzalloc(inlen, GFP_KERNEL); 3454 if (!in) { 3455 err = -ENOMEM; 3456 goto err; 3457 } 3458 3459 MLX5_SET(create_mkey_in, in, data_direct, 1); 3460 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); 3461 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA); 3462 MLX5_SET(mkc, mkc, lw, 1); 3463 MLX5_SET(mkc, mkc, lr, 1); 3464 MLX5_SET(mkc, mkc, rw, 1); 3465 MLX5_SET(mkc, mkc, rr, 1); 3466 MLX5_SET(mkc, mkc, a, 1); 3467 MLX5_SET(mkc, mkc, pd, pdn); 3468 MLX5_SET(mkc, mkc, length64, 1); 3469 MLX5_SET(mkc, mkc, qpn, 0xffffff); 3470 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3471 if (err) 3472 goto err_mkey; 3473 3474 dev->ddr.mkey = mkey; 3475 dev->ddr.pdn = pdn; 3476 3477 /* create another mkey with RO support */ 3478 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write)) { 3479 MLX5_SET(mkc, mkc, relaxed_ordering_write, 1); 3480 ro_supp = true; 3481 } 3482 3483 if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read)) { 3484 MLX5_SET(mkc, mkc, relaxed_ordering_read, 1); 3485 ro_supp = true; 3486 } 3487 3488 if (ro_supp) { 3489 err = mlx5_core_create_mkey(mdev, &mkey, in, inlen); 3490 /* RO is defined as best effort */ 3491 if (!err) { 3492 dev->ddr.mkey_ro = mkey; 3493 dev->ddr.mkey_ro_valid = true; 3494 } 3495 } 3496 3497 kvfree(in); 3498 return 0; 3499 3500 err_mkey: 3501 kvfree(in); 3502 err: 3503 mlx5_core_dealloc_pd(mdev, pdn); 3504 return err; 3505 } 3506 3507 static void 3508 mlx5_ib_free_data_direct_resources(struct mlx5_ib_dev *dev) 3509 { 3510 3511 if (dev->ddr.mkey_ro_valid) 3512 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey_ro); 3513 3514 mlx5_core_destroy_mkey(dev->mdev, dev->ddr.mkey); 3515 mlx5_core_dealloc_pd(dev->mdev, dev->ddr.pdn); 3516 } 3517 3518 static u32 get_core_cap_flags(struct ib_device *ibdev, 3519 struct mlx5_hca_vport_context *rep) 3520 { 3521 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3522 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 3523 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 3524 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 3525 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 3526 u32 ret = 0; 3527 3528 if (rep->grh_required) 3529 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 3530 3531 if (dev->num_plane) 3532 return ret | RDMA_CORE_CAP_PROT_IB | RDMA_CORE_CAP_IB_MAD | 3533 RDMA_CORE_CAP_IB_CM | RDMA_CORE_CAP_IB_SA | 3534 RDMA_CORE_CAP_AF_IB; 3535 else if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3536 return ret | RDMA_CORE_CAP_IB_MAD | RDMA_CORE_CAP_IB_SMI; 3537 3538 if (ll == IB_LINK_LAYER_INFINIBAND) 3539 return ret | RDMA_CORE_PORT_IBA_IB; 3540 3541 if (raw_support) 3542 ret |= RDMA_CORE_PORT_RAW_PACKET; 3543 3544 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 3545 return ret; 3546 3547 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 3548 return ret; 3549 3550 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 3551 ret |= RDMA_CORE_PORT_IBA_ROCE; 3552 3553 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 3554 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 3555 3556 return ret; 3557 } 3558 3559 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 3560 struct ib_port_immutable *immutable) 3561 { 3562 struct ib_port_attr attr; 3563 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3564 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 3565 struct mlx5_hca_vport_context rep = {0}; 3566 int err; 3567 3568 err = ib_query_port(ibdev, port_num, &attr); 3569 if (err) 3570 return err; 3571 3572 if (ll == IB_LINK_LAYER_INFINIBAND) { 3573 if (ibdev->type == RDMA_DEVICE_TYPE_SMI) 3574 port_num = smi_to_native_portnum(dev, port_num); 3575 3576 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 3577 &rep); 3578 if (err) 3579 return err; 3580 } 3581 3582 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3583 immutable->gid_tbl_len = attr.gid_tbl_len; 3584 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 3585 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 3586 3587 return 0; 3588 } 3589 3590 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 3591 struct ib_port_immutable *immutable) 3592 { 3593 struct ib_port_attr attr; 3594 int err; 3595 3596 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3597 3598 err = ib_query_port(ibdev, port_num, &attr); 3599 if (err) 3600 return err; 3601 3602 immutable->pkey_tbl_len = attr.pkey_tbl_len; 3603 immutable->gid_tbl_len = attr.gid_tbl_len; 3604 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 3605 3606 return 0; 3607 } 3608 3609 static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3610 { 3611 struct mlx5_ib_dev *dev = 3612 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3613 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3614 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3615 fw_rev_sub(dev->mdev)); 3616 } 3617 3618 static int lag_event(struct notifier_block *nb, unsigned long event, void *data) 3619 { 3620 struct mlx5_ib_dev *dev = container_of(nb, struct mlx5_ib_dev, 3621 lag_events); 3622 struct mlx5_core_dev *mdev = dev->mdev; 3623 struct ib_device *ibdev = &dev->ib_dev; 3624 struct net_device *old_ndev = NULL; 3625 struct mlx5_ib_port *port; 3626 struct net_device *ndev; 3627 u32 portnum = 0; 3628 int ret = 0; 3629 int i; 3630 3631 switch (event) { 3632 case MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE: 3633 ndev = data; 3634 if (ndev) { 3635 if (!mlx5_lag_is_roce(mdev)) { 3636 // sriov lag 3637 for (i = 0; i < dev->num_ports; i++) { 3638 port = &dev->port[i]; 3639 if (port->rep && port->rep->vport == 3640 MLX5_VPORT_UPLINK) { 3641 portnum = i; 3642 break; 3643 } 3644 } 3645 } 3646 old_ndev = ib_device_get_netdev(ibdev, portnum + 1); 3647 ret = ib_device_set_netdev(ibdev, ndev, portnum + 1); 3648 if (ret) 3649 goto out; 3650 3651 if (old_ndev) 3652 roce_del_all_netdev_gids(ibdev, portnum + 1, 3653 old_ndev); 3654 rdma_roce_rescan_port(ibdev, portnum + 1); 3655 } 3656 break; 3657 default: 3658 return NOTIFY_DONE; 3659 } 3660 3661 out: 3662 dev_put(old_ndev); 3663 return notifier_from_errno(ret); 3664 } 3665 3666 static void mlx5e_lag_event_register(struct mlx5_ib_dev *dev) 3667 { 3668 dev->lag_events.notifier_call = lag_event; 3669 blocking_notifier_chain_register(&dev->mdev->priv.lag_nh, 3670 &dev->lag_events); 3671 } 3672 3673 static void mlx5e_lag_event_unregister(struct mlx5_ib_dev *dev) 3674 { 3675 blocking_notifier_chain_unregister(&dev->mdev->priv.lag_nh, 3676 &dev->lag_events); 3677 } 3678 3679 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3680 { 3681 struct mlx5_core_dev *mdev = dev->mdev; 3682 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3683 MLX5_FLOW_NAMESPACE_LAG); 3684 struct mlx5_flow_table *ft; 3685 int err; 3686 3687 if (!ns || !mlx5_lag_is_active(mdev)) 3688 return 0; 3689 3690 err = mlx5_cmd_create_vport_lag(mdev); 3691 if (err) 3692 return err; 3693 3694 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3695 if (IS_ERR(ft)) { 3696 err = PTR_ERR(ft); 3697 goto err_destroy_vport_lag; 3698 } 3699 3700 mlx5e_lag_event_register(dev); 3701 dev->flow_db->lag_demux_ft = ft; 3702 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3703 dev->lag_active = true; 3704 return 0; 3705 3706 err_destroy_vport_lag: 3707 mlx5_cmd_destroy_vport_lag(mdev); 3708 return err; 3709 } 3710 3711 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3712 { 3713 struct mlx5_core_dev *mdev = dev->mdev; 3714 3715 if (dev->lag_active) { 3716 dev->lag_active = false; 3717 3718 mlx5e_lag_event_unregister(dev); 3719 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3720 dev->flow_db->lag_demux_ft = NULL; 3721 3722 mlx5_cmd_destroy_vport_lag(mdev); 3723 } 3724 } 3725 3726 static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3727 struct net_device *netdev) 3728 { 3729 int err; 3730 3731 if (roce->tracking_netdev) 3732 return; 3733 roce->tracking_netdev = netdev; 3734 roce->nb.notifier_call = mlx5_netdev_event; 3735 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3736 WARN_ON(err); 3737 } 3738 3739 static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3740 { 3741 if (!roce->tracking_netdev) 3742 return; 3743 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3744 &roce->nn); 3745 roce->tracking_netdev = NULL; 3746 } 3747 3748 static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3749 unsigned long event, void *data) 3750 { 3751 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3752 struct net_device *netdev = data; 3753 3754 switch (event) { 3755 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3756 if (netdev) 3757 mlx5_netdev_notifier_register(roce, netdev); 3758 else 3759 mlx5_netdev_notifier_unregister(roce); 3760 break; 3761 default: 3762 return NOTIFY_DONE; 3763 } 3764 3765 return NOTIFY_OK; 3766 } 3767 3768 static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3769 { 3770 struct mlx5_roce *roce = &dev->port[port_num].roce; 3771 3772 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3773 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3774 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3775 } 3776 3777 static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3778 { 3779 struct mlx5_roce *roce = &dev->port[port_num].roce; 3780 3781 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3782 mlx5_netdev_notifier_unregister(roce); 3783 } 3784 3785 static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3786 { 3787 int err; 3788 3789 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3790 err = mlx5_nic_vport_enable_roce(dev->mdev); 3791 if (err) 3792 return err; 3793 } 3794 3795 err = mlx5_eth_lag_init(dev); 3796 if (err) 3797 goto err_disable_roce; 3798 3799 return 0; 3800 3801 err_disable_roce: 3802 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3803 mlx5_nic_vport_disable_roce(dev->mdev); 3804 3805 return err; 3806 } 3807 3808 static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3809 { 3810 mlx5_eth_lag_cleanup(dev); 3811 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3812 mlx5_nic_vport_disable_roce(dev->mdev); 3813 } 3814 3815 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3816 enum rdma_netdev_t type, 3817 struct rdma_netdev_alloc_params *params) 3818 { 3819 if (type != RDMA_NETDEV_IPOIB) 3820 return -EOPNOTSUPP; 3821 3822 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3823 } 3824 3825 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3826 size_t count, loff_t *pos) 3827 { 3828 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3829 char lbuf[20]; 3830 int len; 3831 3832 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3833 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3834 } 3835 3836 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3837 size_t count, loff_t *pos) 3838 { 3839 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3840 u32 timeout; 3841 u32 var; 3842 3843 if (kstrtouint_from_user(buf, count, 0, &var)) 3844 return -EFAULT; 3845 3846 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3847 1000); 3848 if (timeout != var) 3849 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3850 timeout); 3851 3852 delay_drop->timeout = timeout; 3853 3854 return count; 3855 } 3856 3857 static const struct file_operations fops_delay_drop_timeout = { 3858 .owner = THIS_MODULE, 3859 .open = simple_open, 3860 .write = delay_drop_timeout_write, 3861 .read = delay_drop_timeout_read, 3862 }; 3863 3864 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3865 struct mlx5_ib_multiport_info *mpi) 3866 { 3867 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3868 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3869 int comps; 3870 int err; 3871 int i; 3872 3873 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3874 3875 mlx5_ib_disable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb); 3876 3877 mlx5_core_mp_event_replay(ibdev->mdev, 3878 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3879 NULL); 3880 mlx5_core_mp_event_replay(mpi->mdev, 3881 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3882 NULL); 3883 3884 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3885 3886 spin_lock(&port->mp.mpi_lock); 3887 if (!mpi->ibdev) { 3888 spin_unlock(&port->mp.mpi_lock); 3889 return; 3890 } 3891 3892 mpi->ibdev = NULL; 3893 3894 spin_unlock(&port->mp.mpi_lock); 3895 if (mpi->mdev_events.notifier_call) 3896 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3897 mpi->mdev_events.notifier_call = NULL; 3898 mlx5_mdev_netdev_untrack(ibdev, port_num); 3899 spin_lock(&port->mp.mpi_lock); 3900 3901 comps = mpi->mdev_refcnt; 3902 if (comps) { 3903 mpi->unaffiliate = true; 3904 init_completion(&mpi->unref_comp); 3905 spin_unlock(&port->mp.mpi_lock); 3906 3907 for (i = 0; i < comps; i++) 3908 wait_for_completion(&mpi->unref_comp); 3909 3910 spin_lock(&port->mp.mpi_lock); 3911 mpi->unaffiliate = false; 3912 } 3913 3914 port->mp.mpi = NULL; 3915 3916 spin_unlock(&port->mp.mpi_lock); 3917 3918 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3919 3920 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3921 /* Log an error, still needed to cleanup the pointers and add 3922 * it back to the list. 3923 */ 3924 if (err) 3925 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3926 port_num + 1); 3927 3928 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3929 } 3930 3931 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3932 struct mlx5_ib_multiport_info *mpi) 3933 { 3934 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3935 u64 key; 3936 int err; 3937 3938 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3939 3940 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3941 if (ibdev->port[port_num].mp.mpi) { 3942 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3943 port_num + 1); 3944 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3945 return false; 3946 } 3947 3948 ibdev->port[port_num].mp.mpi = mpi; 3949 mpi->ibdev = ibdev; 3950 mpi->mdev_events.notifier_call = NULL; 3951 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3952 3953 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3954 if (err) 3955 goto unbind; 3956 3957 mlx5_mdev_netdev_track(ibdev, port_num); 3958 3959 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3960 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3961 3962 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3963 3964 key = mpi->mdev->priv.adev_idx; 3965 mlx5_core_mp_event_replay(mpi->mdev, 3966 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3967 &key); 3968 mlx5_core_mp_event_replay(ibdev->mdev, 3969 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3970 &key); 3971 3972 err = mlx5_ib_enable_lb_mp(ibdev->mdev, mpi->mdev, &ibdev->lb); 3973 if (err) 3974 goto unbind; 3975 3976 return true; 3977 3978 unbind: 3979 mlx5_ib_unbind_slave_port(ibdev, mpi); 3980 return false; 3981 } 3982 3983 static int mlx5_ib_data_direct_init(struct mlx5_ib_dev *dev) 3984 { 3985 char vuid[MLX5_ST_SZ_BYTES(array1024_auto) + 1] = {}; 3986 int ret; 3987 3988 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 3989 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 3990 return 0; 3991 3992 ret = mlx5_cmd_query_vuid(dev->mdev, true, vuid); 3993 if (ret) 3994 return ret; 3995 3996 ret = mlx5_ib_create_data_direct_resources(dev); 3997 if (ret) 3998 return ret; 3999 4000 INIT_LIST_HEAD(&dev->data_direct_mr_list); 4001 ret = mlx5_data_direct_ib_reg(dev, vuid); 4002 if (ret) 4003 mlx5_ib_free_data_direct_resources(dev); 4004 4005 return ret; 4006 } 4007 4008 static void mlx5_ib_data_direct_cleanup(struct mlx5_ib_dev *dev) 4009 { 4010 if (!MLX5_CAP_GEN(dev->mdev, data_direct) || 4011 !MLX5_CAP_GEN_2(dev->mdev, query_vuid)) 4012 return; 4013 4014 mlx5_data_direct_ib_unreg(dev); 4015 mlx5_ib_free_data_direct_resources(dev); 4016 } 4017 4018 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 4019 { 4020 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4021 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4022 port_num + 1); 4023 struct mlx5_ib_multiport_info *mpi; 4024 int err; 4025 u32 i; 4026 4027 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4028 return 0; 4029 4030 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 4031 &dev->sys_image_guid); 4032 if (err) 4033 return err; 4034 4035 err = mlx5_nic_vport_enable_roce(dev->mdev); 4036 if (err) 4037 return err; 4038 4039 mutex_lock(&mlx5_ib_multiport_mutex); 4040 for (i = 0; i < dev->num_ports; i++) { 4041 bool bound = false; 4042 4043 /* build a stub multiport info struct for the native port. */ 4044 if (i == port_num) { 4045 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4046 if (!mpi) { 4047 mutex_unlock(&mlx5_ib_multiport_mutex); 4048 mlx5_nic_vport_disable_roce(dev->mdev); 4049 return -ENOMEM; 4050 } 4051 4052 mpi->is_master = true; 4053 mpi->mdev = dev->mdev; 4054 mpi->sys_image_guid = dev->sys_image_guid; 4055 dev->port[i].mp.mpi = mpi; 4056 mpi->ibdev = dev; 4057 mpi = NULL; 4058 continue; 4059 } 4060 4061 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 4062 list) { 4063 if (dev->sys_image_guid == mpi->sys_image_guid && 4064 (mlx5_core_native_port_num(mpi->mdev) - 1) == i && 4065 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) { 4066 bound = mlx5_ib_bind_slave_port(dev, mpi); 4067 } 4068 4069 if (bound) { 4070 dev_dbg(mpi->mdev->device, 4071 "removing port from unaffiliated list.\n"); 4072 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 4073 list_del(&mpi->list); 4074 break; 4075 } 4076 } 4077 if (!bound) 4078 mlx5_ib_dbg(dev, "no free port found for port %d\n", 4079 i + 1); 4080 } 4081 4082 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 4083 mutex_unlock(&mlx5_ib_multiport_mutex); 4084 return err; 4085 } 4086 4087 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 4088 { 4089 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4090 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 4091 port_num + 1); 4092 u32 i; 4093 4094 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 4095 return; 4096 4097 mutex_lock(&mlx5_ib_multiport_mutex); 4098 for (i = 0; i < dev->num_ports; i++) { 4099 if (dev->port[i].mp.mpi) { 4100 /* Destroy the native port stub */ 4101 if (i == port_num) { 4102 kfree(dev->port[i].mp.mpi); 4103 dev->port[i].mp.mpi = NULL; 4104 } else { 4105 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 4106 i + 1); 4107 list_add_tail(&dev->port[i].mp.mpi->list, 4108 &mlx5_ib_unaffiliated_port_list); 4109 mlx5_ib_unbind_slave_port(dev, 4110 dev->port[i].mp.mpi); 4111 } 4112 } 4113 } 4114 4115 mlx5_ib_dbg(dev, "removing from devlist\n"); 4116 list_del(&dev->ib_dev_list); 4117 mutex_unlock(&mlx5_ib_multiport_mutex); 4118 4119 mlx5_nic_vport_disable_roce(dev->mdev); 4120 } 4121 4122 static int mmap_obj_cleanup(struct ib_uobject *uobject, 4123 enum rdma_remove_reason why, 4124 struct uverbs_attr_bundle *attrs) 4125 { 4126 struct mlx5_user_mmap_entry *obj = uobject->object; 4127 4128 rdma_user_mmap_entry_remove(&obj->rdma_entry); 4129 return 0; 4130 } 4131 4132 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 4133 struct mlx5_user_mmap_entry *entry, 4134 size_t length) 4135 { 4136 return rdma_user_mmap_entry_insert_range( 4137 &c->ibucontext, &entry->rdma_entry, length, 4138 (MLX5_IB_MMAP_OFFSET_START << 16), 4139 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 4140 } 4141 4142 static struct mlx5_user_mmap_entry * 4143 alloc_var_entry(struct mlx5_ib_ucontext *c) 4144 { 4145 struct mlx5_user_mmap_entry *entry; 4146 struct mlx5_var_table *var_table; 4147 u32 page_idx; 4148 int err; 4149 4150 var_table = &to_mdev(c->ibucontext.device)->var_table; 4151 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 4152 if (!entry) 4153 return ERR_PTR(-ENOMEM); 4154 4155 mutex_lock(&var_table->bitmap_lock); 4156 page_idx = find_first_zero_bit(var_table->bitmap, 4157 var_table->num_var_hw_entries); 4158 if (page_idx >= var_table->num_var_hw_entries) { 4159 err = -ENOSPC; 4160 mutex_unlock(&var_table->bitmap_lock); 4161 goto end; 4162 } 4163 4164 set_bit(page_idx, var_table->bitmap); 4165 mutex_unlock(&var_table->bitmap_lock); 4166 4167 entry->address = var_table->hw_start_addr + 4168 (page_idx * var_table->stride_size); 4169 entry->page_idx = page_idx; 4170 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 4171 4172 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 4173 var_table->stride_size); 4174 if (err) 4175 goto err_insert; 4176 4177 return entry; 4178 4179 err_insert: 4180 mutex_lock(&var_table->bitmap_lock); 4181 clear_bit(page_idx, var_table->bitmap); 4182 mutex_unlock(&var_table->bitmap_lock); 4183 end: 4184 kfree(entry); 4185 return ERR_PTR(err); 4186 } 4187 4188 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 4189 struct uverbs_attr_bundle *attrs) 4190 { 4191 struct ib_uobject *uobj = uverbs_attr_get_uobject( 4192 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 4193 struct mlx5_ib_ucontext *c; 4194 struct mlx5_user_mmap_entry *entry; 4195 u64 mmap_offset; 4196 u32 length; 4197 int err; 4198 4199 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 4200 if (IS_ERR(c)) 4201 return PTR_ERR(c); 4202 4203 entry = alloc_var_entry(c); 4204 if (IS_ERR(entry)) 4205 return PTR_ERR(entry); 4206 4207 mmap_offset = mlx5_entry_to_mmap_offset(entry); 4208 length = entry->rdma_entry.npages * PAGE_SIZE; 4209 uobj->object = entry; 4210 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 4211 4212 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 4213 &mmap_offset, sizeof(mmap_offset)); 4214 if (err) 4215 return err; 4216 4217 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 4218 &entry->page_idx, sizeof(entry->page_idx)); 4219 if (err) 4220 return err; 4221 4222 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 4223 &length, sizeof(length)); 4224 return err; 4225 } 4226 4227 DECLARE_UVERBS_NAMED_METHOD( 4228 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 4229 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 4230 MLX5_IB_OBJECT_VAR, 4231 UVERBS_ACCESS_NEW, 4232 UA_MANDATORY), 4233 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 4234 UVERBS_ATTR_TYPE(u32), 4235 UA_MANDATORY), 4236 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 4237 UVERBS_ATTR_TYPE(u32), 4238 UA_MANDATORY), 4239 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 4240 UVERBS_ATTR_TYPE(u64), 4241 UA_MANDATORY)); 4242 4243 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 4244 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 4245 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 4246 MLX5_IB_OBJECT_VAR, 4247 UVERBS_ACCESS_DESTROY, 4248 UA_MANDATORY)); 4249 4250 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 4251 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 4252 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 4253 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 4254 4255 static bool var_is_supported(struct ib_device *device) 4256 { 4257 struct mlx5_ib_dev *dev = to_mdev(device); 4258 4259 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4260 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 4261 } 4262 4263 static struct mlx5_user_mmap_entry * 4264 alloc_uar_entry(struct mlx5_ib_ucontext *c, 4265 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 4266 { 4267 struct mlx5_user_mmap_entry *entry; 4268 struct mlx5_ib_dev *dev; 4269 u32 uar_index; 4270 int err; 4271 4272 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 4273 if (!entry) 4274 return ERR_PTR(-ENOMEM); 4275 4276 dev = to_mdev(c->ibucontext.device); 4277 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 4278 if (err) 4279 goto end; 4280 4281 entry->page_idx = uar_index; 4282 entry->address = uar_index2paddress(dev, uar_index); 4283 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 4284 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 4285 else 4286 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 4287 4288 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 4289 if (err) 4290 goto err_insert; 4291 4292 return entry; 4293 4294 err_insert: 4295 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 4296 end: 4297 kfree(entry); 4298 return ERR_PTR(err); 4299 } 4300 4301 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 4302 struct uverbs_attr_bundle *attrs) 4303 { 4304 struct ib_uobject *uobj = uverbs_attr_get_uobject( 4305 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 4306 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 4307 struct mlx5_ib_ucontext *c; 4308 struct mlx5_user_mmap_entry *entry; 4309 u64 mmap_offset; 4310 u32 length; 4311 int err; 4312 4313 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 4314 if (IS_ERR(c)) 4315 return PTR_ERR(c); 4316 4317 err = uverbs_get_const(&alloc_type, attrs, 4318 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 4319 if (err) 4320 return err; 4321 4322 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 4323 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 4324 return -EOPNOTSUPP; 4325 4326 if (!mlx5_wc_support_get(to_mdev(c->ibucontext.device)->mdev) && 4327 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 4328 return -EOPNOTSUPP; 4329 4330 entry = alloc_uar_entry(c, alloc_type); 4331 if (IS_ERR(entry)) 4332 return PTR_ERR(entry); 4333 4334 mmap_offset = mlx5_entry_to_mmap_offset(entry); 4335 length = entry->rdma_entry.npages * PAGE_SIZE; 4336 uobj->object = entry; 4337 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 4338 4339 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4340 &mmap_offset, sizeof(mmap_offset)); 4341 if (err) 4342 return err; 4343 4344 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4345 &entry->page_idx, sizeof(entry->page_idx)); 4346 if (err) 4347 return err; 4348 4349 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4350 &length, sizeof(length)); 4351 return err; 4352 } 4353 4354 DECLARE_UVERBS_NAMED_METHOD( 4355 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 4356 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 4357 MLX5_IB_OBJECT_UAR, 4358 UVERBS_ACCESS_NEW, 4359 UA_MANDATORY), 4360 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 4361 enum mlx5_ib_uapi_uar_alloc_type, 4362 UA_MANDATORY), 4363 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 4364 UVERBS_ATTR_TYPE(u32), 4365 UA_MANDATORY), 4366 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 4367 UVERBS_ATTR_TYPE(u32), 4368 UA_MANDATORY), 4369 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 4370 UVERBS_ATTR_TYPE(u64), 4371 UA_MANDATORY)); 4372 4373 DECLARE_UVERBS_NAMED_METHOD_DESTROY( 4374 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 4375 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 4376 MLX5_IB_OBJECT_UAR, 4377 UVERBS_ACCESS_DESTROY, 4378 UA_MANDATORY)); 4379 4380 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 4381 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 4382 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 4383 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 4384 4385 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4386 mlx5_ib_query_context, 4387 UVERBS_OBJECT_DEVICE, 4388 UVERBS_METHOD_QUERY_CONTEXT, 4389 UVERBS_ATTR_PTR_OUT( 4390 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 4391 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 4392 dump_fill_mkey), 4393 UA_MANDATORY)); 4394 4395 ADD_UVERBS_ATTRIBUTES_SIMPLE( 4396 mlx5_ib_reg_dmabuf_mr, 4397 UVERBS_OBJECT_MR, 4398 UVERBS_METHOD_REG_DMABUF_MR, 4399 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_REG_DMABUF_MR_ACCESS_FLAGS, 4400 enum mlx5_ib_uapi_reg_dmabuf_flags, 4401 UA_OPTIONAL)); 4402 4403 static const struct uapi_definition mlx5_ib_defs[] = { 4404 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 4405 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 4406 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 4407 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 4408 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 4409 UAPI_DEF_CHAIN(mlx5_ib_create_cq_defs), 4410 4411 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 4412 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_MR, &mlx5_ib_reg_dmabuf_mr), 4413 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 4414 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 4415 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 4416 {} 4417 }; 4418 4419 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 4420 { 4421 mlx5_ib_data_direct_cleanup(dev); 4422 mlx5_ib_cleanup_multiport_master(dev); 4423 WARN_ON(!xa_empty(&dev->odp_mkeys)); 4424 mutex_destroy(&dev->cap_mask_mutex); 4425 WARN_ON(!xa_empty(&dev->sig_mrs)); 4426 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 4427 mlx5r_macsec_dealloc_gids(dev); 4428 } 4429 4430 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 4431 { 4432 struct mlx5_core_dev *mdev = dev->mdev; 4433 int err, i; 4434 4435 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 4436 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 4437 dev->ib_dev.dev.parent = mdev->device; 4438 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 4439 4440 for (i = 0; i < dev->num_ports; i++) { 4441 spin_lock_init(&dev->port[i].mp.mpi_lock); 4442 dev->port[i].roce.dev = dev; 4443 dev->port[i].roce.native_port_num = i + 1; 4444 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 4445 } 4446 4447 err = mlx5r_cmd_query_special_mkeys(dev); 4448 if (err) 4449 return err; 4450 4451 err = mlx5r_macsec_init_gids_and_devlist(dev); 4452 if (err) 4453 return err; 4454 4455 err = mlx5_ib_init_multiport_master(dev); 4456 if (err) 4457 goto err; 4458 4459 err = set_has_smi_cap(dev); 4460 if (err) 4461 goto err_mp; 4462 4463 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 4464 if (err) 4465 goto err_mp; 4466 4467 if (mlx5_use_mad_ifc(dev)) 4468 get_ext_port_caps(dev); 4469 4470 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 4471 4472 mutex_init(&dev->cap_mask_mutex); 4473 mutex_init(&dev->data_direct_lock); 4474 INIT_LIST_HEAD(&dev->qp_list); 4475 spin_lock_init(&dev->reset_flow_resource_lock); 4476 xa_init(&dev->odp_mkeys); 4477 xa_init(&dev->sig_mrs); 4478 atomic_set(&dev->mkey_var, 0); 4479 4480 spin_lock_init(&dev->dm.lock); 4481 dev->dm.dev = mdev; 4482 err = mlx5_ib_data_direct_init(dev); 4483 if (err) 4484 goto err_mp; 4485 4486 err = pcim_p2pdma_init(mdev->pdev); 4487 if (err && err != -EOPNOTSUPP) 4488 goto err_dd; 4489 4490 return 0; 4491 err_dd: 4492 mlx5_ib_data_direct_cleanup(dev); 4493 err_mp: 4494 mlx5_ib_cleanup_multiport_master(dev); 4495 err: 4496 mlx5r_macsec_dealloc_gids(dev); 4497 return err; 4498 } 4499 4500 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 4501 enum rdma_nl_dev_type type, 4502 const char *name); 4503 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev); 4504 4505 static const struct ib_device_ops mlx5_ib_dev_ops = { 4506 .owner = THIS_MODULE, 4507 .driver_id = RDMA_DRIVER_MLX5, 4508 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 4509 4510 .add_gid = mlx5_ib_add_gid, 4511 .add_sub_dev = mlx5_ib_add_sub_dev, 4512 .alloc_mr = mlx5_ib_alloc_mr, 4513 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 4514 .alloc_pd = mlx5_ib_alloc_pd, 4515 .alloc_ucontext = mlx5_ib_alloc_ucontext, 4516 .attach_mcast = mlx5_ib_mcg_attach, 4517 .check_mr_status = mlx5_ib_check_mr_status, 4518 .create_ah = mlx5_ib_create_ah, 4519 .create_cq = mlx5_ib_create_cq, 4520 .create_qp = mlx5_ib_create_qp, 4521 .create_srq = mlx5_ib_create_srq, 4522 .create_user_ah = mlx5_ib_create_ah, 4523 .dealloc_pd = mlx5_ib_dealloc_pd, 4524 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 4525 .del_gid = mlx5_ib_del_gid, 4526 .del_sub_dev = mlx5_ib_del_sub_dev, 4527 .dereg_mr = mlx5_ib_dereg_mr, 4528 .destroy_ah = mlx5_ib_destroy_ah, 4529 .destroy_cq = mlx5_ib_destroy_cq, 4530 .destroy_qp = mlx5_ib_destroy_qp, 4531 .destroy_srq = mlx5_ib_destroy_srq, 4532 .detach_mcast = mlx5_ib_mcg_detach, 4533 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 4534 .drain_rq = mlx5_ib_drain_rq, 4535 .drain_sq = mlx5_ib_drain_sq, 4536 .device_group = &mlx5_attr_group, 4537 .get_dev_fw_str = get_dev_fw_str, 4538 .get_dma_mr = mlx5_ib_get_dma_mr, 4539 .get_link_layer = mlx5_ib_port_link_layer, 4540 .map_mr_sg = mlx5_ib_map_mr_sg, 4541 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 4542 .mmap = mlx5_ib_mmap, 4543 .mmap_free = mlx5_ib_mmap_free, 4544 .mmap_get_pfns = mlx5_ib_mmap_get_pfns, 4545 .modify_cq = mlx5_ib_modify_cq, 4546 .modify_device = mlx5_ib_modify_device, 4547 .modify_port = mlx5_ib_modify_port, 4548 .modify_qp = mlx5_ib_modify_qp, 4549 .modify_srq = mlx5_ib_modify_srq, 4550 .pgoff_to_mmap_entry = mlx5_ib_pgoff_to_mmap_entry, 4551 .pre_destroy_cq = mlx5_ib_pre_destroy_cq, 4552 .poll_cq = mlx5_ib_poll_cq, 4553 .post_destroy_cq = mlx5_ib_post_destroy_cq, 4554 .post_recv = mlx5_ib_post_recv_nodrain, 4555 .post_send = mlx5_ib_post_send_nodrain, 4556 .post_srq_recv = mlx5_ib_post_srq_recv, 4557 .process_mad = mlx5_ib_process_mad, 4558 .query_ah = mlx5_ib_query_ah, 4559 .query_device = mlx5_ib_query_device, 4560 .query_gid = mlx5_ib_query_gid, 4561 .query_pkey = mlx5_ib_query_pkey, 4562 .query_port_speed = mlx5_ib_query_port_speed, 4563 .query_qp = mlx5_ib_query_qp, 4564 .query_srq = mlx5_ib_query_srq, 4565 .query_ucontext = mlx5_ib_query_ucontext, 4566 .reg_user_mr = mlx5_ib_reg_user_mr, 4567 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 4568 .req_notify_cq = mlx5_ib_arm_cq, 4569 .rereg_user_mr = mlx5_ib_rereg_user_mr, 4570 .resize_cq = mlx5_ib_resize_cq, 4571 .ufile_hw_cleanup = mlx5_ib_ufile_hw_cleanup, 4572 4573 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 4574 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 4575 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 4576 INIT_RDMA_OBJ_SIZE(ib_dmah, mlx5_ib_dmah, ibdmah), 4577 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 4578 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 4579 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 4580 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 4581 }; 4582 4583 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 4584 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 4585 }; 4586 4587 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 4588 .get_vf_config = mlx5_ib_get_vf_config, 4589 .get_vf_guid = mlx5_ib_get_vf_guid, 4590 .get_vf_stats = mlx5_ib_get_vf_stats, 4591 .set_vf_guid = mlx5_ib_set_vf_guid, 4592 .set_vf_link_state = mlx5_ib_set_vf_link_state, 4593 }; 4594 4595 static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 4596 .alloc_mw = mlx5_ib_alloc_mw, 4597 .dealloc_mw = mlx5_ib_dealloc_mw, 4598 4599 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 4600 }; 4601 4602 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 4603 .alloc_xrcd = mlx5_ib_alloc_xrcd, 4604 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 4605 4606 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 4607 }; 4608 4609 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 4610 { 4611 struct mlx5_core_dev *mdev = dev->mdev; 4612 struct mlx5_var_table *var_table = &dev->var_table; 4613 u8 log_doorbell_bar_size; 4614 u8 log_doorbell_stride; 4615 u64 bar_size; 4616 4617 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4618 log_doorbell_bar_size); 4619 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 4620 log_doorbell_stride); 4621 var_table->hw_start_addr = dev->mdev->bar_addr + 4622 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 4623 doorbell_bar_offset); 4624 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 4625 var_table->stride_size = 1ULL << log_doorbell_stride; 4626 var_table->num_var_hw_entries = div_u64(bar_size, 4627 var_table->stride_size); 4628 mutex_init(&var_table->bitmap_lock); 4629 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 4630 GFP_KERNEL); 4631 return (var_table->bitmap) ? 0 : -ENOMEM; 4632 } 4633 4634 static void mlx5_ib_cleanup_ucaps(struct mlx5_ib_dev *dev) 4635 { 4636 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4637 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4638 4639 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4640 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) 4641 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4642 } 4643 4644 static int mlx5_ib_init_ucaps(struct mlx5_ib_dev *dev) 4645 { 4646 int ret; 4647 4648 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) { 4649 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4650 if (ret) 4651 return ret; 4652 } 4653 4654 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & 4655 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA) { 4656 ret = ib_create_ucap(RDMA_UCAP_MLX5_CTRL_OTHER_VHCA); 4657 if (ret) 4658 goto remove_local; 4659 } 4660 4661 return 0; 4662 4663 remove_local: 4664 if (MLX5_CAP_GEN(dev->mdev, uctx_cap) & MLX5_UCTX_CAP_RDMA_CTRL) 4665 ib_remove_ucap(RDMA_UCAP_MLX5_CTRL_LOCAL); 4666 return ret; 4667 } 4668 4669 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 4670 { 4671 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4672 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) 4673 mlx5_ib_cleanup_ucaps(dev); 4674 4675 bitmap_free(dev->var_table.bitmap); 4676 } 4677 4678 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 4679 { 4680 struct mlx5_core_dev *mdev = dev->mdev; 4681 int err; 4682 4683 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 4684 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 4685 ib_set_device_ops(&dev->ib_dev, 4686 &mlx5_ib_dev_ipoib_enhanced_ops); 4687 4688 if (mlx5_core_is_pf(mdev)) 4689 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 4690 4691 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 4692 4693 if (MLX5_CAP_GEN(mdev, imaicl)) 4694 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 4695 4696 if (MLX5_CAP_GEN(mdev, xrc)) 4697 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 4698 4699 if (MLX5_CAP_DEV_MEM(mdev, memic) || 4700 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4701 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 4702 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 4703 4704 if (mdev->st) 4705 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dmah_ops); 4706 4707 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 4708 4709 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 4710 dev->ib_dev.driver_def = mlx5_ib_defs; 4711 4712 err = init_node_data(dev); 4713 if (err) 4714 return err; 4715 4716 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 4717 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 4718 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 4719 mutex_init(&dev->lb.mutex); 4720 4721 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 4722 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 4723 err = mlx5_ib_init_var_table(dev); 4724 if (err) 4725 return err; 4726 } 4727 4728 if (MLX5_CAP_GEN_2_64(dev->mdev, general_obj_types_127_64) & 4729 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL) { 4730 err = mlx5_ib_init_ucaps(dev); 4731 if (err) 4732 goto err_ucaps; 4733 } 4734 4735 dev->ib_dev.use_cq_dim = true; 4736 4737 return 0; 4738 4739 err_ucaps: 4740 bitmap_free(dev->var_table.bitmap); 4741 return err; 4742 } 4743 4744 static const struct ib_device_ops mlx5_ib_dev_port_ops = { 4745 .get_port_immutable = mlx5_port_immutable, 4746 .query_port = mlx5_ib_query_port, 4747 }; 4748 4749 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 4750 { 4751 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 4752 return 0; 4753 } 4754 4755 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 4756 .get_port_immutable = mlx5_port_rep_immutable, 4757 .query_port = mlx5_ib_rep_query_port, 4758 .query_pkey = mlx5_ib_rep_query_pkey, 4759 }; 4760 4761 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 4762 { 4763 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 4764 return 0; 4765 } 4766 4767 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 4768 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 4769 .create_wq = mlx5_ib_create_wq, 4770 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 4771 .destroy_wq = mlx5_ib_destroy_wq, 4772 .modify_wq = mlx5_ib_modify_wq, 4773 4774 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 4775 ib_rwq_ind_tbl), 4776 }; 4777 4778 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 4779 { 4780 struct mlx5_core_dev *mdev = dev->mdev; 4781 enum rdma_link_layer ll; 4782 int port_type_cap; 4783 u32 port_num = 0; 4784 int err; 4785 4786 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4787 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4788 4789 if (ll == IB_LINK_LAYER_ETHERNET) { 4790 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4791 4792 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4793 4794 /* Register only for native ports */ 4795 mlx5_mdev_netdev_track(dev, port_num); 4796 4797 err = mlx5_enable_eth(dev); 4798 if (err) 4799 goto cleanup; 4800 } 4801 4802 return 0; 4803 cleanup: 4804 mlx5_mdev_netdev_untrack(dev, port_num); 4805 return err; 4806 } 4807 4808 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4809 { 4810 struct mlx5_core_dev *mdev = dev->mdev; 4811 enum rdma_link_layer ll; 4812 int port_type_cap; 4813 u32 port_num; 4814 4815 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4816 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4817 4818 if (ll == IB_LINK_LAYER_ETHERNET) { 4819 mlx5_disable_eth(dev); 4820 4821 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4822 mlx5_mdev_netdev_untrack(dev, port_num); 4823 } 4824 } 4825 4826 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4827 { 4828 mlx5_ib_init_cong_debugfs(dev, 4829 mlx5_core_native_port_num(dev->mdev) - 1); 4830 return 0; 4831 } 4832 4833 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4834 { 4835 mlx5_ib_cleanup_cong_debugfs(dev, 4836 mlx5_core_native_port_num(dev->mdev) - 1); 4837 } 4838 4839 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4840 { 4841 int err; 4842 4843 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4844 if (err) 4845 return err; 4846 4847 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4848 if (err) 4849 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4850 4851 return err; 4852 } 4853 4854 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4855 { 4856 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4857 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4858 } 4859 4860 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4861 { 4862 const char *name; 4863 4864 if (dev->sub_dev_name) { 4865 name = dev->sub_dev_name; 4866 ib_mark_name_assigned_by_user(&dev->ib_dev); 4867 } else if (!mlx5_lag_is_active(dev->mdev)) 4868 name = "mlx5_%d"; 4869 else 4870 name = "mlx5_bond_%d"; 4871 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4872 } 4873 4874 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4875 { 4876 mlx5_mkey_cache_cleanup(dev); 4877 mlx5r_umr_resource_cleanup(dev); 4878 mlx5r_umr_cleanup(dev); 4879 } 4880 4881 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4882 { 4883 ib_unregister_device(&dev->ib_dev); 4884 } 4885 4886 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4887 { 4888 int ret; 4889 4890 ret = mlx5r_umr_init(dev); 4891 if (ret) 4892 return ret; 4893 4894 ret = mlx5_mkey_cache_init(dev); 4895 if (ret) 4896 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4897 return ret; 4898 } 4899 4900 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4901 { 4902 struct dentry *root; 4903 4904 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4905 return 0; 4906 4907 mutex_init(&dev->delay_drop.lock); 4908 dev->delay_drop.dev = dev; 4909 dev->delay_drop.activate = false; 4910 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4911 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4912 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4913 atomic_set(&dev->delay_drop.events_cnt, 0); 4914 4915 if (!mlx5_debugfs_root) 4916 return 0; 4917 4918 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4919 dev->delay_drop.dir_debugfs = root; 4920 4921 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4922 &dev->delay_drop.events_cnt); 4923 debugfs_create_atomic_t("num_rqs", 0400, root, 4924 &dev->delay_drop.rqs_cnt); 4925 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4926 &fops_delay_drop_timeout); 4927 return 0; 4928 } 4929 4930 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4931 { 4932 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4933 return; 4934 4935 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4936 if (!dev->delay_drop.dir_debugfs) 4937 return; 4938 4939 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4940 dev->delay_drop.dir_debugfs = NULL; 4941 } 4942 4943 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4944 { 4945 struct mlx5_ib_resources *devr = &dev->devr; 4946 int port; 4947 4948 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4949 INIT_WORK(&devr->ports[port].pkey_change_work, 4950 pkey_change_handler); 4951 4952 dev->mdev_events.notifier_call = mlx5_ib_event; 4953 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4954 4955 mlx5r_macsec_event_register(dev); 4956 4957 return 0; 4958 } 4959 4960 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4961 { 4962 struct mlx5_ib_resources *devr = &dev->devr; 4963 int port; 4964 4965 mlx5r_macsec_event_unregister(dev); 4966 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4967 4968 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 4969 cancel_work_sync(&devr->ports[port].pkey_change_work); 4970 } 4971 4972 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, 4973 struct mlx5_data_direct_dev *dev) 4974 { 4975 mutex_lock(&ibdev->data_direct_lock); 4976 ibdev->data_direct_dev = dev; 4977 mutex_unlock(&ibdev->data_direct_lock); 4978 } 4979 4980 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev) 4981 { 4982 mutex_lock(&ibdev->data_direct_lock); 4983 mlx5_ib_revoke_data_direct_mrs(ibdev); 4984 ibdev->data_direct_dev = NULL; 4985 mutex_unlock(&ibdev->data_direct_lock); 4986 } 4987 4988 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4989 const struct mlx5_ib_profile *profile, 4990 int stage) 4991 { 4992 dev->ib_active = false; 4993 4994 /* Number of stages to cleanup */ 4995 while (stage) { 4996 stage--; 4997 if (profile->stage[stage].cleanup) 4998 profile->stage[stage].cleanup(dev); 4999 } 5000 5001 kfree(dev->port); 5002 ib_dealloc_device(&dev->ib_dev); 5003 } 5004 5005 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 5006 const struct mlx5_ib_profile *profile) 5007 { 5008 int err; 5009 int i; 5010 5011 dev->profile = profile; 5012 5013 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 5014 if (profile->stage[i].init) { 5015 err = profile->stage[i].init(dev); 5016 if (err) 5017 goto err_out; 5018 } 5019 } 5020 5021 dev->ib_active = true; 5022 return 0; 5023 5024 err_out: 5025 /* Clean up stages which were initialized */ 5026 while (i) { 5027 i--; 5028 if (profile->stage[i].cleanup) 5029 profile->stage[i].cleanup(dev); 5030 } 5031 return -ENOMEM; 5032 } 5033 5034 static const struct mlx5_ib_profile pf_profile = { 5035 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5036 mlx5_ib_stage_init_init, 5037 mlx5_ib_stage_init_cleanup), 5038 STAGE_CREATE(MLX5_IB_STAGE_FS, 5039 mlx5_ib_fs_init, 5040 mlx5_ib_fs_cleanup), 5041 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5042 mlx5_ib_stage_caps_init, 5043 mlx5_ib_stage_caps_cleanup), 5044 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5045 mlx5_ib_stage_non_default_cb, 5046 NULL), 5047 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5048 mlx5_ib_roce_init, 5049 mlx5_ib_roce_cleanup), 5050 STAGE_CREATE(MLX5_IB_STAGE_QP, 5051 mlx5_init_qp_table, 5052 mlx5_cleanup_qp_table), 5053 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 5054 mlx5_init_srq_table, 5055 mlx5_cleanup_srq_table), 5056 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5057 mlx5_ib_dev_res_init, 5058 mlx5_ib_dev_res_cleanup), 5059 STAGE_CREATE(MLX5_IB_STAGE_ODP, 5060 mlx5_ib_odp_init_one, 5061 mlx5_ib_odp_cleanup_one), 5062 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5063 mlx5_ib_counters_init, 5064 mlx5_ib_counters_cleanup), 5065 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 5066 mlx5_ib_stage_cong_debugfs_init, 5067 mlx5_ib_stage_cong_debugfs_cleanup), 5068 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5069 mlx5_ib_stage_bfrag_init, 5070 mlx5_ib_stage_bfrag_cleanup), 5071 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5072 NULL, 5073 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5074 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 5075 mlx5_ib_devx_init, 5076 mlx5_ib_devx_cleanup), 5077 STAGE_CREATE(MLX5_IB_STAGE_SYS_ERROR_NOTIFIER, 5078 mlx5_ib_stage_sys_error_notifier_init, 5079 mlx5_ib_stage_sys_error_notifier_cleanup), 5080 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5081 mlx5_ib_stage_ib_reg_init, 5082 mlx5_ib_stage_ib_reg_cleanup), 5083 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 5084 mlx5_ib_stage_dev_notifier_init, 5085 mlx5_ib_stage_dev_notifier_cleanup), 5086 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5087 mlx5_ib_stage_post_ib_reg_umr_init, 5088 NULL), 5089 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 5090 mlx5_ib_stage_delay_drop_init, 5091 mlx5_ib_stage_delay_drop_cleanup), 5092 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 5093 mlx5_ib_restrack_init, 5094 NULL), 5095 }; 5096 5097 const struct mlx5_ib_profile raw_eth_profile = { 5098 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5099 mlx5_ib_stage_init_init, 5100 mlx5_ib_stage_init_cleanup), 5101 STAGE_CREATE(MLX5_IB_STAGE_FS, 5102 mlx5_ib_fs_init, 5103 mlx5_ib_fs_cleanup), 5104 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5105 mlx5_ib_stage_caps_init, 5106 mlx5_ib_stage_caps_cleanup), 5107 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5108 mlx5_ib_stage_raw_eth_non_default_cb, 5109 NULL), 5110 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 5111 mlx5_ib_roce_init, 5112 mlx5_ib_roce_cleanup), 5113 STAGE_CREATE(MLX5_IB_STAGE_QP, 5114 mlx5_init_qp_table, 5115 mlx5_cleanup_qp_table), 5116 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 5117 mlx5_init_srq_table, 5118 mlx5_cleanup_srq_table), 5119 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5120 mlx5_ib_dev_res_init, 5121 mlx5_ib_dev_res_cleanup), 5122 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 5123 mlx5_ib_counters_init, 5124 mlx5_ib_counters_cleanup), 5125 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 5126 mlx5_ib_stage_cong_debugfs_init, 5127 mlx5_ib_stage_cong_debugfs_cleanup), 5128 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5129 mlx5_ib_stage_bfrag_init, 5130 mlx5_ib_stage_bfrag_cleanup), 5131 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 5132 NULL, 5133 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 5134 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 5135 mlx5_ib_devx_init, 5136 mlx5_ib_devx_cleanup), 5137 STAGE_CREATE(MLX5_IB_STAGE_SYS_ERROR_NOTIFIER, 5138 mlx5_ib_stage_sys_error_notifier_init, 5139 mlx5_ib_stage_sys_error_notifier_cleanup), 5140 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5141 mlx5_ib_stage_ib_reg_init, 5142 mlx5_ib_stage_ib_reg_cleanup), 5143 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 5144 mlx5_ib_stage_dev_notifier_init, 5145 mlx5_ib_stage_dev_notifier_cleanup), 5146 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 5147 mlx5_ib_stage_post_ib_reg_umr_init, 5148 NULL), 5149 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 5150 mlx5_ib_stage_delay_drop_init, 5151 mlx5_ib_stage_delay_drop_cleanup), 5152 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 5153 mlx5_ib_restrack_init, 5154 NULL), 5155 }; 5156 5157 static const struct mlx5_ib_profile plane_profile = { 5158 STAGE_CREATE(MLX5_IB_STAGE_INIT, 5159 mlx5_ib_stage_init_init, 5160 mlx5_ib_stage_init_cleanup), 5161 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 5162 mlx5_ib_stage_caps_init, 5163 mlx5_ib_stage_caps_cleanup), 5164 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 5165 mlx5_ib_stage_non_default_cb, 5166 NULL), 5167 STAGE_CREATE(MLX5_IB_STAGE_QP, 5168 mlx5_init_qp_table, 5169 mlx5_cleanup_qp_table), 5170 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 5171 mlx5_init_srq_table, 5172 mlx5_cleanup_srq_table), 5173 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 5174 mlx5_ib_dev_res_init, 5175 mlx5_ib_dev_res_cleanup), 5176 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 5177 mlx5_ib_stage_bfrag_init, 5178 mlx5_ib_stage_bfrag_cleanup), 5179 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 5180 mlx5_ib_stage_ib_reg_init, 5181 mlx5_ib_stage_ib_reg_cleanup), 5182 }; 5183 5184 static struct ib_device *mlx5_ib_add_sub_dev(struct ib_device *parent, 5185 enum rdma_nl_dev_type type, 5186 const char *name) 5187 { 5188 struct mlx5_ib_dev *mparent = to_mdev(parent), *mplane; 5189 enum rdma_link_layer ll; 5190 int ret; 5191 5192 if (mparent->smi_dev) 5193 return ERR_PTR(-EEXIST); 5194 5195 ll = mlx5_port_type_cap_to_rdma_ll(MLX5_CAP_GEN(mparent->mdev, 5196 port_type)); 5197 if (type != RDMA_DEVICE_TYPE_SMI || !mparent->num_plane || 5198 ll != IB_LINK_LAYER_INFINIBAND || 5199 !MLX5_CAP_GEN_2(mparent->mdev, multiplane_qp_ud)) 5200 return ERR_PTR(-EOPNOTSUPP); 5201 5202 mplane = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 5203 mlx5_core_net(mparent->mdev)); 5204 if (!mplane) 5205 return ERR_PTR(-ENOMEM); 5206 5207 mplane->port = kcalloc(mparent->num_plane * mparent->num_ports, 5208 sizeof(*mplane->port), GFP_KERNEL); 5209 if (!mplane->port) { 5210 ret = -ENOMEM; 5211 goto fail_kcalloc; 5212 } 5213 5214 mplane->ib_dev.type = type; 5215 mplane->mdev = mparent->mdev; 5216 mplane->num_ports = mparent->num_plane; 5217 mplane->sub_dev_name = name; 5218 mplane->ib_dev.phys_port_cnt = mplane->num_ports; 5219 5220 ret = __mlx5_ib_add(mplane, &plane_profile); 5221 if (ret) 5222 goto fail_ib_add; 5223 5224 mparent->smi_dev = mplane; 5225 return &mplane->ib_dev; 5226 5227 fail_ib_add: 5228 kfree(mplane->port); 5229 fail_kcalloc: 5230 ib_dealloc_device(&mplane->ib_dev); 5231 return ERR_PTR(ret); 5232 } 5233 5234 static void mlx5_ib_del_sub_dev(struct ib_device *sub_dev) 5235 { 5236 struct mlx5_ib_dev *mdev = to_mdev(sub_dev); 5237 5238 to_mdev(sub_dev->parent)->smi_dev = NULL; 5239 __mlx5_ib_remove(mdev, mdev->profile, MLX5_IB_STAGE_MAX); 5240 } 5241 5242 static int mlx5r_mp_probe(struct auxiliary_device *adev, 5243 const struct auxiliary_device_id *id) 5244 { 5245 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 5246 struct mlx5_core_dev *mdev = idev->mdev; 5247 struct mlx5_ib_multiport_info *mpi; 5248 struct mlx5_ib_dev *dev; 5249 bool bound = false; 5250 int err; 5251 5252 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 5253 if (!mpi) 5254 return -ENOMEM; 5255 5256 mpi->mdev = mdev; 5257 err = mlx5_query_nic_vport_system_image_guid(mdev, 5258 &mpi->sys_image_guid); 5259 if (err) { 5260 kfree(mpi); 5261 return err; 5262 } 5263 5264 mutex_lock(&mlx5_ib_multiport_mutex); 5265 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 5266 if (dev->sys_image_guid == mpi->sys_image_guid && 5267 mlx5_core_same_coredev_type(dev->mdev, mpi->mdev)) 5268 bound = mlx5_ib_bind_slave_port(dev, mpi); 5269 5270 if (bound) { 5271 rdma_roce_rescan_device(&dev->ib_dev); 5272 mpi->ibdev->ib_active = true; 5273 break; 5274 } 5275 } 5276 5277 if (!bound) { 5278 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 5279 dev_dbg(mdev->device, 5280 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 5281 } 5282 mutex_unlock(&mlx5_ib_multiport_mutex); 5283 5284 auxiliary_set_drvdata(adev, mpi); 5285 return 0; 5286 } 5287 5288 static void mlx5r_mp_remove(struct auxiliary_device *adev) 5289 { 5290 struct mlx5_ib_multiport_info *mpi; 5291 5292 mpi = auxiliary_get_drvdata(adev); 5293 mutex_lock(&mlx5_ib_multiport_mutex); 5294 if (mpi->ibdev) 5295 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 5296 else 5297 list_del(&mpi->list); 5298 mutex_unlock(&mlx5_ib_multiport_mutex); 5299 kfree(mpi); 5300 } 5301 5302 static int mlx5r_probe(struct auxiliary_device *adev, 5303 const struct auxiliary_device_id *id) 5304 { 5305 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 5306 struct mlx5_core_dev *mdev = idev->mdev; 5307 const struct mlx5_ib_profile *profile; 5308 int port_type_cap, num_ports, ret; 5309 enum rdma_link_layer ll; 5310 struct mlx5_ib_dev *dev; 5311 5312 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 5313 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 5314 5315 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 5316 MLX5_CAP_GEN(mdev, num_vhca_ports)); 5317 dev = ib_alloc_device_with_net(mlx5_ib_dev, ib_dev, 5318 mlx5_core_net(mdev)); 5319 if (!dev) 5320 return -ENOMEM; 5321 5322 if (ll == IB_LINK_LAYER_INFINIBAND) { 5323 ret = mlx5_ib_get_plane_num(mdev, &dev->num_plane); 5324 if (ret) 5325 goto fail; 5326 } 5327 5328 dev->port = kcalloc(num_ports, sizeof(*dev->port), 5329 GFP_KERNEL); 5330 if (!dev->port) { 5331 ret = -ENOMEM; 5332 goto fail; 5333 } 5334 5335 dev->mdev = mdev; 5336 dev->num_ports = num_ports; 5337 dev->ib_dev.phys_port_cnt = num_ports; 5338 5339 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 5340 profile = &raw_eth_profile; 5341 else 5342 profile = &pf_profile; 5343 5344 ret = __mlx5_ib_add(dev, profile); 5345 if (ret) 5346 goto fail_ib_add; 5347 5348 auxiliary_set_drvdata(adev, dev); 5349 return 0; 5350 5351 fail_ib_add: 5352 kfree(dev->port); 5353 fail: 5354 ib_dealloc_device(&dev->ib_dev); 5355 return ret; 5356 } 5357 5358 static void mlx5r_remove(struct auxiliary_device *adev) 5359 { 5360 struct mlx5_ib_dev *dev; 5361 5362 dev = auxiliary_get_drvdata(adev); 5363 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 5364 } 5365 5366 static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 5367 { .name = MLX5_ADEV_NAME ".multiport", }, 5368 {}, 5369 }; 5370 5371 static const struct auxiliary_device_id mlx5r_id_table[] = { 5372 { .name = MLX5_ADEV_NAME ".rdma", }, 5373 {}, 5374 }; 5375 5376 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 5377 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 5378 5379 static struct auxiliary_driver mlx5r_mp_driver = { 5380 .name = "multiport", 5381 .probe = mlx5r_mp_probe, 5382 .remove = mlx5r_mp_remove, 5383 .id_table = mlx5r_mp_id_table, 5384 }; 5385 5386 static struct auxiliary_driver mlx5r_driver = { 5387 .name = "rdma", 5388 .probe = mlx5r_probe, 5389 .remove = mlx5r_remove, 5390 .id_table = mlx5r_id_table, 5391 }; 5392 5393 static int __init mlx5_ib_init(void) 5394 { 5395 int ret; 5396 5397 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 5398 if (!xlt_emergency_page) 5399 return -ENOMEM; 5400 5401 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 5402 if (!mlx5_ib_event_wq) { 5403 free_page((unsigned long)xlt_emergency_page); 5404 return -ENOMEM; 5405 } 5406 5407 ret = mlx5_ib_qp_event_init(); 5408 if (ret) 5409 goto qp_event_err; 5410 5411 mlx5_ib_odp_init(); 5412 ret = mlx5r_rep_init(); 5413 if (ret) 5414 goto rep_err; 5415 ret = mlx5_data_direct_driver_register(); 5416 if (ret) 5417 goto dd_err; 5418 ret = auxiliary_driver_register(&mlx5r_mp_driver); 5419 if (ret) 5420 goto mp_err; 5421 ret = auxiliary_driver_register(&mlx5r_driver); 5422 if (ret) 5423 goto drv_err; 5424 5425 return 0; 5426 5427 drv_err: 5428 auxiliary_driver_unregister(&mlx5r_mp_driver); 5429 mp_err: 5430 mlx5_data_direct_driver_unregister(); 5431 dd_err: 5432 mlx5r_rep_cleanup(); 5433 rep_err: 5434 mlx5_ib_qp_event_cleanup(); 5435 qp_event_err: 5436 destroy_workqueue(mlx5_ib_event_wq); 5437 free_page((unsigned long)xlt_emergency_page); 5438 return ret; 5439 } 5440 5441 static void __exit mlx5_ib_cleanup(void) 5442 { 5443 mlx5_data_direct_driver_unregister(); 5444 auxiliary_driver_unregister(&mlx5r_driver); 5445 auxiliary_driver_unregister(&mlx5r_mp_driver); 5446 mlx5r_rep_cleanup(); 5447 5448 mlx5_ib_qp_event_cleanup(); 5449 destroy_workqueue(mlx5_ib_event_wq); 5450 free_page((unsigned long)xlt_emergency_page); 5451 } 5452 5453 module_init(mlx5_ib_init); 5454 module_exit(mlx5_ib_cleanup); 5455