1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * drivers/ata/sata_dwc_460ex.c
4 *
5 * Synopsys DesignWare Cores (DWC) SATA host driver
6 *
7 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
8 *
9 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
10 * Copyright 2008 DENX Software Engineering
11 *
12 * Based on versions provided by AMCC and Synopsys which are:
13 * Copyright 2006 Applied Micro Circuits Corporation
14 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/dmaengine.h>
21 #include <linux/of.h>
22 #include <linux/platform_device.h>
23 #include <linux/phy/phy.h>
24 #include <linux/libata.h>
25 #include <linux/slab.h>
26 #include <trace/events/libata.h>
27
28 #include "libata.h"
29
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_cmnd.h>
32
33 /* These two are defined in "libata.h" */
34 #undef DRV_NAME
35 #undef DRV_VERSION
36
37 #define DRV_NAME "sata-dwc"
38 #define DRV_VERSION "1.3"
39
40 #define sata_dwc_writel(a, v) writel_relaxed(v, a)
41 #define sata_dwc_readl(a) readl_relaxed(a)
42
43 #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length */
44
45 enum {
46 SATA_DWC_MAX_PORTS = 1,
47
48 SATA_DWC_SCR_OFFSET = 0x24,
49 SATA_DWC_REG_OFFSET = 0x64,
50 };
51
52 /* DWC SATA Registers */
53 struct sata_dwc_regs {
54 u32 fptagr; /* 1st party DMA tag */
55 u32 fpbor; /* 1st party DMA buffer offset */
56 u32 fptcr; /* 1st party DMA Xfr count */
57 u32 dmacr; /* DMA Control */
58 u32 dbtsr; /* DMA Burst Transac size */
59 u32 intpr; /* Interrupt Pending */
60 u32 intmr; /* Interrupt Mask */
61 u32 errmr; /* Error Mask */
62 u32 llcr; /* Link Layer Control */
63 u32 phycr; /* PHY Control */
64 u32 physr; /* PHY Status */
65 u32 rxbistpd; /* Recvd BIST pattern def register */
66 u32 rxbistpd1; /* Recvd BIST data dword1 */
67 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
68 u32 txbistpd; /* Trans BIST pattern def register */
69 u32 txbistpd1; /* Trans BIST data dword1 */
70 u32 txbistpd2; /* Trans BIST data dword2 */
71 u32 bistcr; /* BIST Control Register */
72 u32 bistfctr; /* BIST FIS Count Register */
73 u32 bistsr; /* BIST Status Register */
74 u32 bistdecr; /* BIST Dword Error count register */
75 u32 res[15]; /* Reserved locations */
76 u32 testr; /* Test Register */
77 u32 versionr; /* Version Register */
78 u32 idr; /* ID Register */
79 u32 unimpl[192]; /* Unimplemented */
80 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
81 };
82
83 enum {
84 SCR_SCONTROL_DET_ENABLE = 0x00000001,
85 SCR_SSTATUS_DET_PRESENT = 0x00000001,
86 SCR_SERROR_DIAG_X = 0x04000000,
87 /* DWC SATA Register Operations */
88 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
89 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
90 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
91 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
92 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
93 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
94 SATA_DWC_INTPR_DMAT = 0x00000001,
95 SATA_DWC_INTPR_NEWFP = 0x00000002,
96 SATA_DWC_INTPR_PMABRT = 0x00000004,
97 SATA_DWC_INTPR_ERR = 0x00000008,
98 SATA_DWC_INTPR_NEWBIST = 0x00000010,
99 SATA_DWC_INTPR_IPF = 0x10000000,
100 SATA_DWC_INTMR_DMATM = 0x00000001,
101 SATA_DWC_INTMR_NEWFPM = 0x00000002,
102 SATA_DWC_INTMR_PMABRTM = 0x00000004,
103 SATA_DWC_INTMR_ERRM = 0x00000008,
104 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
105 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
106 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
107 SATA_DWC_LLCR_RPDEN = 0x00000004,
108 /* This is all error bits, zero's are reserved fields. */
109 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
110 };
111
112 #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
113 #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
114 SATA_DWC_DMACR_TMOD_TXCHEN)
115 #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
116 SATA_DWC_DMACR_TMOD_TXCHEN)
117 #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
118 #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
119 << 16)
120 struct sata_dwc_device {
121 struct device *dev; /* generic device struct */
122 struct ata_probe_ent *pe; /* ptr to probe-ent */
123 struct ata_host *host;
124 struct sata_dwc_regs __iomem *sata_dwc_regs; /* DW SATA specific */
125 u32 sactive_issued;
126 u32 sactive_queued;
127 struct phy *phy;
128 phys_addr_t dmadr;
129 #ifdef CONFIG_SATA_DWC_OLD_DMA
130 struct dw_dma_chip *dma;
131 #endif
132 };
133
134 /*
135 * Allow one extra special slot for commands and DMA management
136 * to account for libata internal commands.
137 */
138 #define SATA_DWC_QCMD_MAX (ATA_MAX_QUEUE + 1)
139
140 struct sata_dwc_device_port {
141 struct sata_dwc_device *hsdev;
142 int cmd_issued[SATA_DWC_QCMD_MAX];
143 int dma_pending[SATA_DWC_QCMD_MAX];
144
145 /* DMA info */
146 struct dma_chan *chan;
147 struct dma_async_tx_descriptor *desc[SATA_DWC_QCMD_MAX];
148 u32 dma_interrupt_count;
149 };
150
151 /*
152 * Commonly used DWC SATA driver macros
153 */
154 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)(host)->private_data)
155 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)(ap)->host->private_data)
156 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)(ap)->private_data)
157 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)(qc)->ap->host->private_data)
158 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)(p)->hsdev)
159
160 enum {
161 SATA_DWC_CMD_ISSUED_NOT = 0,
162 SATA_DWC_CMD_ISSUED_PEND = 1,
163 SATA_DWC_CMD_ISSUED_EXEC = 2,
164 SATA_DWC_CMD_ISSUED_NODATA = 3,
165
166 SATA_DWC_DMA_PENDING_NONE = 0,
167 SATA_DWC_DMA_PENDING_TX = 1,
168 SATA_DWC_DMA_PENDING_RX = 2,
169 };
170
171 /*
172 * Prototypes
173 */
174 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
175 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc);
176 static void sata_dwc_dma_xfer_complete(struct ata_port *ap);
177 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
178
179 #ifdef CONFIG_SATA_DWC_OLD_DMA
180
181 #include <linux/platform_data/dma-dw.h>
182 #include <linux/dma/dw.h>
183
184 static struct dw_dma_slave sata_dwc_dma_dws = {
185 .src_id = 0,
186 .dst_id = 0,
187 .m_master = 1,
188 .p_master = 0,
189 };
190
sata_dwc_dma_filter(struct dma_chan * chan,void * param)191 static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
192 {
193 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
194
195 if (dws->dma_dev != chan->device->dev)
196 return false;
197
198 chan->private = dws;
199 return true;
200 }
201
sata_dwc_dma_get_channel_old(struct sata_dwc_device_port * hsdevp)202 static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
203 {
204 struct sata_dwc_device *hsdev = hsdevp->hsdev;
205 struct dw_dma_slave *dws = &sata_dwc_dma_dws;
206 struct device *dev = hsdev->dev;
207 dma_cap_mask_t mask;
208
209 dws->dma_dev = dev;
210
211 dma_cap_zero(mask);
212 dma_cap_set(DMA_SLAVE, mask);
213
214 /* Acquire DMA channel */
215 hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
216 if (!hsdevp->chan) {
217 dev_err(dev, "%s: dma channel unavailable\n", __func__);
218 return -EAGAIN;
219 }
220
221 return 0;
222 }
223
sata_dwc_dma_init_old(struct platform_device * pdev,struct sata_dwc_device * hsdev)224 static int sata_dwc_dma_init_old(struct platform_device *pdev,
225 struct sata_dwc_device *hsdev)
226 {
227 struct device *dev = &pdev->dev;
228
229 hsdev->dma = devm_kzalloc(dev, sizeof(*hsdev->dma), GFP_KERNEL);
230 if (!hsdev->dma)
231 return -ENOMEM;
232
233 hsdev->dma->dev = dev;
234 hsdev->dma->id = pdev->id;
235
236 /* Get SATA DMA interrupt number */
237 hsdev->dma->irq = platform_get_irq(pdev, 1);
238 if (hsdev->dma->irq < 0)
239 return hsdev->dma->irq;
240
241 /* Get physical SATA DMA register base address */
242 hsdev->dma->regs = devm_platform_ioremap_resource(pdev, 1);
243 if (IS_ERR(hsdev->dma->regs))
244 return PTR_ERR(hsdev->dma->regs);
245
246 /* Initialize AHB DMAC */
247 return dw_dma_probe(hsdev->dma);
248 }
249
sata_dwc_dma_exit_old(struct sata_dwc_device * hsdev)250 static void sata_dwc_dma_exit_old(struct sata_dwc_device *hsdev)
251 {
252 if (!hsdev->dma)
253 return;
254
255 dw_dma_remove(hsdev->dma);
256 }
257
258 #endif
259
get_prot_descript(u8 protocol)260 static const char *get_prot_descript(u8 protocol)
261 {
262 switch (protocol) {
263 case ATA_PROT_NODATA:
264 return "ATA no data";
265 case ATA_PROT_PIO:
266 return "ATA PIO";
267 case ATA_PROT_DMA:
268 return "ATA DMA";
269 case ATA_PROT_NCQ:
270 return "ATA NCQ";
271 case ATA_PROT_NCQ_NODATA:
272 return "ATA NCQ no data";
273 case ATAPI_PROT_NODATA:
274 return "ATAPI no data";
275 case ATAPI_PROT_PIO:
276 return "ATAPI PIO";
277 case ATAPI_PROT_DMA:
278 return "ATAPI DMA";
279 default:
280 return "unknown";
281 }
282 }
283
dma_dwc_xfer_done(void * hsdev_instance)284 static void dma_dwc_xfer_done(void *hsdev_instance)
285 {
286 unsigned long flags;
287 struct sata_dwc_device *hsdev = hsdev_instance;
288 struct ata_host *host = (struct ata_host *)hsdev->host;
289 struct ata_port *ap;
290 struct sata_dwc_device_port *hsdevp;
291 u8 tag = 0;
292 unsigned int port = 0;
293
294 spin_lock_irqsave(&host->lock, flags);
295 ap = host->ports[port];
296 hsdevp = HSDEVP_FROM_AP(ap);
297 tag = ap->link.active_tag;
298
299 /*
300 * Each DMA command produces 2 interrupts. Only
301 * complete the command after both interrupts have been
302 * seen. (See sata_dwc_isr())
303 */
304 hsdevp->dma_interrupt_count++;
305 sata_dwc_clear_dmacr(hsdevp, tag);
306
307 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
308 dev_err(ap->dev, "DMA not pending tag=0x%02x pending=%d\n",
309 tag, hsdevp->dma_pending[tag]);
310 }
311
312 if ((hsdevp->dma_interrupt_count % 2) == 0)
313 sata_dwc_dma_xfer_complete(ap);
314
315 spin_unlock_irqrestore(&host->lock, flags);
316 }
317
dma_dwc_xfer_setup(struct ata_queued_cmd * qc)318 static struct dma_async_tx_descriptor *dma_dwc_xfer_setup(struct ata_queued_cmd *qc)
319 {
320 struct ata_port *ap = qc->ap;
321 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
322 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
323 struct dma_slave_config sconf;
324 struct dma_async_tx_descriptor *desc;
325
326 if (qc->dma_dir == DMA_DEV_TO_MEM) {
327 sconf.src_addr = hsdev->dmadr;
328 sconf.device_fc = false;
329 } else { /* DMA_MEM_TO_DEV */
330 sconf.dst_addr = hsdev->dmadr;
331 sconf.device_fc = false;
332 }
333
334 sconf.direction = qc->dma_dir;
335 sconf.src_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
336 sconf.dst_maxburst = AHB_DMA_BRST_DFLT / 4; /* in items */
337 sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
338 sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
339
340 dmaengine_slave_config(hsdevp->chan, &sconf);
341
342 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
343 desc = dmaengine_prep_slave_sg(hsdevp->chan, qc->sg, qc->n_elem,
344 qc->dma_dir,
345 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
346
347 if (!desc)
348 return NULL;
349
350 desc->callback = dma_dwc_xfer_done;
351 desc->callback_param = hsdev;
352
353 dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pa\n", __func__,
354 qc->sg, qc->n_elem, &hsdev->dmadr);
355
356 return desc;
357 }
358
sata_dwc_scr_read(struct ata_link * link,unsigned int scr,u32 * val)359 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
360 {
361 if (scr > SCR_NOTIFICATION) {
362 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
363 __func__, scr);
364 return -EINVAL;
365 }
366
367 *val = sata_dwc_readl(link->ap->ioaddr.scr_addr + (scr * 4));
368 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
369 link->ap->print_id, scr, *val);
370
371 return 0;
372 }
373
sata_dwc_scr_write(struct ata_link * link,unsigned int scr,u32 val)374 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
375 {
376 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
377 link->ap->print_id, scr, val);
378 if (scr > SCR_NOTIFICATION) {
379 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
380 __func__, scr);
381 return -EINVAL;
382 }
383 sata_dwc_writel(link->ap->ioaddr.scr_addr + (scr * 4), val);
384
385 return 0;
386 }
387
clear_serror(struct ata_port * ap)388 static void clear_serror(struct ata_port *ap)
389 {
390 u32 val;
391 sata_dwc_scr_read(&ap->link, SCR_ERROR, &val);
392 sata_dwc_scr_write(&ap->link, SCR_ERROR, val);
393 }
394
clear_interrupt_bit(struct sata_dwc_device * hsdev,u32 bit)395 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
396 {
397 sata_dwc_writel(&hsdev->sata_dwc_regs->intpr, bit);
398 }
399
qcmd_tag_to_mask(u8 tag)400 static u32 qcmd_tag_to_mask(u8 tag)
401 {
402 return 0x00000001 << (tag & 0x1f);
403 }
404
405 /* See ahci.c */
sata_dwc_error_intr(struct ata_port * ap,struct sata_dwc_device * hsdev,uint intpr)406 static void sata_dwc_error_intr(struct ata_port *ap,
407 struct sata_dwc_device *hsdev, uint intpr)
408 {
409 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
410 struct ata_eh_info *ehi = &ap->link.eh_info;
411 unsigned int err_mask = 0, action = 0;
412 struct ata_queued_cmd *qc;
413 u32 serror;
414 u8 status, tag;
415
416 ata_ehi_clear_desc(ehi);
417
418 sata_dwc_scr_read(&ap->link, SCR_ERROR, &serror);
419 status = ap->ops->sff_check_status(ap);
420
421 tag = ap->link.active_tag;
422
423 dev_err(ap->dev,
424 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
425 __func__, serror, intpr, status, hsdevp->dma_interrupt_count,
426 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]);
427
428 /* Clear error register and interrupt bit */
429 clear_serror(ap);
430 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
431
432 /* This is the only error happening now. TODO check for exact error */
433
434 err_mask |= AC_ERR_HOST_BUS;
435 action |= ATA_EH_RESET;
436
437 /* Pass this on to EH */
438 ehi->serror |= serror;
439 ehi->action |= action;
440
441 qc = ata_qc_from_tag(ap, tag);
442 if (qc)
443 qc->err_mask |= err_mask;
444 else
445 ehi->err_mask |= err_mask;
446
447 ata_port_abort(ap);
448 }
449
450 /*
451 * Function : sata_dwc_isr
452 * arguments : irq, void *dev_instance, struct pt_regs *regs
453 * Return value : irqreturn_t - status of IRQ
454 * This Interrupt handler called via port ops registered function.
455 * .irq_handler = sata_dwc_isr
456 */
sata_dwc_isr(int irq,void * dev_instance)457 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
458 {
459 struct ata_host *host = (struct ata_host *)dev_instance;
460 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
461 struct ata_port *ap;
462 struct ata_queued_cmd *qc;
463 unsigned long flags;
464 u8 status, tag;
465 int handled, port = 0;
466 uint intpr, sactive, sactive2, tag_mask;
467 struct sata_dwc_device_port *hsdevp;
468 hsdev->sactive_issued = 0;
469
470 spin_lock_irqsave(&host->lock, flags);
471
472 /* Read the interrupt register */
473 intpr = sata_dwc_readl(&hsdev->sata_dwc_regs->intpr);
474
475 ap = host->ports[port];
476 hsdevp = HSDEVP_FROM_AP(ap);
477
478 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
479 ap->link.active_tag);
480
481 /* Check for error interrupt */
482 if (intpr & SATA_DWC_INTPR_ERR) {
483 sata_dwc_error_intr(ap, hsdev, intpr);
484 handled = 1;
485 goto DONE;
486 }
487
488 /* Check for DMA SETUP FIS (FP DMA) interrupt */
489 if (intpr & SATA_DWC_INTPR_NEWFP) {
490 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
491
492 tag = (u8)(sata_dwc_readl(&hsdev->sata_dwc_regs->fptagr));
493 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
494 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
495 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
496
497 hsdev->sactive_issued |= qcmd_tag_to_mask(tag);
498
499 qc = ata_qc_from_tag(ap, tag);
500 if (unlikely(!qc)) {
501 dev_err(ap->dev, "failed to get qc");
502 handled = 1;
503 goto DONE;
504 }
505 /*
506 * Start FP DMA for NCQ command. At this point the tag is the
507 * active tag. It is the tag that matches the command about to
508 * be completed.
509 */
510 trace_ata_bmdma_start(ap, &qc->tf, tag);
511 qc->ap->link.active_tag = tag;
512 sata_dwc_bmdma_start_by_tag(qc, tag);
513
514 handled = 1;
515 goto DONE;
516 }
517 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
518 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
519
520 /* If no sactive issued and tag_mask is zero then this is not NCQ */
521 if (hsdev->sactive_issued == 0 && tag_mask == 0) {
522 if (ap->link.active_tag == ATA_TAG_POISON)
523 tag = 0;
524 else
525 tag = ap->link.active_tag;
526 qc = ata_qc_from_tag(ap, tag);
527
528 /* DEV interrupt w/ no active qc? */
529 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
530 dev_err(ap->dev,
531 "%s interrupt with no active qc qc=%p\n",
532 __func__, qc);
533 ap->ops->sff_check_status(ap);
534 handled = 1;
535 goto DONE;
536 }
537 status = ap->ops->sff_check_status(ap);
538
539 qc->ap->link.active_tag = tag;
540 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
541
542 if (status & ATA_ERR) {
543 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
544 sata_dwc_qc_complete(ap, qc);
545 handled = 1;
546 goto DONE;
547 }
548
549 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
550 __func__, get_prot_descript(qc->tf.protocol));
551 DRVSTILLBUSY:
552 if (ata_is_dma(qc->tf.protocol)) {
553 /*
554 * Each DMA transaction produces 2 interrupts. The DMAC
555 * transfer complete interrupt and the SATA controller
556 * operation done interrupt. The command should be
557 * completed only after both interrupts are seen.
558 */
559 hsdevp->dma_interrupt_count++;
560 if (hsdevp->dma_pending[tag] == \
561 SATA_DWC_DMA_PENDING_NONE) {
562 dev_err(ap->dev,
563 "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
564 __func__, intpr, status,
565 hsdevp->dma_pending[tag]);
566 }
567
568 if ((hsdevp->dma_interrupt_count % 2) == 0)
569 sata_dwc_dma_xfer_complete(ap);
570 } else if (ata_is_pio(qc->tf.protocol)) {
571 ata_sff_hsm_move(ap, qc, status, 0);
572 handled = 1;
573 goto DONE;
574 } else {
575 if (unlikely(sata_dwc_qc_complete(ap, qc)))
576 goto DRVSTILLBUSY;
577 }
578
579 handled = 1;
580 goto DONE;
581 }
582
583 /*
584 * This is a NCQ command. At this point we need to figure out for which
585 * tags we have gotten a completion interrupt. One interrupt may serve
586 * as completion for more than one operation when commands are queued
587 * (NCQ). We need to process each completed command.
588 */
589
590 /* process completed commands */
591 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
592 tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
593
594 if (sactive != 0 || hsdev->sactive_issued > 1 || tag_mask > 1) {
595 dev_dbg(ap->dev,
596 "%s NCQ:sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
597 __func__, sactive, hsdev->sactive_issued, tag_mask);
598 }
599
600 if ((tag_mask | hsdev->sactive_issued) != hsdev->sactive_issued) {
601 dev_warn(ap->dev,
602 "Bad tag mask? sactive=0x%08x sactive_issued=0x%08x tag_mask=0x%08x\n",
603 sactive, hsdev->sactive_issued, tag_mask);
604 }
605
606 /* read just to clear ... not bad if currently still busy */
607 status = ap->ops->sff_check_status(ap);
608 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
609
610 while (tag_mask) {
611 tag = __ffs(tag_mask);
612 tag_mask &= ~(1U << tag);
613 qc = ata_qc_from_tag(ap, tag);
614 if (unlikely(!qc)) {
615 dev_err(ap->dev, "failed to get qc");
616 handled = 1;
617 goto DONE;
618 }
619
620 /* To be picked up by completion functions */
621 qc->ap->link.active_tag = tag;
622 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
623
624 /* Let libata/scsi layers handle error */
625 if (status & ATA_ERR) {
626 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
627 status);
628 sata_dwc_qc_complete(ap, qc);
629 handled = 1;
630 goto DONE;
631 }
632
633 /* Process completed command */
634 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
635 get_prot_descript(qc->tf.protocol));
636 if (ata_is_dma(qc->tf.protocol)) {
637 hsdevp->dma_interrupt_count++;
638 if (hsdevp->dma_pending[tag] == \
639 SATA_DWC_DMA_PENDING_NONE)
640 dev_warn(ap->dev, "%s: DMA not pending?\n",
641 __func__);
642 if ((hsdevp->dma_interrupt_count % 2) == 0)
643 sata_dwc_dma_xfer_complete(ap);
644 } else {
645 if (unlikely(sata_dwc_qc_complete(ap, qc)))
646 goto STILLBUSY;
647 }
648 continue;
649
650 STILLBUSY:
651 ap->stats.idle_irq++;
652 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
653 ap->print_id);
654 } /* while tag_mask */
655
656 /*
657 * Check to see if any commands completed while we were processing our
658 * initial set of completed commands (read status clears interrupts,
659 * so we might miss a completed command interrupt if one came in while
660 * we were processing --we read status as part of processing a completed
661 * command).
662 */
663 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive2);
664 if (sactive2 != sactive) {
665 dev_dbg(ap->dev,
666 "More completed - sactive=0x%x sactive2=0x%x\n",
667 sactive, sactive2);
668 }
669 handled = 1;
670
671 DONE:
672 spin_unlock_irqrestore(&host->lock, flags);
673 return IRQ_RETVAL(handled);
674 }
675
sata_dwc_clear_dmacr(struct sata_dwc_device_port * hsdevp,u8 tag)676 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
677 {
678 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
679 u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr);
680
681 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
682 dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr);
683 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
684 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
685 dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr);
686 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
687 } else {
688 /*
689 * This should not happen, it indicates the driver is out of
690 * sync. If it does happen, clear dmacr anyway.
691 */
692 dev_err(hsdev->dev,
693 "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
694 __func__, tag, hsdevp->dma_pending[tag], dmacr);
695 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
696 SATA_DWC_DMACR_TXRXCH_CLEAR);
697 }
698 }
699
sata_dwc_dma_xfer_complete(struct ata_port * ap)700 static void sata_dwc_dma_xfer_complete(struct ata_port *ap)
701 {
702 struct ata_queued_cmd *qc;
703 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
704 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
705 u8 tag = 0;
706
707 tag = ap->link.active_tag;
708 qc = ata_qc_from_tag(ap, tag);
709 if (!qc) {
710 dev_err(ap->dev, "failed to get qc");
711 return;
712 }
713
714 if (ata_is_dma(qc->tf.protocol)) {
715 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
716 dev_err(ap->dev,
717 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
718 __func__,
719 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
720 }
721
722 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
723 sata_dwc_qc_complete(ap, qc);
724 ap->link.active_tag = ATA_TAG_POISON;
725 } else {
726 sata_dwc_qc_complete(ap, qc);
727 }
728 }
729
sata_dwc_qc_complete(struct ata_port * ap,struct ata_queued_cmd * qc)730 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc)
731 {
732 u8 status = 0;
733 u32 mask = 0x0;
734 u8 tag = qc->hw_tag;
735 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
736 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
737 hsdev->sactive_queued = 0;
738
739 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
740 dev_err(ap->dev, "TX DMA PENDING\n");
741 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
742 dev_err(ap->dev, "RX DMA PENDING\n");
743 dev_dbg(ap->dev,
744 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
745 qc->tf.command, status, ap->print_id, qc->tf.protocol);
746
747 /* clear active bit */
748 mask = (~(qcmd_tag_to_mask(tag)));
749 hsdev->sactive_queued = hsdev->sactive_queued & mask;
750 hsdev->sactive_issued = hsdev->sactive_issued & mask;
751 ata_qc_complete(qc);
752 return 0;
753 }
754
sata_dwc_enable_interrupts(struct sata_dwc_device * hsdev)755 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
756 {
757 /* Enable selective interrupts by setting the interrupt maskregister*/
758 sata_dwc_writel(&hsdev->sata_dwc_regs->intmr,
759 SATA_DWC_INTMR_ERRM |
760 SATA_DWC_INTMR_NEWFPM |
761 SATA_DWC_INTMR_PMABRTM |
762 SATA_DWC_INTMR_DMATM);
763 /*
764 * Unmask the error bits that should trigger an error interrupt by
765 * setting the error mask register.
766 */
767 sata_dwc_writel(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
768
769 dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
770 __func__, sata_dwc_readl(&hsdev->sata_dwc_regs->intmr),
771 sata_dwc_readl(&hsdev->sata_dwc_regs->errmr));
772 }
773
sata_dwc_setup_port(struct ata_ioports * port,void __iomem * base)774 static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base)
775 {
776 port->cmd_addr = base + 0x00;
777 port->data_addr = base + 0x00;
778
779 port->error_addr = base + 0x04;
780 port->feature_addr = base + 0x04;
781
782 port->nsect_addr = base + 0x08;
783
784 port->lbal_addr = base + 0x0c;
785 port->lbam_addr = base + 0x10;
786 port->lbah_addr = base + 0x14;
787
788 port->device_addr = base + 0x18;
789 port->command_addr = base + 0x1c;
790 port->status_addr = base + 0x1c;
791
792 port->altstatus_addr = base + 0x20;
793 port->ctl_addr = base + 0x20;
794 }
795
sata_dwc_dma_get_channel(struct sata_dwc_device_port * hsdevp)796 static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp)
797 {
798 struct sata_dwc_device *hsdev = hsdevp->hsdev;
799 struct device *dev = hsdev->dev;
800
801 #ifdef CONFIG_SATA_DWC_OLD_DMA
802 if (!of_property_present(dev->of_node, "dmas"))
803 return sata_dwc_dma_get_channel_old(hsdevp);
804 #endif
805
806 hsdevp->chan = dma_request_chan(dev, "sata-dma");
807 if (IS_ERR(hsdevp->chan)) {
808 dev_err(dev, "failed to allocate dma channel: %ld\n",
809 PTR_ERR(hsdevp->chan));
810 return PTR_ERR(hsdevp->chan);
811 }
812
813 return 0;
814 }
815
816 /*
817 * Function : sata_dwc_port_start
818 * arguments : struct ata_ioports *port
819 * Return value : returns 0 if success, error code otherwise
820 * This function allocates the scatter gather LLI table for AHB DMA
821 */
sata_dwc_port_start(struct ata_port * ap)822 static int sata_dwc_port_start(struct ata_port *ap)
823 {
824 int err = 0;
825 struct sata_dwc_device *hsdev;
826 struct sata_dwc_device_port *hsdevp = NULL;
827 struct device *pdev;
828 int i;
829
830 hsdev = HSDEV_FROM_AP(ap);
831
832 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
833
834 hsdev->host = ap->host;
835 pdev = ap->host->dev;
836 if (!pdev) {
837 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
838 err = -ENODEV;
839 goto CLEANUP;
840 }
841
842 /* Allocate Port Struct */
843 hsdevp = kzalloc_obj(*hsdevp);
844 if (!hsdevp) {
845 err = -ENOMEM;
846 goto CLEANUP;
847 }
848 hsdevp->hsdev = hsdev;
849
850 err = sata_dwc_dma_get_channel(hsdevp);
851 if (err)
852 goto CLEANUP_ALLOC;
853
854 err = phy_power_on(hsdev->phy);
855 if (err)
856 goto CLEANUP_ALLOC;
857
858 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
859 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
860
861 ap->bmdma_prd = NULL; /* set these so libata doesn't use them */
862 ap->bmdma_prd_dma = 0;
863
864 if (ap->port_no == 0) {
865 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
866 __func__);
867 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
868 SATA_DWC_DMACR_TXRXCH_CLEAR);
869
870 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
871 __func__);
872 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
873 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
874 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
875 }
876
877 /* Clear any error bits before libata starts issuing commands */
878 clear_serror(ap);
879 ap->private_data = hsdevp;
880 dev_dbg(ap->dev, "%s: done\n", __func__);
881 return 0;
882
883 CLEANUP_ALLOC:
884 kfree(hsdevp);
885 CLEANUP:
886 dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
887 return err;
888 }
889
sata_dwc_port_stop(struct ata_port * ap)890 static void sata_dwc_port_stop(struct ata_port *ap)
891 {
892 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
893 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
894
895 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
896
897 dmaengine_terminate_sync(hsdevp->chan);
898 dma_release_channel(hsdevp->chan);
899 phy_power_off(hsdev->phy);
900
901 kfree(hsdevp);
902 ap->private_data = NULL;
903 }
904
905 /*
906 * Function : sata_dwc_exec_command_by_tag
907 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
908 * Return value : None
909 * This function keeps track of individual command tag ids and calls
910 * ata_exec_command in libata
911 */
sata_dwc_exec_command_by_tag(struct ata_port * ap,struct ata_taskfile * tf,u8 tag,u32 cmd_issued)912 static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
913 struct ata_taskfile *tf,
914 u8 tag, u32 cmd_issued)
915 {
916 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
917
918 hsdevp->cmd_issued[tag] = cmd_issued;
919
920 /*
921 * Clear SError before executing a new command.
922 * sata_dwc_scr_write and read can not be used here. Clearing the PM
923 * managed SError register for the disk needs to be done before the
924 * task file is loaded.
925 */
926 clear_serror(ap);
927 ata_sff_exec_command(ap, tf);
928 }
929
sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd * qc,u8 tag)930 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
931 {
932 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
933 SATA_DWC_CMD_ISSUED_PEND);
934 }
935
sata_dwc_bmdma_setup(struct ata_queued_cmd * qc)936 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
937 {
938 u8 tag = qc->hw_tag;
939
940 if (!ata_is_ncq(qc->tf.protocol))
941 tag = 0;
942
943 sata_dwc_bmdma_setup_by_tag(qc, tag);
944 }
945
sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd * qc,u8 tag)946 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
947 {
948 int start_dma;
949 u32 reg;
950 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
951 struct ata_port *ap = qc->ap;
952 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
953 struct dma_async_tx_descriptor *desc = hsdevp->desc[tag];
954 int dir = qc->dma_dir;
955
956 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
957 start_dma = 1;
958 if (dir == DMA_TO_DEVICE)
959 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
960 else
961 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
962 } else {
963 dev_err(ap->dev,
964 "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
965 __func__, hsdevp->cmd_issued[tag], tag);
966 start_dma = 0;
967 }
968
969 if (start_dma) {
970 sata_dwc_scr_read(&ap->link, SCR_ERROR, ®);
971 if (reg & SATA_DWC_SERROR_ERR_BITS) {
972 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
973 __func__, reg);
974 }
975
976 if (dir == DMA_TO_DEVICE)
977 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
978 SATA_DWC_DMACR_TXCHEN);
979 else
980 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
981 SATA_DWC_DMACR_RXCHEN);
982
983 /* Enable AHB DMA transfer on the specified channel */
984 dmaengine_submit(desc);
985 dma_async_issue_pending(hsdevp->chan);
986 }
987 }
988
sata_dwc_bmdma_start(struct ata_queued_cmd * qc)989 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
990 {
991 u8 tag = qc->hw_tag;
992
993 if (!ata_is_ncq(qc->tf.protocol))
994 tag = 0;
995
996 sata_dwc_bmdma_start_by_tag(qc, tag);
997 }
998
sata_dwc_qc_issue(struct ata_queued_cmd * qc)999 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1000 {
1001 u32 sactive;
1002 u8 tag = qc->hw_tag;
1003 struct ata_port *ap = qc->ap;
1004 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1005
1006 if (!ata_is_ncq(qc->tf.protocol))
1007 tag = 0;
1008
1009 if (ata_is_dma(qc->tf.protocol)) {
1010 hsdevp->desc[tag] = dma_dwc_xfer_setup(qc);
1011 if (!hsdevp->desc[tag])
1012 return AC_ERR_SYSTEM;
1013 } else {
1014 hsdevp->desc[tag] = NULL;
1015 }
1016
1017 if (ata_is_ncq(qc->tf.protocol)) {
1018 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
1019 sactive |= (0x00000001 << tag);
1020 sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive);
1021
1022 trace_ata_tf_load(ap, &qc->tf);
1023 ap->ops->sff_tf_load(ap, &qc->tf);
1024 trace_ata_exec_command(ap, &qc->tf, tag);
1025 sata_dwc_exec_command_by_tag(ap, &qc->tf, tag,
1026 SATA_DWC_CMD_ISSUED_PEND);
1027 } else {
1028 return ata_bmdma_qc_issue(qc);
1029 }
1030 return 0;
1031 }
1032
sata_dwc_error_handler(struct ata_port * ap)1033 static void sata_dwc_error_handler(struct ata_port *ap)
1034 __must_hold(&ap->host->eh_mutex)
1035 {
1036 ata_sff_error_handler(ap);
1037 }
1038
sata_dwc_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)1039 static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1040 unsigned long deadline)
1041 {
1042 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1043 int ret;
1044
1045 ret = sata_sff_hardreset(link, class, deadline);
1046
1047 sata_dwc_enable_interrupts(hsdev);
1048
1049 /* Reconfigure the DMA control register */
1050 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1051 SATA_DWC_DMACR_TXRXCH_CLEAR);
1052
1053 /* Reconfigure the DMA Burst Transaction Size register */
1054 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
1055 SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1056 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1057
1058 return ret;
1059 }
1060
sata_dwc_dev_select(struct ata_port * ap,unsigned int device)1061 static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device)
1062 {
1063 /* SATA DWC is master only */
1064 }
1065
1066 /*
1067 * scsi mid-layer and libata interface structures
1068 */
1069 static const struct scsi_host_template sata_dwc_sht = {
1070 ATA_NCQ_SHT(DRV_NAME),
1071 /*
1072 * test-only: Currently this driver doesn't handle NCQ
1073 * correctly. We enable NCQ but set the queue depth to a
1074 * max of 1. This will get fixed in in a future release.
1075 */
1076 .sg_tablesize = LIBATA_MAX_PRD,
1077 /* .can_queue = ATA_MAX_QUEUE, */
1078 /*
1079 * Make sure a LLI block is not created that will span 8K max FIS
1080 * boundary. If the block spans such a FIS boundary, there is a chance
1081 * that a DMA burst will cross that boundary -- this results in an
1082 * error in the host controller.
1083 */
1084 .dma_boundary = 0x1fff /* ATA_DMA_BOUNDARY */,
1085 };
1086
1087 static struct ata_port_operations sata_dwc_ops = {
1088 .inherits = &ata_sff_port_ops,
1089
1090 .error_handler = sata_dwc_error_handler,
1091 .reset.hardreset = sata_dwc_hardreset,
1092
1093 .qc_issue = sata_dwc_qc_issue,
1094
1095 .scr_read = sata_dwc_scr_read,
1096 .scr_write = sata_dwc_scr_write,
1097
1098 .port_start = sata_dwc_port_start,
1099 .port_stop = sata_dwc_port_stop,
1100
1101 .sff_dev_select = sata_dwc_dev_select,
1102
1103 .bmdma_setup = sata_dwc_bmdma_setup,
1104 .bmdma_start = sata_dwc_bmdma_start,
1105 };
1106
1107 static const struct ata_port_info sata_dwc_port_info[] = {
1108 {
1109 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
1110 .pio_mask = ATA_PIO4,
1111 .udma_mask = ATA_UDMA6,
1112 .port_ops = &sata_dwc_ops,
1113 },
1114 };
1115
sata_dwc_probe(struct platform_device * ofdev)1116 static int sata_dwc_probe(struct platform_device *ofdev)
1117 {
1118 struct device *dev = &ofdev->dev;
1119 struct sata_dwc_device *hsdev;
1120 u32 idr, versionr;
1121 char *ver = (char *)&versionr;
1122 void __iomem *base;
1123 int err = 0;
1124 int irq;
1125 struct ata_host *host;
1126 struct ata_port_info pi = sata_dwc_port_info[0];
1127 const struct ata_port_info *ppi[] = { &pi, NULL };
1128 struct resource *res;
1129
1130 /* Allocate DWC SATA device */
1131 host = ata_host_alloc_pinfo(dev, ppi, SATA_DWC_MAX_PORTS);
1132 hsdev = devm_kzalloc(dev, sizeof(*hsdev), GFP_KERNEL);
1133 if (!host || !hsdev)
1134 return -ENOMEM;
1135
1136 host->private_data = hsdev;
1137
1138 /* Ioremap SATA registers */
1139 base = devm_platform_get_and_ioremap_resource(ofdev, 0, &res);
1140 if (IS_ERR(base))
1141 return PTR_ERR(base);
1142 dev_dbg(dev, "ioremap done for SATA register address\n");
1143
1144 /* Synopsys DWC SATA specific Registers */
1145 hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET;
1146 hsdev->dmadr = res->start + SATA_DWC_REG_OFFSET + offsetof(struct sata_dwc_regs, dmadr);
1147
1148 /* Setup port */
1149 host->ports[0]->ioaddr.cmd_addr = base;
1150 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1151 sata_dwc_setup_port(&host->ports[0]->ioaddr, base);
1152
1153 /* Read the ID and Version Registers */
1154 idr = sata_dwc_readl(&hsdev->sata_dwc_regs->idr);
1155 versionr = sata_dwc_readl(&hsdev->sata_dwc_regs->versionr);
1156 dev_notice(dev, "id %d, controller version %c.%c%c\n", idr, ver[0], ver[1], ver[2]);
1157
1158 /* Save dev for later use in dev_xxx() routines */
1159 hsdev->dev = dev;
1160
1161 /* Get SATA interrupt number */
1162 irq = platform_get_irq(ofdev, 0);
1163 if (irq < 0)
1164 return irq;
1165
1166 #ifdef CONFIG_SATA_DWC_OLD_DMA
1167 if (!of_property_present(dev->of_node, "dmas")) {
1168 err = sata_dwc_dma_init_old(ofdev, hsdev);
1169 if (err)
1170 return err;
1171 }
1172 #endif
1173
1174 hsdev->phy = devm_phy_optional_get(dev, "sata-phy");
1175 if (IS_ERR(hsdev->phy))
1176 return PTR_ERR(hsdev->phy);
1177
1178 err = phy_init(hsdev->phy);
1179 if (err)
1180 goto error_out;
1181
1182 /*
1183 * Now, register with libATA core, this will also initiate the
1184 * device discovery process, invoking our port_start() handler &
1185 * error_handler() to execute a dummy Softreset EH session
1186 */
1187 err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1188 if (err)
1189 dev_err(dev, "failed to activate host");
1190
1191 /* Enable SATA Interrupts */
1192 sata_dwc_enable_interrupts(hsdev);
1193 return 0;
1194
1195 error_out:
1196 phy_exit(hsdev->phy);
1197 return err;
1198 }
1199
sata_dwc_remove(struct platform_device * ofdev)1200 static void sata_dwc_remove(struct platform_device *ofdev)
1201 {
1202 struct device *dev = &ofdev->dev;
1203 struct ata_host *host = dev_get_drvdata(dev);
1204 struct sata_dwc_device *hsdev = host->private_data;
1205
1206 ata_host_detach(host);
1207
1208 phy_exit(hsdev->phy);
1209
1210 #ifdef CONFIG_SATA_DWC_OLD_DMA
1211 /* Free SATA DMA resources */
1212 sata_dwc_dma_exit_old(hsdev);
1213 #endif
1214
1215 dev_dbg(dev, "done\n");
1216 }
1217
1218 static const struct of_device_id sata_dwc_match[] = {
1219 { .compatible = "amcc,sata-460ex", },
1220 {}
1221 };
1222 MODULE_DEVICE_TABLE(of, sata_dwc_match);
1223
1224 static struct platform_driver sata_dwc_driver = {
1225 .driver = {
1226 .name = DRV_NAME,
1227 .of_match_table = sata_dwc_match,
1228 },
1229 .probe = sata_dwc_probe,
1230 .remove = sata_dwc_remove,
1231 };
1232
1233 module_platform_driver(sata_dwc_driver);
1234
1235 MODULE_LICENSE("GPL");
1236 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1237 MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
1238 MODULE_VERSION(DRV_VERSION);
1239