1 /* 2 * Copyright 2012-2026 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "dc_probe.h" 33 #include "grph_object_defs.h" 34 #include "logger_types.h" 35 #include "hdcp_msg_types.h" 36 #include "gpio_types.h" 37 #include "link_service_types.h" 38 #include "grph_object_ctrl_defs.h" 39 #include <inc/hw/opp.h> 40 #include <inc/hw/rmcm.h> 41 42 #include "hwss/hw_sequencer.h" 43 #include "inc/compressor.h" 44 #include "inc/hw/dmcu.h" 45 #include "dml/display_mode_lib.h" 46 47 #include "dml2_wrapper/dml2_wrapper.h" 48 49 #include "dmub/inc/dmub_cmd.h" 50 51 #include "dml/dml1_frl_cap_chk.h" 52 53 #include "sspl/dc_spl_types.h" 54 #include "inc/dc_core_interface.h" 55 56 struct abm_save_restore; 57 58 /* forward declaration */ 59 struct aux_payload; 60 struct set_config_cmd_payload; 61 struct dmub_notification; 62 struct dcn_hubbub_reg_state; 63 struct dcn_hubp_reg_state; 64 struct dcn_dpp_reg_state; 65 struct dcn_mpc_reg_state; 66 struct dcn_opp_reg_state; 67 struct dcn_dsc_reg_state; 68 struct dcn_optc_reg_state; 69 struct dcn_dccg_reg_state; 70 71 #define DC_VER "3.2.401" 72 73 /** 74 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC 75 */ 76 #define MAX_SURFACES 4 77 /** 78 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW 79 */ 80 #define MAX_PLANES 6 81 #define MAX_STREAMS 6 82 #define MIN_VIEWPORT_SIZE 12 83 #define MAX_NUM_EDP 2 84 #define MAX_SUPPORTED_FORMATS 7 85 86 #define MAX_HOST_ROUTERS_NUM 3 87 #define MAX_DPIA_PER_HOST_ROUTER 3 88 #define MAX_DPIA_NUM (MAX_HOST_ROUTERS_NUM * MAX_DPIA_PER_HOST_ROUTER) 89 90 #define NUM_FAST_FLIPS_TO_STEADY_STATE 20 91 92 struct frl_cap_chk_intermediates_fixed31_32 { 93 int c_frl_sb; 94 struct fixed31_32 overhead_sb; 95 struct fixed31_32 overhead_rs; 96 struct fixed31_32 overhead_map; 97 struct fixed31_32 overhead_min; 98 struct fixed31_32 overhead_max; 99 struct fixed31_32 f_pixel_clock_max; 100 struct fixed31_32 t_line; 101 struct fixed31_32 r_bit_min; 102 struct fixed31_32 r_frl_char_min; 103 struct fixed31_32 c_frl_line; 104 struct fixed31_32 ap; 105 struct fixed31_32 r_ap; 106 struct fixed31_32 avg_audio_packets_line; 107 struct fixed31_32 margin; 108 int audio_packets_line; 109 int blank_audio_min; 110 }; 111 112 struct frl_cap_chk_params_fixed31_32 { 113 int lanes; 114 struct fixed31_32 f_pixel_clock_nominal; /* Pixel Clock rate (Hz) */ 115 struct fixed31_32 r_bit_nominal; /* FRL bitrate (bps) */ 116 unsigned int audio_packet_type; 117 struct fixed31_32 f_audio; /* Audio rate (Hz) */ 118 uint32_t h_active; /* Active pixels per line */ 119 uint32_t h_blank; /* Blanking pixels per line */ 120 int bpc; /* Bits per component */ 121 int vic; /* Video Identification Code */ 122 123 enum hdmi_frl_pixel_encoding pixel_encoding; 124 125 bool compressed; /* set to true if DSC is enabled */ 126 bool bypass_hc_target_calc; /* debug only */ 127 bool allow_all_bpp; /* dsc_all_bpp */ 128 129 /* DSC parameters */ 130 int slices; 131 int slice_width; 132 struct fixed31_32 bpp_target; 133 int layout; 134 int acat; /* not supported */ 135 136 /* outputs */ 137 struct frl_dml_borrow_params borrow_params; 138 int average_tribyte_rate; 139 }; 140 141 /* Display Core Interfaces */ 142 struct dc_versions { 143 const char *dc_ver; 144 struct dmcu_version dmcu_version; 145 }; 146 147 enum dp_protocol_version { 148 DP_VERSION_1_4 = 0, 149 DP_VERSION_2_1, 150 DP_VERSION_UNKNOWN, 151 }; 152 153 enum dc_plane_type { 154 DC_PLANE_TYPE_INVALID, 155 DC_PLANE_TYPE_DCE_RGB, 156 DC_PLANE_TYPE_DCE_UNDERLAY, 157 DC_PLANE_TYPE_DCN_UNIVERSAL, 158 }; 159 160 // Sizes defined as multiples of 64KB 161 enum det_size { 162 DET_SIZE_DEFAULT = 0, 163 DET_SIZE_192KB = 3, 164 DET_SIZE_256KB = 4, 165 DET_SIZE_320KB = 5, 166 DET_SIZE_384KB = 6 167 }; 168 169 170 struct dc_plane_cap { 171 enum dc_plane_type type; 172 uint32_t per_pixel_alpha : 1; 173 struct { 174 uint32_t argb8888 : 1; 175 uint32_t nv12 : 1; 176 uint32_t fp16 : 1; 177 uint32_t p010 : 1; 178 uint32_t ayuv : 1; 179 uint32_t yuy2 : 1; // Packed 422 8bpc 180 uint32_t y210 : 1; // Packed 422 10bpc 181 uint32_t y212 : 1; // Packed 422 12bpc 182 uint32_t p208 : 1; // Planar 422 8bpc 183 uint32_t p210 : 1; // Planar 422 10bpc 184 uint32_t p212 : 1; // Planar 422 12bpc 185 /* Not all caps will be used/supported */ 186 } pixel_format_support; 187 // max upscaling factor x1000 188 // upscaling factors are always >= 1 189 // for example, 1080p -> 8K is 4.0, or 4000 raw value 190 struct { 191 uint32_t argb8888; 192 uint32_t nv12; 193 uint32_t fp16; 194 } max_upscale_factor; 195 // max downscale factor x1000 196 // downscale factors are always <= 1 197 // for example, 8K -> 1080p is 0.25, or 250 raw value 198 struct { 199 uint32_t argb8888; 200 uint32_t nv12; 201 uint32_t fp16; 202 } max_downscale_factor; 203 // minimal width/height 204 uint32_t min_width; 205 uint32_t min_height; 206 }; 207 208 /** 209 * DOC: color-management-caps 210 * 211 * **Color management caps (DPP and MPC)** 212 * 213 * Modules/color calculates various color operations which are translated to 214 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 215 * DCN1, every new generation comes with fairly major differences in color 216 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 217 * decide mapping to HW block based on logical capabilities. 218 */ 219 220 /** 221 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 222 * @srgb: RGB color space transfer func 223 * @bt2020: BT.2020 transfer func 224 * @gamma2_2: standard gamma 225 * @pq: perceptual quantizer transfer function 226 * @hlg: hybrid log–gamma transfer function 227 */ 228 struct rom_curve_caps { 229 uint16_t srgb : 1; 230 uint16_t bt2020 : 1; 231 uint16_t gamma2_2 : 1; 232 uint16_t pq : 1; 233 uint16_t hlg : 1; 234 }; 235 236 /** 237 * struct dpp_color_caps - color pipeline capabilities for display pipe and 238 * plane blocks 239 * 240 * @dcn_arch: all DCE generations treated the same 241 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 242 * just plain 256-entry lookup 243 * @icsc: input color space conversion 244 * @dgam_ram: programmable degamma LUT 245 * @post_csc: post color space conversion, before gamut remap 246 * @gamma_corr: degamma correction 247 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 248 * with MPC by setting mpc:shared_3d_lut flag 249 * @ogam_ram: programmable out/blend gamma LUT 250 * @ocsc: output color space conversion 251 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 252 * @upsp_pre_scaler: Ability to upsample 420/422 before scaling 253 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 254 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 255 * 256 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 257 */ 258 struct dpp_color_caps { 259 uint16_t dcn_arch : 1; 260 uint16_t input_lut_shared : 1; 261 uint16_t icsc : 1; 262 uint16_t dgam_ram : 1; 263 uint16_t post_csc : 1; 264 uint16_t gamma_corr : 1; 265 uint16_t hw_3d_lut : 1; 266 uint16_t ogam_ram : 1; 267 uint16_t ocsc : 1; 268 uint16_t dgam_rom_for_yuv : 1; 269 uint16_t upsp_pre_scaler : 1; 270 struct rom_curve_caps dgam_rom_caps; 271 struct rom_curve_caps ogam_rom_caps; 272 }; 273 274 /* Below structure is to describe the HW support for mem layout, extend support 275 range to match what OS could handle in the roadmap */ 276 struct lut3d_caps { 277 uint32_t dma_3d_lut : 1; /*< DMA mode support for 3D LUT */ 278 struct { 279 uint32_t swizzle_3d_rgb : 1; 280 uint32_t swizzle_3d_bgr : 1; 281 uint32_t linear_1d : 1; 282 } mem_layout_support; 283 struct { 284 uint32_t unorm_12msb : 1; 285 uint32_t unorm_12lsb : 1; 286 uint32_t float_fp1_5_10 : 1; 287 } mem_format_support; 288 struct { 289 uint32_t order_rgba : 1; 290 uint32_t order_bgra : 1; 291 } mem_pixel_order_support; 292 /*< size options are 9, 17, 33, 45, 65 */ 293 struct { 294 uint32_t dim_9 : 1; /* 3D LUT support for 9x9x9 */ 295 uint32_t dim_17 : 1; /* 3D LUT support for 17x17x17 */ 296 uint32_t dim_33 : 1; /* 3D LUT support for 33x33x33 */ 297 uint32_t dim_45 : 1; /* 3D LUT support for 45x45x45 */ 298 uint32_t dim_65 : 1; /* 3D LUT support for 65x65x65 */ 299 } lut_dim_caps; 300 }; 301 302 /** 303 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 304 * plane combined blocks 305 * 306 * @gamut_remap: color transformation matrix 307 * @ogam_ram: programmable out gamma LUT 308 * @ocsc: output color space conversion matrix 309 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 310 * @num_rmcm_3dluts: number of RMCM 3D LUTS; always assumes a preceding shaper LUT 311 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 312 * instance 313 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 314 * @mcm_3d_lut_caps: HW support cap for MCM LUT memory 315 * @rmcm_3d_lut_caps: HW support cap for RMCM LUT memory 316 * @preblend: whether color manager supports preblend with MPC 317 */ 318 struct mpc_color_caps { 319 uint16_t gamut_remap : 1; 320 uint16_t ogam_ram : 1; 321 uint16_t ocsc : 1; 322 uint16_t num_3dluts : 3; 323 uint16_t num_rmcm_3dluts : 3; 324 uint16_t shared_3d_lut:1; 325 struct rom_curve_caps ogam_rom_caps; 326 struct lut3d_caps mcm_3d_lut_caps; 327 struct lut3d_caps rmcm_3d_lut_caps; 328 bool preblend; 329 struct fixed31_32 max_gamut_remap_coeff; 330 }; 331 332 /** 333 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 334 * @dpp: color pipes caps for DPP 335 * @mpc: color pipes caps for MPC 336 */ 337 struct dc_color_caps { 338 struct dpp_color_caps dpp; 339 struct mpc_color_caps mpc; 340 }; 341 342 struct dc_dmub_caps { 343 bool psr; 344 bool mclk_sw; 345 bool subvp_psr; 346 bool gecc_enable; 347 uint8_t fams_ver; 348 bool aux_backlight_support; 349 }; 350 351 struct dc_scl_caps { 352 bool sharpener_support; 353 }; 354 355 struct dc_check_config { 356 /** 357 * max video plane width that can be safely assumed to be always 358 * supported by single DPP pipe. 359 */ 360 unsigned int max_optimizable_video_width; 361 bool enable_legacy_fast_update; 362 363 bool deferred_transition_state; 364 unsigned int transition_countdown_to_steady_state; 365 }; 366 367 struct dc_caps { 368 uint32_t max_streams; 369 uint32_t max_links; 370 uint32_t max_audios; 371 uint32_t max_slave_planes; 372 uint32_t max_slave_yuv_planes; 373 uint32_t max_slave_rgb_planes; 374 uint32_t max_planes; 375 uint32_t max_downscale_ratio; 376 uint32_t i2c_speed_in_khz; 377 uint32_t i2c_speed_in_khz_hdcp; 378 uint32_t dmdata_alloc_size; 379 unsigned int max_cursor_size; 380 unsigned int max_buffered_cursor_size; 381 unsigned int max_video_width; 382 unsigned int min_horizontal_blanking_period; 383 int linear_pitch_alignment; 384 bool dcc_const_color; 385 bool dynamic_audio; 386 bool is_apu; 387 bool dual_link_dvi; 388 bool post_blend_color_processing; 389 bool force_dp_tps4_for_cp2520; 390 bool disable_dp_clk_share; 391 bool psp_setup_panel_mode; 392 bool extended_aux_timeout_support; 393 bool dmcub_support; 394 bool zstate_support; 395 bool ips_support; 396 bool ips_v2_support; 397 uint32_t num_of_internal_disp; 398 enum dp_protocol_version max_dp_protocol_version; 399 bool hdmi_hpo; 400 unsigned int mall_size_per_mem_channel; 401 unsigned int mall_size_total; 402 unsigned int cursor_cache_size; 403 struct dc_plane_cap planes[MAX_PLANES]; 404 struct dc_color_caps color; 405 struct dc_dmub_caps dmub_caps; 406 bool dp_hpo; 407 bool dp_hdmi21_pcon_support; 408 bool edp_dsc_support; 409 bool vbios_lttpr_aware; 410 bool vbios_lttpr_enable; 411 bool fused_io_supported; 412 uint32_t max_otg_num; 413 uint32_t max_cab_allocation_bytes; 414 uint32_t cache_line_size; 415 uint32_t cache_num_ways; 416 uint16_t subvp_fw_processing_delay_us; 417 uint8_t subvp_drr_max_vblank_margin_us; 418 uint16_t subvp_prefetch_end_to_mall_start_us; 419 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 420 uint16_t subvp_pstate_allow_width_us; 421 uint16_t subvp_vertical_int_margin_us; 422 bool seamless_odm; 423 uint32_t max_v_total; 424 bool vtotal_limited_by_fp2; 425 uint32_t max_disp_clock_khz_at_vmin; 426 uint8_t subvp_drr_vblank_start_margin_us; 427 bool cursor_not_scaled; 428 bool dcmode_power_limits_present; 429 bool sequential_ono; 430 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 431 uint32_t dcc_plane_width_limit; 432 struct dc_scl_caps scl_caps; 433 uint8_t num_of_host_routers; 434 uint8_t num_of_dpias_per_host_router; 435 /* limit of the ODM only, could be limited by other factors (like pipe count)*/ 436 uint8_t max_odm_combine_factor; 437 bool utm_support; 438 }; 439 440 struct dc_bug_wa { 441 bool no_connect_phy_config; 442 bool dedcn20_305_wa; 443 bool skip_clock_update; 444 bool lt_early_cr_pattern; 445 struct { 446 uint8_t uclk : 1; 447 uint8_t fclk : 1; 448 uint8_t dcfclk : 1; 449 uint8_t dcfclk_ds: 1; 450 } clock_update_disable_mask; 451 bool skip_psr_ips_crtc_disable; 452 }; 453 struct dc_dcc_surface_param { 454 struct dc_size surface_size; 455 enum surface_pixel_format format; 456 unsigned int plane0_pitch; 457 struct dc_size plane1_size; 458 unsigned int plane1_pitch; 459 union { 460 enum swizzle_mode_values swizzle_mode; 461 enum swizzle_mode_addr3_values swizzle_mode_addr3; 462 }; 463 enum dc_scan_direction scan; 464 }; 465 466 struct dc_dcc_setting { 467 unsigned int max_compressed_blk_size; 468 unsigned int max_uncompressed_blk_size; 469 bool independent_64b_blks; 470 //These bitfields to be used starting with DCN 3.0 471 struct { 472 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 473 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 474 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 475 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 476 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 477 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 478 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 479 } dcc_controls; 480 }; 481 482 struct dc_surface_dcc_cap { 483 union { 484 struct { 485 struct dc_dcc_setting rgb; 486 } grph; 487 488 struct { 489 struct dc_dcc_setting luma; 490 struct dc_dcc_setting chroma; 491 } video; 492 }; 493 494 bool capable; 495 bool const_color_support; 496 }; 497 498 struct dc_static_screen_params { 499 struct { 500 bool force_trigger; 501 bool cursor_update; 502 bool surface_update; 503 bool overlay_update; 504 } triggers; 505 unsigned int num_frames; 506 }; 507 508 509 /* Surface update type is used by dc_update_surfaces_and_stream 510 * The update type is determined at the very beginning of the function based 511 * on parameters passed in and decides how much programming (or updating) is 512 * going to be done during the call. 513 * 514 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 515 * logical calculations or hardware register programming. This update MUST be 516 * ISR safe on windows. Currently fast update will only be used to flip surface 517 * address. 518 * 519 * UPDATE_TYPE_MED is used for slower updates which require significant hw 520 * re-programming however do not affect bandwidth consumption or clock 521 * requirements. At present, this is the level at which front end updates 522 * that do not require us to run bw_calcs happen. These are in/out transfer func 523 * updates, viewport offset changes, recout size changes and pixel depth changes. 524 * This update can be done at ISR, but we want to minimize how often this happens. 525 * 526 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 527 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 528 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 529 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 530 * a full update. This cannot be done at ISR level and should be a rare event. 531 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 532 * underscan we don't expect to see this call at all. 533 */ 534 535 enum dc_update_type { 536 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 537 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 538 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 539 }; 540 541 enum dc_lock_descriptor { 542 LOCK_DESCRIPTOR_NONE = 0x0, 543 LOCK_DESCRIPTOR_STREAM = 0x1, 544 LOCK_DESCRIPTOR_LINK = 0x2, 545 LOCK_DESCRIPTOR_GLOBAL = 0x4, 546 LOCK_DESCRIPTOR_PROBE = 0x8, 547 }; 548 549 struct dc_update_descriptor { 550 enum dc_update_type update_type; 551 enum dc_lock_descriptor lock_descriptor; 552 }; 553 554 /* Forward declaration*/ 555 struct dc; 556 struct dc_plane_state; 557 struct dc_state; 558 559 struct dc_cap_funcs { 560 bool (*get_dcc_compression_cap)(const struct dc *dc, 561 const struct dc_dcc_surface_param *input, 562 struct dc_surface_dcc_cap *output); 563 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 564 }; 565 566 struct link_training_settings; 567 568 union allow_lttpr_non_transparent_mode { 569 struct { 570 bool DP1_4A : 1; 571 bool DP2_0 : 1; 572 } bits; 573 unsigned char raw; 574 }; 575 /* Structure to hold configuration flags set by dm at dc creation. */ 576 struct dc_config { 577 bool gpu_vm_support; 578 bool disable_disp_pll_sharing; 579 bool fbc_support; 580 bool disable_fractional_pwm; 581 bool allow_seamless_boot_optimization; 582 bool seamless_boot_edp_requested; 583 bool edp_not_connected; 584 bool edp_no_power_sequencing; 585 bool force_enum_edp; 586 bool forced_clocks; 587 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 588 bool multi_mon_pp_mclk_switch; 589 bool lsdma_peak_bw_contention_support; 590 bool disable_dmcu; 591 bool allow_4to1MPC; 592 bool enable_windowed_mpo_odm; 593 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 594 uint32_t allow_edp_hotplug_detection; 595 bool skip_riommu_prefetch_wa; 596 bool clamp_min_dcfclk; 597 uint64_t vblank_alignment_dto_params; 598 uint8_t vblank_alignment_max_frame_time_diff; 599 bool is_asymmetric_memory; 600 bool is_single_rank_dimm; 601 bool is_vmin_only_asic; 602 bool use_spl; 603 bool prefer_easf; 604 bool use_pipe_ctx_sync_logic; 605 int smart_mux_version; 606 bool ignore_dpref_ss; 607 bool enable_mipi_converter_optimization; 608 bool enable_frl; 609 bool force_hdmi21_frl_enc_enable; 610 bool use_default_clock_table; 611 bool force_bios_enable_lttpr; 612 uint8_t force_bios_fixed_vs; 613 unsigned int sdpif_request_limit_words_per_umc; 614 bool dc_mode_clk_limit_support; 615 bool EnableMinDispClkODM; 616 bool enable_auto_dpm_test_logs; 617 unsigned int disable_ips; 618 unsigned int disable_ips_rcg; 619 unsigned int disable_ips_in_vpb; 620 bool disable_ips_in_dpms_off; 621 bool usb4_bw_alloc_support; 622 bool allow_0_dtb_clk; 623 bool use_assr_psp_message; 624 bool support_edp0_on_dp1; 625 unsigned int enable_fpo_flicker_detection; 626 bool disable_hbr_audio_dp2; 627 bool consolidated_dpia_dp_lt; 628 bool set_pipe_unlock_order; 629 bool enable_dpia_pre_training; 630 bool unify_link_enc_assignment; 631 bool enable_cursor_offload; 632 bool dp_connector_no_native_i2c; 633 unsigned int link_index_with_no_ddc; 634 bool frame_update_cmd_version2; 635 struct spl_sharpness_range dcn_sharpness_range; 636 struct spl_sharpness_range dcn_override_sharpness_range; 637 bool no_native422_support; 638 }; 639 640 enum visual_confirm { 641 VISUAL_CONFIRM_DISABLE = 0, 642 VISUAL_CONFIRM_SURFACE = 1, 643 VISUAL_CONFIRM_HDR = 2, 644 VISUAL_CONFIRM_MPCTREE = 4, 645 VISUAL_CONFIRM_PSR = 5, 646 VISUAL_CONFIRM_SWAPCHAIN = 6, 647 VISUAL_CONFIRM_FAMS = 7, 648 VISUAL_CONFIRM_SWIZZLE = 9, 649 VISUAL_CONFIRM_SMARTMUX_DGPU = 10, 650 VISUAL_CONFIRM_REPLAY = 12, 651 VISUAL_CONFIRM_SUBVP = 14, 652 VISUAL_CONFIRM_ABM = 15, 653 VISUAL_CONFIRM_MCLK_SWITCH = 16, 654 VISUAL_CONFIRM_FAMS2 = 19, 655 VISUAL_CONFIRM_HW_CURSOR = 20, 656 VISUAL_CONFIRM_VABC = 21, 657 VISUAL_CONFIRM_DCC = 22, 658 VISUAL_CONFIRM_BOOSTED_REFRESH_RATE = 23, 659 VISUAL_CONFIRM_DM_PASSTHROUGH = 26, 660 VISUAL_CONFIRM_EXPLICIT = 0x80000000, 661 }; 662 663 enum dc_psr_power_opts { 664 psr_power_opt_invalid = 0x0, 665 psr_power_opt_smu_opt_static_screen = 0x1, 666 psr_power_opt_z10_static_screen = 0x10, 667 psr_power_opt_ds_disable_allow = 0x100, 668 }; 669 670 enum dml_hostvm_override_opts { 671 DML_HOSTVM_NO_OVERRIDE = 0x0, 672 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 673 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 674 }; 675 676 enum dc_replay_power_opts { 677 replay_power_opt_invalid = 0x0, 678 replay_power_opt_smu_opt_static_screen = 0x1, 679 replay_power_opt_z10_static_screen = 0x10, 680 }; 681 682 enum dcc_option { 683 DCC_ENABLE = 0, 684 DCC_DISABLE = 1, 685 DCC_HALF_REQ_DISALBE = 2, 686 }; 687 688 enum in_game_fams_config { 689 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 690 INGAME_FAMS_DISABLE, // disable in-game fams 691 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 692 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 693 }; 694 695 /** 696 * enum pipe_split_policy - Pipe split strategy supported by DCN 697 * 698 * This enum is used to define the pipe split policy supported by DCN. By 699 * default, DC favors MPC_SPLIT_DYNAMIC. 700 */ 701 enum pipe_split_policy { 702 /** 703 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 704 * pipe in order to bring the best trade-off between performance and 705 * power consumption. This is the recommended option. 706 */ 707 MPC_SPLIT_DYNAMIC = 0, 708 709 /** 710 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 711 * try any sort of split optimization. 712 */ 713 MPC_SPLIT_AVOID = 1, 714 715 /** 716 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 717 * optimize the pipe utilization when using a single display; if the 718 * user connects to a second display, DC will avoid pipe split. 719 */ 720 MPC_SPLIT_AVOID_MULT_DISP = 2, 721 }; 722 723 enum wm_report_mode { 724 WM_REPORT_DEFAULT = 0, 725 WM_REPORT_OVERRIDE = 1, 726 }; 727 enum dtm_pstate{ 728 dtm_level_p0 = 0,/*highest voltage*/ 729 dtm_level_p1, 730 dtm_level_p2, 731 dtm_level_p3, 732 dtm_level_p4,/*when active_display_count = 0*/ 733 }; 734 735 enum dcn_pwr_state { 736 DCN_PWR_STATE_UNKNOWN = -1, 737 DCN_PWR_STATE_MISSION_MODE = 0, 738 DCN_PWR_STATE_LOW_POWER = 3, 739 }; 740 741 enum dcn_zstate_support_state { 742 DCN_ZSTATE_SUPPORT_UNKNOWN, 743 DCN_ZSTATE_SUPPORT_ALLOW, 744 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 745 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 746 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 747 DCN_ZSTATE_SUPPORT_DISALLOW, 748 }; 749 750 /* 751 * struct dc_clocks - DC pipe clocks 752 * 753 * For any clocks that may differ per pipe only the max is stored in this 754 * structure 755 */ 756 struct dc_clocks { 757 int dispclk_khz; 758 int actual_dispclk_khz; 759 int dppclk_khz; 760 int actual_dppclk_khz; 761 int disp_dpp_voltage_level_khz; 762 int dcfclk_khz; 763 int socclk_khz; 764 int dcfclk_deep_sleep_khz; 765 int fclk_khz; 766 int phyclk_khz; 767 int dramclk_khz; 768 bool p_state_change_support; 769 enum dcn_zstate_support_state zstate_support; 770 bool dtbclk_en; 771 int ref_dtbclk_khz; 772 bool fclk_p_state_change_support; 773 enum dcn_pwr_state pwr_state; 774 /* 775 * Elements below are not compared for the purposes of 776 * optimization required 777 */ 778 779 /* 780 * @cstate_allow 781 * 782 * DCN's DF C-state vote as last successfully acknowledged by PMFW. 783 * false = DCN does NOT permit DF C-state; 784 * true = DCN permits DF C-state; 785 */ 786 bool cstate_allow; 787 bool prev_p_state_change_support; 788 bool fclk_prev_p_state_change_support; 789 int num_ways; 790 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 791 792 /* 793 * @fw_based_mclk_switching 794 * 795 * DC has a mechanism that leverage the variable refresh rate to switch 796 * memory clock in cases that we have a large latency to achieve the 797 * memory clock change and a short vblank window. DC has some 798 * requirements to enable this feature, and this field describes if the 799 * system support or not such a feature. 800 */ 801 bool fw_based_mclk_switching; 802 bool fw_based_mclk_switching_shut_down; 803 bool alt_ch_pstate_switch; 804 int prev_num_ways; 805 enum dtm_pstate dtm_level; 806 int max_supported_dppclk_khz; 807 int max_supported_dispclk_khz; 808 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 809 int bw_dispclk_khz; 810 int idle_dramclk_khz; 811 int idle_fclk_khz; 812 int subvp_prefetch_dramclk_khz; 813 int subvp_prefetch_fclk_khz; 814 /* deprecated: use _KBps variants — will be removed after DML update */ 815 unsigned int utm_urgent_bandwidth_lb_Kbps; 816 unsigned int utm_nominal_bandwidth_lb_Kbps; 817 unsigned int utm_urgent_bandwidth_lb_KBps; 818 unsigned int utm_nominal_bandwidth_lb_KBps; 819 unsigned int utm_latency_ub_index; 820 unsigned int utm_lsdma_bandwidth_lb_KBps; 821 unsigned int utm_nominal_max_latency_ub_ns; 822 unsigned int utm_nominal_avg_latency_ub_ns; 823 /* deprecated: use _KBps variant — will be removed after DML update */ 824 unsigned int required_avg_active_bandwidth_Kbps; 825 unsigned int required_avg_active_bandwidth_KBps; 826 827 /* Stutter efficiency is technically not clock values 828 * but stored here so the values are part of the update_clocks call similar to num_ways 829 * Efficiencies are stored as percentage (0-100) 830 */ 831 struct { 832 uint8_t base_efficiency; //LP1 833 uint8_t low_power_efficiency; //LP2 834 uint8_t z8_stutter_efficiency; 835 int z8_stutter_period; 836 } stutter_efficiency; 837 }; 838 839 struct dc_bw_validation_profile { 840 bool enable; 841 842 unsigned long long total_ticks; 843 unsigned long long voltage_level_ticks; 844 unsigned long long watermark_ticks; 845 unsigned long long rq_dlg_ticks; 846 847 unsigned long long total_count; 848 unsigned long long skip_fast_count; 849 unsigned long long skip_pass_count; 850 unsigned long long skip_fail_count; 851 }; 852 853 #define BW_VAL_TRACE_SETUP() \ 854 unsigned long long end_tick = 0; \ 855 unsigned long long voltage_level_tick = 0; \ 856 unsigned long long watermark_tick = 0; \ 857 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 858 dm_get_timestamp(dc->ctx) : 0 859 860 #define BW_VAL_TRACE_COUNT() \ 861 if (dc->debug.bw_val_profile.enable) \ 862 dc->debug.bw_val_profile.total_count++ 863 864 #define BW_VAL_TRACE_SKIP(status) \ 865 if (dc->debug.bw_val_profile.enable) { \ 866 if (!voltage_level_tick) \ 867 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 868 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 869 } 870 871 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 872 if (dc->debug.bw_val_profile.enable) \ 873 voltage_level_tick = dm_get_timestamp(dc->ctx) 874 875 #define BW_VAL_TRACE_END_WATERMARKS() \ 876 if (dc->debug.bw_val_profile.enable) \ 877 watermark_tick = dm_get_timestamp(dc->ctx) 878 879 #define BW_VAL_TRACE_FINISH() \ 880 if (dc->debug.bw_val_profile.enable) { \ 881 end_tick = dm_get_timestamp(dc->ctx); \ 882 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 883 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 884 if (watermark_tick) { \ 885 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 886 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 887 } \ 888 } 889 890 union mem_low_power_enable_options { 891 struct { 892 bool vga: 1; 893 bool i2c: 1; 894 bool dmcu: 1; 895 bool dscl: 1; 896 bool cm: 1; 897 bool mpc: 1; 898 bool optc: 1; 899 bool vpg: 1; 900 bool afmt: 1; 901 } bits; 902 uint32_t u32All; 903 }; 904 905 union root_clock_optimization_options { 906 struct { 907 bool dpp: 1; 908 bool dsc: 1; 909 bool hdmistream: 1; 910 bool hdmichar: 1; 911 bool dpstream: 1; 912 bool symclk32_se: 1; 913 bool symclk32_le: 1; 914 bool symclk_fe: 1; 915 bool physymclk: 1; 916 bool dpiasymclk: 1; 917 uint32_t reserved: 22; 918 } bits; 919 uint32_t u32All; 920 }; 921 922 union fine_grain_clock_gating_enable_options { 923 struct { 924 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 925 bool dchub : 1; /* Display controller hub */ 926 bool dchubbub : 1; 927 bool dpp : 1; /* Display pipes and planes */ 928 bool opp : 1; /* Output pixel processing */ 929 bool optc : 1; /* Output pipe timing combiner */ 930 bool dio : 1; /* Display output */ 931 bool dwb : 1; /* Display writeback */ 932 bool mmhubbub : 1; /* Multimedia hub */ 933 bool dmu : 1; /* Display core management unit */ 934 bool az : 1; /* Azalia */ 935 bool dchvm : 1; 936 bool dsc : 1; /* Display stream compression */ 937 938 uint32_t reserved : 19; 939 } bits; 940 uint32_t u32All; 941 }; 942 943 enum pg_hw_pipe_resources { 944 PG_HUBP = 0, 945 PG_DPP, 946 PG_DSC, 947 PG_MPCC, 948 PG_OPP, 949 PG_OPTC, 950 PG_DPSTREAM, 951 PG_HDMISTREAM, 952 PG_PHYSYMCLK, 953 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 954 }; 955 956 enum pg_hw_resources { 957 PG_DCCG = 0, 958 PG_DCIO, 959 PG_DIO, 960 PG_DCHUBBUB, 961 PG_DCHVM, 962 PG_DWB, 963 PG_HPO, 964 PG_DCOH, 965 PG_HW_RESOURCES_NUM_ELEMENT 966 }; 967 968 struct pg_block_update { 969 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 970 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 971 }; 972 973 union dpia_debug_options { 974 struct { 975 uint32_t disable_dpia:1; /* bit 0 */ 976 uint32_t force_non_lttpr:1; /* bit 1 */ 977 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 978 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 979 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 980 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 981 uint32_t enable_usb4_bw_zero_alloc_patch:1; /* bit 6 */ 982 uint32_t reserved:25; 983 } bits; 984 uint32_t raw; 985 }; 986 987 /* AUX wake work around options 988 * 0: enable/disable work around 989 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 990 * 15-2: reserved 991 * 31-16: timeout in ms 992 */ 993 union aux_wake_wa_options { 994 struct { 995 uint32_t enable_wa : 1; 996 uint32_t use_default_timeout : 1; 997 uint32_t rsvd: 14; 998 uint32_t timeout_ms : 16; 999 } bits; 1000 uint32_t raw; 1001 }; 1002 1003 struct dc_debug_data { 1004 uint32_t ltFailCount; 1005 uint32_t i2cErrorCount; 1006 uint32_t auxErrorCount; 1007 struct pipe_topology_history topology_history; 1008 }; 1009 1010 struct dc_phy_addr_space_config { 1011 struct { 1012 uint64_t start_addr; 1013 uint64_t end_addr; 1014 uint64_t fb_top; 1015 uint64_t fb_offset; 1016 uint64_t fb_base; 1017 uint64_t agp_top; 1018 uint64_t agp_bot; 1019 uint64_t agp_base; 1020 } system_aperture; 1021 1022 struct { 1023 uint64_t page_table_start_addr; 1024 uint64_t page_table_end_addr; 1025 uint64_t page_table_base_addr; 1026 bool base_addr_is_mc_addr; 1027 } gart_config; 1028 1029 bool valid; 1030 bool is_hvm_enabled; 1031 uint64_t page_table_default_page_addr; 1032 }; 1033 1034 struct dc_virtual_addr_space_config { 1035 uint64_t page_table_base_addr; 1036 uint64_t page_table_start_addr; 1037 uint64_t page_table_end_addr; 1038 uint32_t page_table_block_size_in_bytes; 1039 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 1040 }; 1041 1042 struct dc_bounding_box_overrides { 1043 unsigned int sr_exit_time_ns; 1044 unsigned int sr_enter_plus_exit_time_ns; 1045 unsigned int sr_lp_exit_time_ns; 1046 unsigned int sr_lp_enter_plus_exit_time_ns; 1047 unsigned int sr_exit_z8_time_ns; 1048 unsigned int sr_enter_plus_exit_z8_time_ns; 1049 unsigned int urgent_latency_ns; 1050 unsigned int percent_of_ideal_drambw; 1051 unsigned int dram_clock_change_latency_ns; 1052 unsigned int dummy_clock_change_latency_ns; 1053 unsigned int fclk_clock_change_latency_ns; 1054 /* This forces a hard min on the DCFCLK we use 1055 * for DML. Unlike the debug option for forcing 1056 * DCFCLK, this override affects watermark calculations 1057 */ 1058 unsigned int min_dcfclk_mhz; 1059 }; 1060 1061 struct dc_qos_info { 1062 uint32_t qos_bandwidth_lb_in_mbps; 1063 uint32_t calculated_avg_bw_in_mbps; 1064 uint32_t qos_max_latency_ub_in_ns; 1065 uint32_t qos_avg_latency_ub_in_ns; 1066 uint32_t dcn_bandwidth_ub_in_mbps; 1067 uint32_t qos_max_bw_budget_in_mbps; 1068 }; 1069 1070 struct dc_state; 1071 struct resource_pool; 1072 struct dce_hwseq; 1073 struct link_service; 1074 1075 /* 1076 * struct dc_debug_options - DC debug struct 1077 * 1078 * This struct provides a simple mechanism for developers to change some 1079 * configurations, enable/disable features, and activate extra debug options. 1080 * This can be very handy to narrow down whether some specific feature is 1081 * causing an issue or not. 1082 */ 1083 struct dc_debug_options { 1084 bool disable_dsc; 1085 enum visual_confirm visual_confirm; 1086 unsigned int visual_confirm_rect_height; 1087 1088 bool sanity_checks; 1089 bool max_disp_clk; 1090 bool surface_trace; 1091 bool clock_trace; 1092 bool validation_trace; 1093 bool bandwidth_calcs_trace; 1094 int max_downscale_src_width; 1095 1096 /* stutter efficiency related */ 1097 bool disable_stutter; 1098 bool use_max_lb; 1099 enum dcc_option disable_dcc; 1100 1101 /* 1102 * @pipe_split_policy: Define which pipe split policy is used by the 1103 * display core. 1104 */ 1105 enum pipe_split_policy pipe_split_policy; 1106 bool force_single_disp_pipe_split; 1107 bool voltage_align_fclk; 1108 bool disable_min_fclk; 1109 1110 bool hdcp_lc_force_fw_enable; 1111 bool hdcp_lc_enable_sw_fallback; 1112 1113 bool disable_dfs_bypass; 1114 bool disable_dpp_power_gate; 1115 bool disable_hubp_power_gate; 1116 bool disable_dsc_power_gate; 1117 bool disable_optc_power_gate; 1118 bool disable_hpo_power_gate; 1119 bool disable_io_clk_power_gate; 1120 bool disable_mem_power_gate; 1121 bool disable_dio_power_gate; 1122 unsigned int dsc_min_slice_height_override; 1123 unsigned int dsc_bpp_increment_div; 1124 bool disable_pplib_wm_range; 1125 enum wm_report_mode pplib_wm_report_mode; 1126 unsigned int min_disp_clk_khz; 1127 unsigned int min_dpp_clk_khz; 1128 unsigned int min_dram_clk_khz; 1129 unsigned int sr_exit_time_dpm0_ns; 1130 unsigned int sr_enter_plus_exit_time_dpm0_ns; 1131 unsigned int sr_exit_time_ns; 1132 unsigned int sr_enter_plus_exit_time_ns; 1133 unsigned int sr_exit_z8_time_ns; 1134 unsigned int sr_enter_plus_exit_z8_time_ns; 1135 unsigned int urgent_latency_ns; 1136 uint32_t underflow_assert_delay_us; 1137 unsigned int percent_of_ideal_drambw; 1138 unsigned int dram_clock_change_latency_ns; 1139 bool optimized_watermark; 1140 int always_scale; 1141 bool disable_pplib_clock_request; 1142 bool disable_clock_gate; 1143 bool disable_mem_low_power; 1144 bool pstate_enabled; 1145 bool disable_dmcu; 1146 bool force_abm_enable; 1147 bool disable_stereo_support; 1148 bool vsr_support; 1149 bool performance_trace; 1150 bool az_endpoint_mute_only; 1151 bool always_use_regamma; 1152 bool recovery_enabled; 1153 bool avoid_vbios_exec_table; 1154 bool scl_reset_length10; 1155 bool hdmi20_disable; 1156 bool skip_detection_link_training; 1157 uint32_t edid_read_retry_times; 1158 1159 uint8_t force_odm_combine; //bit vector based on otg inst 1160 uint8_t seamless_boot_odm_combine; 1161 uint8_t force_odm_combine_4to1; //bit vector based on otg inst 1162 1163 unsigned int minimum_z8_residency_time; 1164 unsigned int minimum_z10_residency_time; 1165 bool disable_z9_mpc; 1166 unsigned int force_fclk_khz; 1167 bool enable_tri_buf; 1168 bool ips_disallow_entry; 1169 bool disable_idle_power_optimizations; 1170 unsigned int mall_size_override; 1171 unsigned int mall_additional_timer_percent; 1172 bool mall_error_as_fatal; 1173 bool dmub_command_table; /* for testing only */ 1174 struct dc_bw_validation_profile bw_val_profile; 1175 bool disable_fec; 1176 bool disable_48mhz_pwrdwn; 1177 /* This forces a hard min on the DCFCLK requested to SMU/PP 1178 * watermarks are not affected. 1179 */ 1180 unsigned int force_min_dcfclk_mhz; 1181 int dwb_fi_phase; 1182 bool disable_timing_sync; 1183 bool cm_in_bypass; 1184 int force_clock_mode;/*every mode change.*/ 1185 1186 bool disable_dram_clock_change_vactive_support; 1187 bool validate_dml_output; 1188 bool enable_dmcub_surface_flip; 1189 bool usbc_combo_phy_reset_wa; 1190 bool force_fva; 1191 int max_frl_rate; 1192 unsigned int force_frl_rate; 1193 bool ignore_ffe; 1194 unsigned int select_ffe; 1195 unsigned int limit_ffe; 1196 bool force_frl_always; 1197 bool force_frl_dsc; 1198 bool force_frl_max; 1199 bool apply_vsdb_rcc_wa; 1200 bool enable_hdmi_idcc; 1201 1202 bool enable_dram_clock_change_one_display_vactive; 1203 /* TODO - remove once tested */ 1204 bool legacy_dp2_lt; 1205 bool set_mst_en_for_sst; 1206 bool disable_uhbr; 1207 bool force_dp2_lt_fallback_method; 1208 bool ignore_cable_id; 1209 union mem_low_power_enable_options enable_mem_low_power; 1210 union root_clock_optimization_options root_clock_optimization; 1211 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 1212 bool hpo_optimization; 1213 bool force_vblank_alignment; 1214 1215 /* Enable dmub aux for legacy ddc */ 1216 bool enable_dmub_aux_for_legacy_ddc; 1217 bool disable_fams; 1218 enum in_game_fams_config disable_fams_gaming; 1219 /* FEC/PSR1 sequence enable delay in 100us */ 1220 uint8_t fec_enable_delay_in100us; 1221 bool enable_driver_sequence_debug; 1222 enum det_size crb_alloc_policy; 1223 unsigned int crb_alloc_policy_min_disp_count; 1224 bool disable_z10; 1225 bool enable_z9_disable_interface; 1226 bool psr_skip_crtc_disable; 1227 uint32_t ips_skip_crtc_disable_mask; 1228 union dpia_debug_options dpia_debug; 1229 bool disable_fixed_vs_aux_timeout_wa; 1230 uint32_t fixed_vs_aux_delay_config_wa; 1231 bool force_disable_subvp; 1232 bool force_subvp_mclk_switch; 1233 bool allow_sw_cursor_fallback; 1234 unsigned int force_subvp_num_ways; 1235 unsigned int force_mall_ss_num_ways; 1236 bool alloc_extra_way_for_cursor; 1237 uint32_t subvp_extra_lines; 1238 bool disable_force_pstate_allow_on_hw_release; 1239 bool force_usr_allow; 1240 /* uses value at boot and disables switch */ 1241 bool disable_dtb_ref_clk_switch; 1242 bool extended_blank_optimization; 1243 union aux_wake_wa_options aux_wake_wa; 1244 uint32_t mst_start_top_delay; 1245 uint8_t psr_power_use_phy_fsm; 1246 enum dml_hostvm_override_opts dml_hostvm_override; 1247 bool dml_disallow_alternate_prefetch_modes; 1248 bool use_legacy_soc_bb_mechanism; 1249 bool exit_idle_opt_for_cursor_updates; 1250 bool using_dml2; 1251 bool enable_single_display_2to1_odm_policy; 1252 bool enable_double_buffered_dsc_pg_support; 1253 bool enable_dp_dig_pixel_rate_div_policy; 1254 bool using_dml21; 1255 enum lttpr_mode lttpr_mode_override; 1256 unsigned int dsc_delay_factor_wa_x1000; 1257 unsigned int min_prefetch_in_strobe_ns; 1258 bool disable_unbounded_requesting; 1259 bool dig_fifo_off_in_blank; 1260 bool override_dispclk_programming; 1261 bool otg_crc_db; 1262 bool disallow_dispclk_dppclk_ds; 1263 bool disable_fpo_optimizations; 1264 bool support_eDP1_5; 1265 uint32_t fpo_vactive_margin_us; 1266 bool disable_fpo_vactive; 1267 bool disable_boot_optimizations; 1268 bool override_odm_optimization; 1269 bool minimize_dispclk_using_odm; 1270 bool disable_subvp_high_refresh; 1271 bool disable_dp_plus_plus_wa; 1272 uint32_t fpo_vactive_min_active_margin_us; 1273 uint32_t fpo_vactive_max_blank_us; 1274 bool enable_hpo_pg_support; 1275 bool disable_dc_mode_overwrite; 1276 bool replay_skip_crtc_disabled; 1277 bool ignore_pg;/*do nothing, let pmfw control it*/ 1278 bool psp_disabled_wa; 1279 unsigned int ips2_eval_delay_us; 1280 unsigned int ips2_entry_delay_us; 1281 bool optimize_ips_handshake; 1282 bool disable_dmub_reallow_idle; 1283 bool disable_timeout; 1284 bool disable_extblankadj; 1285 bool enable_idle_reg_checks; 1286 unsigned int static_screen_wait_frames; 1287 uint32_t pwm_freq; 1288 bool force_chroma_subsampling_1tap; 1289 unsigned int dcc_meta_propagation_delay_us; 1290 bool disable_422_left_edge_pixel; 1291 bool dml21_force_pstate_method; 1292 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1293 uint32_t dml21_disable_pstate_method_mask; 1294 bool force_optional_uclk_pstate_support; 1295 union fw_assisted_mclk_switch_version fams_version; 1296 union dmub_fams2_global_feature_config fams2_config; 1297 bool fams2_imm_restore_drr; 1298 bool skip_hdmi_rr_enable; 1299 unsigned int force_cositing; 1300 unsigned int disable_spl; 1301 unsigned int force_easf; 1302 unsigned int force_sharpness; 1303 unsigned int force_sharpness_level; 1304 unsigned int force_lls; 1305 bool notify_dpia_hr_bw; 1306 bool enable_ips_visual_confirm; 1307 unsigned int sharpen_policy; 1308 unsigned int scale_to_sharpness_policy; 1309 unsigned int enable_oled_edp_power_up_opt; 1310 bool enable_hblank_borrow; 1311 bool force_subvp_df_throttle; 1312 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1313 bool enable_pg_cntl_debug_logs; 1314 unsigned int auxless_alpm_lfps_setup_ns; 1315 unsigned int auxless_alpm_lfps_period_ns; 1316 unsigned int auxless_alpm_lfps_silence_ns; 1317 unsigned int auxless_alpm_lfps_t1t2_us; 1318 short auxless_alpm_lfps_t1t2_offset_us; 1319 bool disable_stutter_for_wm_program; 1320 unsigned int urgent_watermark_override; 1321 bool enable_block_sequence_programming; 1322 uint32_t custom_psp_footer_size; 1323 bool disable_deferred_minimal_transitions; 1324 unsigned int num_fast_flips_to_steady_state_override; 1325 bool enable_dmu_recovery; 1326 unsigned int force_vmin_threshold; 1327 bool enable_otg_frame_sync_pwa; 1328 unsigned int min_deep_sleep_dcfclk_khz; 1329 unsigned int force_odm2to1_for_edp_pixclk_mhz; 1330 bool enable_replay_esd_recovery; 1331 uint8_t iommu_mismatch_temp_wka; 1332 bool disable_dynamic_expansion_for_test_pattern; 1333 bool psr_phy_force_phy_power_down_up_level_2; 1334 uint32_t dml21_custom_derate_num_dpms; 1335 uint32_t dml21_custom_derate_at_dpm[DML2_MAX_NUM_DPM_LVL]; 1336 bool override_utm_client_qc_profile; 1337 uint8_t utm_client_qc_profiles[4]; 1338 }; 1339 1340 1341 /* Generic structure that can be used to query properties of DC. More fields 1342 * can be added as required. 1343 */ 1344 struct dc_current_properties { 1345 unsigned int cursor_size_limit; 1346 }; 1347 1348 enum frame_buffer_mode { 1349 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1350 FRAME_BUFFER_MODE_ZFB_ONLY, 1351 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1352 } ; 1353 1354 struct dchub_init_data { 1355 int64_t zfb_phys_addr_base; 1356 int64_t zfb_mc_base_addr; 1357 uint64_t zfb_size_in_byte; 1358 enum frame_buffer_mode fb_mode; 1359 bool dchub_initialzied; 1360 bool dchub_info_valid; 1361 }; 1362 1363 struct dml2_soc_bb; 1364 1365 struct dc_init_data { 1366 struct hw_asic_id asic_id; 1367 void *driver; /* ctx */ 1368 struct cgs_device *cgs_device; 1369 struct dc_bounding_box_overrides bb_overrides; 1370 1371 int num_virtual_links; 1372 /* 1373 * If 'vbios_override' not NULL, it will be called instead 1374 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1375 */ 1376 struct dc_bios *vbios_override; 1377 enum dce_environment dce_environment; 1378 1379 struct dmub_offload_funcs *dmub_if; 1380 1381 struct dc_config flags; 1382 uint64_t log_mask; 1383 1384 struct dpcd_vendor_signature vendor_signature; 1385 bool force_smu_not_present; 1386 /* 1387 * IP offset for run time initializaion of register addresses 1388 * 1389 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1390 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1391 * before them. 1392 */ 1393 uint32_t *dcn_reg_offsets; 1394 uint32_t *nbio_reg_offsets; 1395 uint32_t *clk_reg_offsets; 1396 void *bb_from_dmub; 1397 enum dc2_selection dc2_selection; 1398 }; 1399 1400 struct dc_callback_init { 1401 struct cp_psp cp_psp; 1402 }; 1403 1404 struct dc *dc_create(const struct dc_init_data *init_params); 1405 void dc_hardware_init(struct dc *dc); 1406 1407 int dc_get_vmid_use_vector(struct dc *dc); 1408 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1409 /* Returns the number of vmids supported */ 1410 unsigned int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1411 void dc_init_callbacks(struct dc *dc, 1412 const struct dc_callback_init *init_params); 1413 void dc_deinit_callbacks(struct dc *dc); 1414 void dc_destroy(struct dc **dc); 1415 1416 /* Surface Interfaces */ 1417 1418 enum { 1419 TRANSFER_FUNC_POINTS = 1025 1420 }; 1421 1422 struct dc_hdr_static_metadata { 1423 /* display chromaticities and white point in units of 0.00001 */ 1424 unsigned int chromaticity_green_x; 1425 unsigned int chromaticity_green_y; 1426 unsigned int chromaticity_blue_x; 1427 unsigned int chromaticity_blue_y; 1428 unsigned int chromaticity_red_x; 1429 unsigned int chromaticity_red_y; 1430 unsigned int chromaticity_white_point_x; 1431 unsigned int chromaticity_white_point_y; 1432 1433 uint32_t min_luminance; 1434 uint32_t max_luminance; 1435 uint32_t maximum_content_light_level; 1436 uint32_t maximum_frame_average_light_level; 1437 }; 1438 1439 enum dc_transfer_func_type { 1440 TF_TYPE_PREDEFINED, 1441 TF_TYPE_DISTRIBUTED_POINTS, 1442 TF_TYPE_BYPASS, 1443 TF_TYPE_HWPWL 1444 }; 1445 1446 struct dc_transfer_func_distributed_points { 1447 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1448 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1449 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1450 1451 uint16_t end_exponent; 1452 uint16_t x_point_at_y1_red; 1453 uint16_t x_point_at_y1_green; 1454 uint16_t x_point_at_y1_blue; 1455 }; 1456 1457 enum dc_transfer_func_predefined { 1458 TRANSFER_FUNCTION_SRGB, 1459 TRANSFER_FUNCTION_BT709, 1460 TRANSFER_FUNCTION_PQ, 1461 TRANSFER_FUNCTION_LINEAR, 1462 TRANSFER_FUNCTION_UNITY, 1463 TRANSFER_FUNCTION_HLG, 1464 TRANSFER_FUNCTION_HLG12, 1465 TRANSFER_FUNCTION_GAMMA22, 1466 TRANSFER_FUNCTION_GAMMA24, 1467 TRANSFER_FUNCTION_GAMMA26 1468 }; 1469 1470 1471 struct dc_transfer_func { 1472 struct kref refcount; 1473 enum dc_transfer_func_type type; 1474 enum dc_transfer_func_predefined tf; 1475 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1476 uint32_t sdr_ref_white_level; 1477 struct fixed31_32 hdr_multiplier; 1478 union { 1479 struct pwl_params pwl; 1480 struct dc_transfer_func_distributed_points tf_pts; 1481 }; 1482 }; 1483 1484 1485 union dc_3dlut_state { 1486 struct { 1487 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1488 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1489 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1490 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1491 uint32_t mpc_rmu1_mux:4; 1492 uint32_t mpc_rmu2_mux:4; 1493 uint32_t reserved:15; 1494 } bits; 1495 uint32_t raw; 1496 }; 1497 1498 1499 #define MATRIX_9C__DIM_128_ALIGNED_LEN 16 // 9+8 : 9 * 8 + 7 * 8 = 72 + 56 = 128 % 128 = 0 1500 #define MATRIX_17C__DIM_128_ALIGNED_LEN 32 //17+15: 17 * 8 + 15 * 8 = 136 + 120 = 256 % 128 = 0 1501 #define MATRIX_33C__DIM_128_ALIGNED_LEN 64 //17+47: 17 * 8 + 47 * 8 = 136 + 376 = 512 % 128 = 0 1502 1503 struct lut_rgb { 1504 uint16_t b; 1505 uint16_t g; 1506 uint16_t r; 1507 uint16_t padding; 1508 }; 1509 1510 //this structure maps directly to how the lut will read it from memory 1511 struct lut_mem_mapping { 1512 union { 1513 //NATIVE MODE 1, 2 1514 //RGB layout [b][g][r] //red is 128 byte aligned 1515 //BGR layout [r][g][b] //blue is 128 byte aligned 1516 struct lut_rgb rgb_17c[17][17][MATRIX_17C__DIM_128_ALIGNED_LEN]; 1517 struct lut_rgb rgb_33c[33][33][MATRIX_33C__DIM_128_ALIGNED_LEN]; 1518 1519 //TRANSFORMED 1520 uint16_t linear_rgb[(33*33*33*4/128+1)*128]; 1521 }; 1522 uint16_t size; 1523 }; 1524 1525 struct dc_3dlut { 1526 struct kref refcount; 1527 struct tetrahedral_params lut_3d; 1528 union dc_3dlut_state state; 1529 }; 1530 1531 /* 3DLUT DMA (Fast Load) params */ 1532 struct dc_3dlut_dma { 1533 struct dc_plane_address addr; 1534 enum dc_cm_lut_swizzle swizzle; 1535 enum dc_cm_lut_pixel_format format; 1536 uint16_t bias; /* FP1.5.10 */ 1537 uint16_t scale; /* FP1.5.10 */ 1538 enum dc_cm_lut_size size; 1539 }; 1540 1541 /* color manager */ 1542 union dc_plane_cm_flags { 1543 unsigned int all; 1544 struct { 1545 unsigned int shaper_enable : 1; 1546 unsigned int lut3d_enable : 1; 1547 unsigned int blend_enable : 1; 1548 /* whether legacy (lut3d_func) or DMA is valid */ 1549 unsigned int lut3d_dma_enable : 1; 1550 /* RMCM lut to be used instead of MCM */ 1551 unsigned int rmcm_enable : 1; 1552 unsigned int reserved: 27; 1553 } bits; 1554 }; 1555 1556 struct dc_plane_cm { 1557 struct kref refcount; 1558 struct dc_transfer_func shaper_func; 1559 union { 1560 struct dc_3dlut lut3d_func; 1561 struct dc_3dlut_dma lut3d_dma; 1562 }; 1563 struct dc_transfer_func blend_func; 1564 union dc_plane_cm_flags flags; 1565 }; 1566 1567 /* 1568 * This structure is filled in by dc_surface_get_status and contains 1569 * the last requested address and the currently active address so the called 1570 * can determine if there are any outstanding flips 1571 */ 1572 struct dc_plane_status { 1573 struct dc_plane_address requested_address; 1574 struct dc_plane_address current_address; 1575 bool is_flip_pending; 1576 bool is_right_eye; 1577 struct cm_hist cm_hist; 1578 }; 1579 1580 struct pipe_update_bits { 1581 uint32_t addr_update:1; 1582 uint32_t dcc_change:1; 1583 uint32_t color_space_change:1; 1584 uint32_t horizontal_mirror_change:1; 1585 uint32_t per_pixel_alpha_change:1; 1586 uint32_t global_alpha_change:1; 1587 uint32_t hdr_mult:1; 1588 uint32_t rotation_change:1; 1589 uint32_t swizzle_change:1; 1590 uint32_t scaling_change:1; 1591 uint32_t position_change:1; 1592 uint32_t in_transfer_func_change:1; 1593 uint32_t input_csc_change:1; 1594 uint32_t coeff_reduction_change:1; 1595 uint32_t pixel_format_change:1; 1596 uint32_t plane_size_change:1; 1597 uint32_t gamut_remap_change:1; 1598 uint32_t cursor_csc_color_matrix_change:1; 1599 uint32_t new_plane:1; 1600 uint32_t bpp_change:1; 1601 uint32_t gamma_change:1; 1602 uint32_t bandwidth_change:1; 1603 uint32_t clock_change:1; 1604 uint32_t stereo_format_change:1; 1605 uint32_t lut_3d:1; 1606 uint32_t tmz_changed:1; 1607 uint32_t full_update:1; 1608 uint32_t sdr_white_level_nits:1; 1609 uint32_t cm_hist_change:1; 1610 /* NOTE: When adding a new field, also update: 1611 * - dc_pipe_update_bits_set_full() 1612 * - dc_pipe_update_bits_is_any_set() 1613 */ 1614 }; 1615 1616 static inline void dc_pipe_update_bits_clear(struct pipe_update_bits *flags) 1617 { 1618 /* memset ensures padding bits are zeroed */ 1619 memset(flags, 0, sizeof(*flags)); 1620 } 1621 1622 static inline void dc_pipe_update_bits_set_full(struct pipe_update_bits *flags) 1623 { 1624 dc_pipe_update_bits_clear(flags); 1625 flags->addr_update = 1; 1626 flags->dcc_change = 1; 1627 flags->color_space_change = 1; 1628 flags->horizontal_mirror_change = 1; 1629 flags->per_pixel_alpha_change = 1; 1630 flags->global_alpha_change = 1; 1631 flags->hdr_mult = 1; 1632 flags->rotation_change = 1; 1633 flags->swizzle_change = 1; 1634 flags->scaling_change = 1; 1635 flags->position_change = 1; 1636 flags->in_transfer_func_change = 1; 1637 flags->input_csc_change = 1; 1638 flags->coeff_reduction_change = 1; 1639 flags->pixel_format_change = 1; 1640 flags->plane_size_change = 1; 1641 flags->gamut_remap_change = 1; 1642 flags->cursor_csc_color_matrix_change = 1; 1643 flags->new_plane = 1; 1644 flags->bpp_change = 1; 1645 flags->gamma_change = 1; 1646 flags->bandwidth_change = 1; 1647 flags->clock_change = 1; 1648 flags->stereo_format_change = 1; 1649 flags->lut_3d = 1; 1650 flags->tmz_changed = 1; 1651 flags->full_update = 1; 1652 flags->sdr_white_level_nits = 1; 1653 flags->cm_hist_change = 1; 1654 } 1655 1656 static inline bool dc_pipe_update_bits_is_any_set(const struct pipe_update_bits *flags) 1657 { 1658 return flags->addr_update || 1659 flags->dcc_change || 1660 flags->color_space_change || 1661 flags->horizontal_mirror_change || 1662 flags->per_pixel_alpha_change || 1663 flags->global_alpha_change || 1664 flags->hdr_mult || 1665 flags->rotation_change || 1666 flags->swizzle_change || 1667 flags->scaling_change || 1668 flags->position_change || 1669 flags->in_transfer_func_change || 1670 flags->input_csc_change || 1671 flags->coeff_reduction_change || 1672 flags->pixel_format_change || 1673 flags->plane_size_change || 1674 flags->gamut_remap_change || 1675 flags->cursor_csc_color_matrix_change || 1676 flags->new_plane || 1677 flags->bpp_change || 1678 flags->gamma_change || 1679 flags->bandwidth_change || 1680 flags->clock_change || 1681 flags->stereo_format_change || 1682 flags->lut_3d || 1683 flags->tmz_changed || 1684 flags->full_update || 1685 flags->sdr_white_level_nits || 1686 flags->cm_hist_change; 1687 } 1688 1689 bool dc_check_address_only_update(struct pipe_update_bits update_bits); 1690 1691 #define DC_REMOVE_PLANE_POINTERS 1 1692 1693 struct dc_plane_state { 1694 struct dc_plane_address address; 1695 struct dc_plane_flip_time time; 1696 bool triplebuffer_flips; 1697 struct scaling_taps scaling_quality; 1698 struct rect src_rect; 1699 struct rect dst_rect; 1700 struct rect clip_rect; 1701 1702 struct plane_size plane_size; 1703 struct dc_tiling_info tiling_info; 1704 1705 struct dc_plane_dcc_param dcc; 1706 1707 struct dc_gamma gamma_correction; 1708 struct dc_transfer_func in_transfer_func; 1709 struct dc_bias_and_scale bias_and_scale; 1710 struct dc_csc_transform input_csc_color_matrix; 1711 struct fixed31_32 coeff_reduction_factor; 1712 struct fixed31_32 hdr_mult; 1713 struct colorspace_transform gamut_remap_matrix; 1714 1715 enum dc_color_space color_space; 1716 1717 #ifndef TRIM_CM2 1718 bool lut_bank_a; 1719 struct dc_hdr_static_metadata hdr_static_ctx; 1720 struct dc_3dlut lut3d_func; 1721 struct dc_transfer_func in_shaper_func; 1722 struct dc_transfer_func blend_tf; 1723 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1724 bool mcm_lut1d_enable; 1725 struct dc_cm2_func_luts mcm_luts; 1726 enum mpcc_movable_cm_location mcm_location; 1727 #endif /* TRIM_CM2 */ 1728 struct dc_plane_cm cm; 1729 1730 struct dc_transfer_func *gamcor_tf; 1731 enum surface_pixel_format format; 1732 enum dc_rotation_angle rotation; 1733 enum plane_stereo_format stereo_format; 1734 1735 bool is_tiling_rotated; 1736 bool per_pixel_alpha; 1737 bool pre_multiplied_alpha; 1738 bool global_alpha; 1739 int global_alpha_value; 1740 bool visible; 1741 bool flip_immediate; 1742 bool horizontal_mirror; 1743 unsigned int layer_index; 1744 1745 struct pipe_update_bits update_bits; 1746 bool flip_int_enabled; 1747 bool skip_manual_trigger; 1748 1749 /* private to DC core */ 1750 struct dc_plane_status status; 1751 struct dc_context *ctx; 1752 1753 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1754 bool force_full_update; 1755 1756 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1757 1758 /* private to dc_surface.c */ 1759 enum dc_irq_source irq_source; 1760 struct kref refcount; 1761 struct tg_color visual_confirm_color; 1762 1763 bool is_statically_allocated; 1764 enum chroma_cositing cositing; 1765 struct dc_csc_transform cursor_csc_color_matrix; 1766 bool adaptive_sharpness_en; 1767 int adaptive_sharpness_policy; 1768 unsigned int sharpness_level; 1769 enum dc_scaling_linearity scaling_linearity; 1770 unsigned int sdr_white_level_nits; 1771 struct cm_hist_control cm_hist_control; 1772 struct spl_sharpness_range sharpness_range; 1773 enum sharpness_range_source sharpness_source; 1774 }; 1775 1776 struct dc_plane_info { 1777 struct plane_size plane_size; 1778 struct dc_tiling_info tiling_info; 1779 struct dc_plane_dcc_param dcc; 1780 enum surface_pixel_format format; 1781 enum dc_rotation_angle rotation; 1782 enum plane_stereo_format stereo_format; 1783 enum dc_color_space color_space; 1784 bool horizontal_mirror; 1785 bool visible; 1786 bool per_pixel_alpha; 1787 bool pre_multiplied_alpha; 1788 bool global_alpha; 1789 int global_alpha_value; 1790 bool input_csc_enabled; 1791 unsigned int layer_index; 1792 enum chroma_cositing cositing; 1793 enum dc_scaling_linearity scaling_linearity; 1794 }; 1795 1796 #include "dc_stream.h" 1797 1798 struct dc_scratch_space { 1799 /* used to temporarily backup plane states of a stream during 1800 * dc update. The reason is that plane states are overwritten 1801 * with surface updates in dc update. Once they are overwritten 1802 * current state is no longer valid. We want to temporarily 1803 * store current value in plane states so we can still recover 1804 * a valid current state during dc update. 1805 */ 1806 struct dc_plane_state plane_states[MAX_SURFACES]; 1807 1808 struct dc_stream_state stream_state; 1809 }; 1810 1811 /* 1812 * A link contains one or more sinks and their connected status. 1813 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1814 */ 1815 struct dc_link { 1816 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1817 unsigned int sink_count; 1818 struct dc_sink *local_sink; 1819 unsigned int link_index; 1820 enum dc_connection_type type; 1821 enum signal_type connector_signal; 1822 enum dc_irq_source irq_source_hpd; 1823 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1824 enum dc_irq_source irq_source_read_request;/* Read Request */ 1825 1826 bool is_hpd_filter_disabled; 1827 bool dp_ss_off; 1828 1829 /** 1830 * @link_state_valid: 1831 * 1832 * If there is no link and local sink, this variable should be set to 1833 * false. Otherwise, it should be set to true; usually, the function 1834 * core_link_enable_stream sets this field to true. 1835 */ 1836 bool link_state_valid; 1837 bool aux_access_disabled; 1838 bool sync_lt_in_progress; 1839 bool skip_stream_reenable; 1840 bool is_internal_display; 1841 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1842 bool is_dig_mapping_flexible; 1843 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1844 bool is_hpd_pending; /* Indicates a new received hpd */ 1845 1846 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1847 * for every link training. This is incompatible with DP LL compliance automation, 1848 * which expects the same link settings to be used every retry on a link loss. 1849 * This flag is used to skip the fallback when link loss occurs during automation. 1850 */ 1851 bool skip_fallback_on_link_loss; 1852 1853 bool edp_sink_present; 1854 1855 struct dp_trace dp_trace; 1856 volatile bool is_link_locked; 1857 1858 /* caps is the same as reported_link_cap. link_traing use 1859 * reported_link_cap. Will clean up. TODO 1860 */ 1861 struct dc_link_settings reported_link_cap; 1862 struct dc_link_settings verified_link_cap; 1863 struct dc_link_settings cur_link_settings; 1864 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1865 struct dc_link_settings preferred_link_setting; 1866 /* preferred_training_settings are override values that 1867 * come from DM. DM is responsible for the memory 1868 * management of the override pointers. 1869 */ 1870 struct dc_link_training_overrides preferred_training_settings; 1871 struct dc_hdmi_frl_link_training_overrides preferred_hdmi_frl_settings; 1872 struct dp_audio_test_data audio_test_data; 1873 1874 /* On ASICs with dp_connector_no_native_i2c cap set and no_ddc_pin cap 1875 * set by IFWI, link aux_hw_inst is used in aux layer functions instead 1876 * of ddc_pin to know which aux instance is associated with link. 1877 */ 1878 bool no_ddc_pin; 1879 /** When set, forces all native I2C communication on this DP connector 1880 * to use the I2C-over-AUX protocol instead of native I2C signaling. 1881 */ 1882 bool force_to_use_aux; 1883 enum gpio_ddc_line aux_hw_inst; 1884 1885 enum gpio_ddc_line ddc_hw_inst; 1886 1887 uint8_t hpd_src; 1888 1889 uint8_t link_enc_hw_inst; 1890 /* DIG link encoder ID. Used as index in link encoder resource pool. 1891 * For links with fixed mapping to DIG, this is not changed after dc_link 1892 * object creation. 1893 */ 1894 enum engine_id eng_id; 1895 enum engine_id dpia_preferred_eng_id; 1896 1897 bool test_pattern_enabled; 1898 /* Pending/Current test pattern are only used to perform and track 1899 * FIXED_VS retimer test pattern/lane adjustment override state. 1900 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1901 * to perform specific lane adjust overrides before setting certain 1902 * PHY test patterns. In cases when lane adjust and set test pattern 1903 * calls are not performed atomically (i.e. performing link training), 1904 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1905 * and current_test_pattern will contain required context for any future 1906 * set pattern/set lane adjust to transition between override state(s). 1907 * */ 1908 enum dp_test_pattern current_test_pattern; 1909 enum dp_test_pattern pending_test_pattern; 1910 1911 union compliance_test_state compliance_test_state; 1912 1913 void *priv; 1914 1915 struct ddc_service *ddc; 1916 1917 enum dp_panel_mode panel_mode; 1918 bool panel_mode_initialized; 1919 bool aux_mode; 1920 1921 /* Private to DC core */ 1922 1923 const struct dc *dc; 1924 1925 struct dc_context *ctx; 1926 1927 struct panel_cntl *panel_cntl; 1928 struct link_encoder *link_enc; 1929 struct hpo_frl_link_encoder *hpo_frl_link_enc; 1930 struct dc_hdmi_frl_link_settings frl_reported_link_cap; 1931 struct dc_hdmi_frl_link_settings frl_verified_link_cap; 1932 struct dc_hdmi_frl_link_settings frl_link_settings; 1933 struct dc_hdmi_frl_flags frl_flags; 1934 union hdmi_idcc_cable_id hdmi_cable_id; 1935 struct graphics_object_id link_id; 1936 1937 /* External encoder eg. NUTMEG or TRAVIS used on CIK APUs. */ 1938 struct graphics_object_id ext_enc_id; 1939 1940 /* Endpoint type distinguishes display endpoints which do not have entries 1941 * in the BIOS connector table from those that do. Helps when tracking link 1942 * encoder to display endpoint assignments. 1943 */ 1944 enum display_endpoint_type ep_type; 1945 union ddi_channel_mapping ddi_channel_mapping; 1946 struct connector_device_tag_info device_tag; 1947 struct dpcd_caps dpcd_caps; 1948 uint32_t dongle_max_pix_clk; 1949 unsigned short chip_caps; 1950 unsigned int dpcd_sink_count; 1951 struct hdcp_caps hdcp_caps; 1952 enum edp_revision edp_revision; 1953 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1954 1955 struct psr_settings psr_settings; 1956 struct replay_settings replay_settings; 1957 1958 /* Drive settings read from integrated info table */ 1959 struct dc_lane_settings bios_forced_drive_settings; 1960 1961 /* Vendor specific LTTPR workaround variables */ 1962 uint8_t vendor_specific_lttpr_link_rate_wa; 1963 bool apply_vendor_specific_lttpr_link_rate_wa; 1964 1965 /* MST record stream using this link */ 1966 struct link_flags { 1967 bool dp_keep_receiver_powered; 1968 bool dp_skip_DID2; 1969 bool dp_skip_reset_segment; 1970 bool dp_skip_fs_144hz; 1971 /* Some DP bridges don't work with RBR and must use HBR. */ 1972 bool dp_skip_rbr; 1973 bool dp_mot_reset_segment; 1974 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1975 bool dpia_mst_dsc_always_on; 1976 /* Forced DPIA into TBT3 compatibility mode. */ 1977 bool dpia_forced_tbt3_mode; 1978 bool dongle_mode_timing_override; 1979 bool blank_stream_on_ocs_change; 1980 bool read_dpcd204h_on_irq_hpd; 1981 bool force_dp_ffe_preset; 1982 bool skip_phy_ssc_reduction; 1983 } wa_flags; 1984 union dc_dp_ffe_preset forced_dp_ffe_preset; 1985 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1986 1987 struct dc_link_status link_status; 1988 struct dprx_states dprx_states; 1989 1990 enum dc_link_fec_state fec_state; 1991 bool is_dds; 1992 bool is_display_mux_present; 1993 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1994 1995 struct dc_panel_config panel_config; 1996 enum dc_panel_type panel_type; 1997 struct phy_state phy_state; 1998 uint32_t phy_transition_bitmask; 1999 // BW ALLOCATON USB4 ONLY 2000 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 2001 bool skip_implict_edp_power_control; 2002 bool forced_psr_active; 2003 enum backlight_control_type backlight_control_type; 2004 }; 2005 2006 struct dc { 2007 struct dc_debug_options debug; 2008 struct dc_versions versions; 2009 struct dc_caps caps; 2010 struct dc_check_config check_config; 2011 struct dc_cap_funcs cap_funcs; 2012 struct dc_config config; 2013 struct dc_bounding_box_overrides bb_overrides; 2014 struct dc_bug_wa work_arounds; 2015 struct dc_context *ctx; 2016 struct dc_phy_addr_space_config vm_pa_config; 2017 2018 uint8_t link_count; 2019 struct dc_link *links[MAX_LINKS]; 2020 uint8_t lowest_dpia_link_index; 2021 struct link_service *link_srv; 2022 2023 struct dc_state *current_state; 2024 struct resource_pool *res_pool; 2025 2026 /** 2027 * @update_scratch_pool: Per-commit scratch buffers for dc_update_state. 2028 */ 2029 struct dc_update_scratch_space *update_scratch_pool[MAX_STREAMS + 1]; 2030 bool update_scratch_in_use[MAX_STREAMS + 1]; 2031 2032 struct clk_mgr *clk_mgr; 2033 2034 /* Display Engine Clock levels */ 2035 struct dm_pp_clock_levels sclk_lvls; 2036 2037 /* Inputs into BW and WM calculations. */ 2038 struct bw_calcs_dceip *bw_dceip; 2039 struct bw_calcs_vbios *bw_vbios; 2040 struct dcn_soc_bounding_box *dcn_soc; 2041 struct dcn_ip_params *dcn_ip; 2042 struct display_mode_lib dml; 2043 2044 /* HW functions */ 2045 struct hw_sequencer_funcs hwss; 2046 struct dce_hwseq *hwseq; 2047 2048 /* Require to optimize clocks and bandwidth for added/removed planes */ 2049 bool optimized_required; 2050 bool idle_optimizations_allowed; 2051 bool enable_c20_dtm_b0; 2052 2053 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 2054 2055 /* For eDP to know the switching state of SmartMux */ 2056 bool is_switch_in_progress_orig; 2057 bool is_switch_in_progress_dest; 2058 2059 /* FBC compressor */ 2060 struct compressor *fbc_compressor; 2061 2062 struct dc_debug_data debug_data; 2063 struct dpcd_vendor_signature vendor_signature; 2064 2065 const char *build_id; 2066 struct vm_helper *vm_helper; 2067 2068 uint32_t *dcn_reg_offsets; 2069 uint32_t *nbio_reg_offsets; 2070 uint32_t *clk_reg_offsets; 2071 2072 /* Scratch memory */ 2073 struct { 2074 struct { 2075 /* 2076 * For matching clock_limits table in driver with table 2077 * from PMFW. 2078 */ 2079 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 2080 } update_bw_bounding_box; 2081 struct dc_scratch_space current_state; 2082 struct dc_scratch_space new_state; 2083 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 2084 struct dc_link temp_link; 2085 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 2086 } scratch; 2087 2088 struct dml2_configuration_options dml2_options; 2089 struct dml2_configuration_options dml2_dc_power_options; 2090 enum dc_acpi_cm_power_state power_state; 2091 struct soc_and_ip_translator *soc_and_ip_translator; 2092 }; 2093 2094 struct dc_scaling_info { 2095 struct rect src_rect; 2096 struct rect dst_rect; 2097 struct rect clip_rect; 2098 struct scaling_taps scaling_quality; 2099 }; 2100 2101 struct dc_surface_update { 2102 struct dc_plane_state *surface; 2103 2104 /* isr safe update parameters. null means no updates */ 2105 const struct dc_flip_addrs *flip_addr; 2106 const struct dc_plane_info *plane_info; 2107 const struct dc_scaling_info *scaling_info; 2108 struct fixed31_32 hdr_mult; 2109 /* following updates require alloc/sleep/spin that is not isr safe, 2110 * null means no updates 2111 */ 2112 const struct dc_gamma *gamma; 2113 const struct dc_transfer_func *in_transfer_func; 2114 2115 const struct dc_csc_transform *input_csc_color_matrix; 2116 const struct fixed31_32 *coeff_reduction_factor; 2117 const struct colorspace_transform *gamut_remap_matrix; 2118 const struct dc_plane_cm *cm; 2119 const struct dc_csc_transform *cursor_csc_color_matrix; 2120 unsigned int sdr_white_level_nits; 2121 struct dc_bias_and_scale bias_and_scale; 2122 struct cm_hist_control *cm_hist_control; 2123 }; 2124 2125 struct dc_state_update { 2126 struct dc_stream_state *stream; 2127 struct dc_stream_update *stream_update; 2128 struct dc_surface_update *surface_updates; 2129 int surface_count; 2130 const struct dc_probe_updates *probe_updates; 2131 }; 2132 2133 /** 2134 * dc_check_state_update() - Classify an update without committing it. 2135 * @check_config: DC check configuration 2136 * @updates: root update object to classify 2137 * 2138 * Return: descriptor indicating update type and required lock scope. 2139 */ 2140 struct dc_update_descriptor dc_check_state_update( 2141 const struct dc_check_config *check_config, 2142 const struct dc_state_update *updates); 2143 2144 /** 2145 * dc_update_state - Commit an absolute dc_state_update. 2146 * @dc: DC structure 2147 * @updates: root update object carrying stream, plane, and probe updates 2148 * 2149 * Return: true on success, false on failure. 2150 */ 2151 bool dc_update_state(struct dc *dc, const struct dc_state_update *updates); 2152 2153 struct dc_update_scratch_space; 2154 2155 /** 2156 * dc_update_state_init - Acquire and initialise a commit scratch buffer. 2157 * @dc: DC structure 2158 * @updates: update descriptor; validated before the slot is acquired 2159 * 2160 * Return: a scratch slot on success, NULL if validation fails or the pool 2161 * is exhausted. The slot must be released via dc_update_state_cleanup() on 2162 * success, or automatically by dc_update_state_prepare() on failure. 2163 */ 2164 struct dc_update_scratch_space *dc_update_state_init( 2165 struct dc *dc, 2166 const struct dc_state_update *updates 2167 ); 2168 2169 /** 2170 * dc_update_state_prepare - Prepare the commit under the global lock. 2171 * @scratch: commit scratch from dc_update_state_init() 2172 * 2173 * On failure the scratch slot is released and false is returned; the caller 2174 * must not call execute or cleanup. 2175 */ 2176 bool dc_update_state_prepare(struct dc_update_scratch_space *scratch); 2177 2178 /** 2179 * dc_update_state_execute - Program hardware; called without the global lock. 2180 * @scratch: commit scratch from dc_update_state_init() 2181 */ 2182 void dc_update_state_execute(const struct dc_update_scratch_space *scratch); 2183 2184 /** 2185 * dc_update_state_cleanup - Finalise the commit and release the scratch slot. 2186 * @scratch: commit scratch from dc_update_state_init() 2187 * 2188 * Must be called with the global lock held. Returns true if the caller must 2189 * loop back to prepare (SEAMLESS continuation). 2190 */ 2191 bool dc_update_state_cleanup(struct dc_update_scratch_space *scratch); 2192 2193 /** 2194 * struct dc_probe_latencies - min/max/avg memory latency in ns. 2195 * @max_latency_ns: maximum latency in nanoseconds 2196 * @avg_latency_ns: average latency in nanoseconds 2197 * @min_latency_ns: minimum latency in nanoseconds 2198 */ 2199 struct dc_probe_latencies { 2200 uint32_t max_latency_ns; 2201 uint32_t avg_latency_ns; 2202 uint32_t min_latency_ns; 2203 }; 2204 2205 /** 2206 * struct dc_probe_status - results for a probe. 2207 * @valid: true if a measurement was latched. 2208 * @measuring: true if the hardware counter is currently running. 2209 * @type: type of the probe that produced this result. 2210 * @u.bandwidth_mbps: peak BW in Mbps (DC_PROBE_PEAK_MEM_BW). 2211 * @u.latency: min/max/avg memory latency in ns (DC_PROBE_MEM_LATENCY), 2212 * stored as struct dc_probe_latencies. 2213 * @u.urgent_assertion_count: number of urgent assertion events (DC_PROBE_URGENT_ASSERTION_COUNT). 2214 * @u.prefetch_data_size: total prefetch data in bytes (DC_PROBE_PREFETCH_DATA_SIZE). 2215 */ 2216 struct dc_probe_status { 2217 bool valid; 2218 bool measuring; 2219 enum dc_probe_type type; 2220 union { 2221 uint32_t bandwidth_mbps; 2222 struct dc_probe_latencies latency; 2223 uint32_t urgent_assertion_count; 2224 uint32_t prefetch_data_size; 2225 } u; 2226 }; 2227 2228 /** 2229 * enum dc_get_status_type - Bitmask selecting which status classes to populate. 2230 * @DC_GET_STATUS_STREAM: populate stream_status fields in dc_state_status 2231 * @DC_GET_STATUS_PROBE: populate probe_status fields in dc_state_status 2232 */ 2233 enum dc_get_status_type { 2234 DC_GET_STATUS_STREAM = (1u << 0), 2235 DC_GET_STATUS_PROBE = (1u << 1), 2236 }; 2237 2238 /** 2239 * struct dc_get_status_options - Input selector for dc_state_get_status. 2240 * @state: source state to read status from 2241 * @types: OR of dc_get_status_type values selecting classes to populate 2242 * @stream: optional stream filter for DC_GET_STATUS_STREAM. NULL means 2243 * populate status for all streams in the state 2244 * @probe: optional probe filter for DC_GET_STATUS_PROBE. NULL means 2245 * populate status for all probes in the state 2246 */ 2247 struct dc_get_status_options { 2248 struct dc_state *state; 2249 uint32_t types; 2250 const struct dc_stream_state *stream; 2251 const struct dc_probe_state *probe; 2252 }; 2253 2254 /** 2255 * struct dc_state_status - Output-only status object from dc_state_get_status. 2256 * @stream_count: number of valid entries in stream_status (DC_GET_STATUS_STREAM) 2257 * @stream_status: pointers to live per-stream status entries 2258 * @probe_count: number of valid entries in probe_status (DC_GET_STATUS_PROBE) 2259 * @probe_status: pointers to live per-probe status entries 2260 */ 2261 struct dc_state_status { 2262 int stream_count; 2263 struct dc_stream_status *stream_status[MAX_STREAMS]; 2264 int probe_count; 2265 struct dc_probe_status *probe_status[MAX_PROBES]; 2266 }; 2267 2268 /** 2269 * dc_state_get_status - Unified status readback for dc_state. 2270 * @status: output object populated according to options->types 2271 * @options: selects the source state, status classes to fill, and filters 2272 * 2273 * Return: DC_OK on success, DC_ERROR_UNEXPECTED if state is NULL. 2274 */ 2275 enum dc_status dc_state_get_status(struct dc_state_status *status, 2276 const struct dc_get_status_options *options); 2277 2278 struct dc_underflow_debug_data { 2279 struct dcn_hubbub_reg_state *hubbub_reg_state; 2280 struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES]; 2281 struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES]; 2282 struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES]; 2283 struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES]; 2284 struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES]; 2285 struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES]; 2286 struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES]; 2287 }; 2288 2289 struct power_features { 2290 bool ips; 2291 bool rcg; 2292 bool replay; 2293 bool dds; 2294 bool sprs; 2295 bool psr; 2296 bool fams; 2297 bool mpo; 2298 bool uclk_p_state; 2299 }; 2300 2301 /* 2302 * Create a new surface with default parameters; 2303 */ 2304 void dc_gamma_retain(struct dc_gamma *dc_gamma); 2305 void dc_gamma_release(struct dc_gamma **dc_gamma); 2306 struct dc_gamma *dc_create_gamma(void); 2307 2308 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 2309 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 2310 struct dc_transfer_func *dc_create_transfer_func(void); 2311 2312 struct dc_3dlut *dc_create_3dlut_func(void); 2313 void dc_3dlut_func_release(struct dc_3dlut *lut); 2314 void dc_3dlut_func_retain(struct dc_3dlut *lut); 2315 2316 struct dc_plane_cm *dc_plane_cm_create(void); 2317 void dc_plane_cm_release(struct dc_plane_cm *cm); 2318 void dc_plane_cm_retain(struct dc_plane_cm *cm); 2319 2320 void dc_post_update_surfaces_to_stream( 2321 struct dc *dc); 2322 2323 /* 2324 * dc_get_default_tiling_info() - Retrieve an ASIC-appropriate default tiling 2325 * description for (typically) linear surfaces. 2326 * 2327 * This is used by OS/DM paths that need a valid, fully-initialized tiling 2328 * description without hardcoding gfx-version specifics in the caller. 2329 */ 2330 void dc_get_default_tiling_info(const struct dc *dc, struct dc_tiling_info *tiling_info); 2331 2332 /** 2333 * struct dc_validation_stream - Per-stream surface/stream association for validation 2334 */ 2335 struct dc_validation_stream { 2336 /** 2337 * @stream: Stream state properties 2338 */ 2339 struct dc_stream_state *stream; 2340 2341 /** 2342 * @plane_states: Surface state 2343 */ 2344 struct dc_plane_state *plane_states[MAX_SURFACES]; 2345 2346 /** 2347 * @plane_count: Total of active planes 2348 */ 2349 uint8_t plane_count; 2350 }; 2351 2352 /** 2353 * struct dc_validation_set - Root validation input grouping all streams for a commit 2354 */ 2355 struct dc_validation_set { 2356 /** 2357 * @streams: Per-stream entries (stream + its planes) 2358 */ 2359 struct dc_validation_stream streams[MAX_STREAMS]; 2360 2361 /** 2362 * @stream_count: Number of active entries in @streams 2363 */ 2364 uint8_t stream_count; 2365 2366 /** 2367 * @probes: Global probe descriptors to validate alongside the streams 2368 */ 2369 struct dc_probe_state probes[MAX_PROBES]; 2370 2371 /** 2372 * @probe_count: Number of active entries in @probes 2373 */ 2374 uint8_t probe_count; 2375 }; 2376 2377 bool dc_validate_boot_timing(const struct dc *dc, 2378 const struct dc_sink *sink, 2379 struct dc_crtc_timing *crtc_timing); 2380 2381 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 2382 2383 enum dc_status dc_validate_with_context(struct dc *dc, 2384 const struct dc_validation_set *set, 2385 struct dc_state *context, 2386 enum dc_validate_mode validate_mode); 2387 2388 bool dc_set_generic_gpio_for_stereo(bool enable, 2389 struct gpio_service *gpio_service); 2390 2391 enum dc_status dc_validate_global_state( 2392 struct dc *dc, 2393 struct dc_state *new_ctx, 2394 enum dc_validate_mode validate_mode); 2395 2396 bool dc_acquire_release_mpc_3dlut( 2397 struct dc *dc, bool acquire, 2398 struct dc_stream_state *stream, 2399 struct dc_3dlut **lut, 2400 struct dc_transfer_func **shaper); 2401 2402 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 2403 void get_audio_check(struct audio_info *aud_modes, 2404 struct audio_check *aud_chk); 2405 2406 /* 2407 * Set up streams and links associated to drive sinks 2408 * The streams parameter is an absolute set of all active streams. 2409 * 2410 * After this call: 2411 * Phy, Encoder, Timing Generator are programmed and enabled. 2412 * New streams are enabled with blank stream; no memory read. 2413 */ 2414 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 2415 2416 2417 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 2418 struct dc_stream_state *stream, 2419 int mpcc_inst); 2420 2421 2422 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 2423 bool dc_set_fva_vrr_adjust(struct dc *dc, 2424 struct dc_stream_state *stream, 2425 struct fva_adj *fva_adj, 2426 struct dc_crtc_timing_adjust *vrr_adj); 2427 2428 int dc_get_hw_max_fva_factor(struct dc *dc, 2429 struct dc_stream_state *stream, 2430 unsigned int max_pixel_clock); 2431 2432 void dc_set_vstartup_start(struct dc *dc, 2433 struct dc_stream_state *stream); 2434 2435 void dc_set_disable_128b_132b_stream_overhead(bool disable); 2436 2437 /* The function returns minimum bandwidth required to drive a given timing 2438 * return - minimum required timing bandwidth in kbps. 2439 */ 2440 uint32_t dc_bandwidth_in_kbps_from_timing( 2441 const struct dc_crtc_timing *timing, 2442 const enum dc_link_encoding_format link_encoding); 2443 2444 /* Link Interfaces */ 2445 /* Return an enumerated dc_link. 2446 * dc_link order is constant and determined at 2447 * boot time. They cannot be created or destroyed. 2448 * Use dc_get_caps() to get number of links. 2449 */ 2450 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 2451 2452 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 2453 bool dc_get_edp_link_panel_inst(const struct dc *dc, 2454 const struct dc_link *link, 2455 unsigned int *inst_out); 2456 2457 /* Return an array of link pointers to edp links. */ 2458 void dc_get_edp_links(const struct dc *dc, 2459 struct dc_link **edp_links, 2460 unsigned int *edp_num); 2461 2462 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 2463 bool powerOn); 2464 2465 /* The function initiates detection handshake over the given link. It first 2466 * determines if there are display connections over the link. If so it initiates 2467 * detection protocols supported by the connected receiver device. The function 2468 * contains protocol specific handshake sequences which are sometimes mandatory 2469 * to establish a proper connection between TX and RX. So it is always 2470 * recommended to call this function as the first link operation upon HPD event 2471 * or power up event. Upon completion, the function will update link structure 2472 * in place based on latest RX capabilities. The function may also cause dpms 2473 * to be reset to off for all currently enabled streams to the link. It is DM's 2474 * responsibility to serialize detection and DPMS updates. 2475 * 2476 * @reason - Indicate which event triggers this detection. dc may customize 2477 * detection flow depending on the triggering events. 2478 * return false - if detection is not fully completed. This could happen when 2479 * there is an unrecoverable error during detection or detection is partially 2480 * completed (detection has been delegated to dm mst manager ie. 2481 * link->connection_type == dc_connection_mst_branch when returning false). 2482 * return true - detection is completed, link has been fully updated with latest 2483 * detection result. 2484 */ 2485 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 2486 2487 struct dc_sink_init_data; 2488 2489 /* When link connection type is dc_connection_mst_branch, remote sink can be 2490 * added to the link. The interface creates a remote sink and associates it with 2491 * current link. The sink will be retained by link until remove remote sink is 2492 * called. 2493 * 2494 * @dc_link - link the remote sink will be added to. 2495 * @edid - byte array of EDID raw data. 2496 * @len - size of the edid in byte 2497 * @init_data - 2498 */ 2499 struct dc_sink *dc_link_add_remote_sink( 2500 struct dc_link *dc_link, 2501 const uint8_t *edid, 2502 unsigned int len, 2503 struct dc_sink_init_data *init_data); 2504 2505 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 2506 * @link - link the sink should be removed from 2507 * @sink - sink to be removed. 2508 */ 2509 void dc_link_remove_remote_sink( 2510 struct dc_link *link, 2511 struct dc_sink *sink); 2512 2513 /* Enable HPD interrupt handler for a given link */ 2514 void dc_link_enable_hpd(const struct dc_link *link); 2515 2516 /* Disable HPD interrupt handler for a given link */ 2517 void dc_link_disable_hpd(const struct dc_link *link); 2518 2519 /* determine if there is a sink connected to the link 2520 * 2521 * @type - dc_connection_single if connected, dc_connection_none otherwise. 2522 * return - false if an unexpected error occurs, true otherwise. 2523 * 2524 * NOTE: This function doesn't detect downstream sink connections i.e 2525 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 2526 * return dc_connection_single if the branch device is connected despite of 2527 * downstream sink's connection status. 2528 */ 2529 bool dc_link_detect_connection_type(struct dc_link *link, 2530 enum dc_connection_type *type); 2531 2532 /* query current hpd pin value 2533 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 2534 * 2535 */ 2536 bool dc_link_get_hpd_state(struct dc_link *link); 2537 2538 /* Getter for cached link status from given link */ 2539 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 2540 2541 /* enable/disable hardware HPD filter. 2542 * 2543 * @link - The link the HPD pin is associated with. 2544 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 2545 * handler once after no HPD change has been detected within dc default HPD 2546 * filtering interval since last HPD event. i.e if display keeps toggling hpd 2547 * pulses within default HPD interval, no HPD event will be received until HPD 2548 * toggles have stopped. Then HPD event will be queued to irq handler once after 2549 * dc default HPD filtering interval since last HPD event. 2550 * 2551 * @enable = false - disable hardware HPD filter. HPD event will be queued 2552 * immediately to irq handler after no HPD change has been detected within 2553 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 2554 */ 2555 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 2556 2557 /* submit i2c read/write payloads through ddc channel 2558 * @link_index - index to a link with ddc in i2c mode 2559 * @cmd - i2c command structure 2560 * return - true if success, false otherwise. 2561 */ 2562 bool dc_submit_i2c( 2563 struct dc *dc, 2564 uint32_t link_index, 2565 struct i2c_command *cmd); 2566 2567 /* submit i2c read/write payloads through oem channel 2568 * @link_index - index to a link with ddc in i2c mode 2569 * @cmd - i2c command structure 2570 * return - true if success, false otherwise. 2571 */ 2572 bool dc_submit_i2c_oem( 2573 struct dc *dc, 2574 struct i2c_command *cmd); 2575 2576 enum aux_return_code_type; 2577 /* Attempt to transfer the given aux payload. This function does not perform 2578 * retries or handle error states. The reply is returned in the payload->reply 2579 * and the result through operation_result. Returns the number of bytes 2580 * transferred,or -1 on a failure. 2581 */ 2582 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 2583 struct aux_payload *payload, 2584 enum aux_return_code_type *operation_result); 2585 2586 struct ddc_service * 2587 dc_get_oem_i2c_device(struct dc *dc); 2588 2589 bool dc_is_oem_i2c_device_present( 2590 struct dc *dc, 2591 size_t slave_address 2592 ); 2593 2594 /* return true if the connected receiver supports the hdcp version */ 2595 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 2596 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 2597 2598 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 2599 * 2600 * TODO - When defer_handling is true the function will have a different purpose. 2601 * It no longer does complete hpd rx irq handling. We should create a separate 2602 * interface specifically for this case. 2603 * 2604 * Return: 2605 * true - Downstream port status changed. DM should call DC to do the 2606 * detection. 2607 * false - no change in Downstream port status. No further action required 2608 * from DM. 2609 */ 2610 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 2611 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 2612 bool defer_handling, bool *has_left_work); 2613 /* handle DP specs define test automation sequence*/ 2614 void dc_link_dp_handle_automated_test(struct dc_link *link); 2615 2616 /* handle DP Link loss sequence and try to recover RX link loss with best 2617 * effort 2618 */ 2619 void dc_link_dp_handle_link_loss(struct dc_link *link); 2620 2621 /* Determine if hpd rx irq should be handled or ignored 2622 * return true - hpd rx irq should be handled. 2623 * return false - it is safe to ignore hpd rx irq event 2624 */ 2625 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 2626 2627 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 2628 * @link - link the hpd irq data associated with 2629 * @hpd_irq_dpcd_data - input hpd irq data 2630 * return - true if hpd irq data indicates a link lost 2631 */ 2632 bool dc_link_check_link_loss_status(struct dc_link *link, 2633 union hpd_irq_data *hpd_irq_dpcd_data); 2634 2635 /* Read hpd rx irq data from a given link 2636 * @link - link where the hpd irq data should be read from 2637 * @irq_data - output hpd irq data 2638 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2639 * read has failed. 2640 */ 2641 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2642 struct dc_link *link, 2643 union hpd_irq_data *irq_data); 2644 2645 bool dc_link_frl_poll_status_flag(struct dc_link *link); 2646 bool dc_link_frl_margin_check_uncompressed_video( 2647 const struct dc_link *link, 2648 struct frl_cap_chk_params_fixed31_32 *params, 2649 struct frl_cap_chk_intermediates_fixed31_32 *inter); 2650 2651 /* The function clears recorded DP RX states in the link. DM should call this 2652 * function when it is resuming from S3 power state to previously connected links. 2653 * 2654 * TODO - in the future we should consider to expand link resume interface to 2655 * support clearing previous rx states. So we don't have to rely on dm to call 2656 * this interface explicitly. 2657 */ 2658 void dc_link_clear_dprx_states(struct dc_link *link); 2659 2660 /* Destruct the mst topology of the link and reset the allocated payload table 2661 * 2662 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2663 * still wants to reset MST topology on an unplug event */ 2664 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2665 2666 /* The function calculates effective DP link bandwidth when a given link is 2667 * using the given link settings. 2668 * 2669 * return - total effective link bandwidth in kbps. 2670 */ 2671 uint32_t dc_link_bandwidth_kbps( 2672 const struct dc_link *link, 2673 const struct dc_link_settings *link_setting); 2674 2675 /* The function returns effective HDMI FRL bandwidth given link rate. 2676 * return - total effective link bandwidth in kbps. 2677 */ 2678 uint32_t dc_link_frl_bandwidth_kbps(const struct dc_link *link, 2679 enum hdmi_frl_link_rate link_rate); 2680 2681 struct dp_audio_bandwidth_params { 2682 const struct dc_crtc_timing *crtc_timing; 2683 enum dp_link_encoding link_encoding; 2684 uint32_t channel_count; 2685 uint32_t sample_rate_hz; 2686 }; 2687 2688 /* The function calculates the minimum size of hblank (in bytes) needed to 2689 * support the specified channel count and sample rate combination, given the 2690 * link encoding and timing to be used. This calculation is not supported 2691 * for 8b/10b SST. 2692 * 2693 * return - min hblank size in bytes, 0 if 8b/10b SST. 2694 */ 2695 uint32_t dc_link_required_hblank_size_bytes( 2696 const struct dc_link *link, 2697 struct dp_audio_bandwidth_params *audio_params); 2698 2699 /* The function takes a snapshot of current link resource allocation state 2700 * @dc: pointer to dc of the dm calling this 2701 * @map: a dc link resource snapshot defined internally to dc. 2702 * 2703 * DM needs to capture a snapshot of current link resource allocation mapping 2704 * and store it in its persistent storage. 2705 * 2706 * Some of the link resource is using first come first serve policy. 2707 * The allocation mapping depends on original hotplug order. This information 2708 * is lost after driver is loaded next time. The snapshot is used in order to 2709 * restore link resource to its previous state so user will get consistent 2710 * link capability allocation across reboot. 2711 * 2712 */ 2713 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2714 2715 /* This function restores link resource allocation state from a snapshot 2716 * @dc: pointer to dc of the dm calling this 2717 * @map: a dc link resource snapshot defined internally to dc. 2718 * 2719 * DM needs to call this function after initial link detection on boot and 2720 * before first commit streams to restore link resource allocation state 2721 * from previous boot session. 2722 * 2723 * Some of the link resource is using first come first serve policy. 2724 * The allocation mapping depends on original hotplug order. This information 2725 * is lost after driver is loaded next time. The snapshot is used in order to 2726 * restore link resource to its previous state so user will get consistent 2727 * link capability allocation across reboot. 2728 * 2729 */ 2730 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2731 2732 void dc_link_wait_for_unlocked(struct dc_link *link); 2733 2734 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2735 * interface i.e stream_update->dsc_config 2736 */ 2737 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2738 2739 /* translate a raw link rate data to bandwidth in kbps */ 2740 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2741 2742 /* determine the optimal bandwidth given link and required bw. 2743 * @link - current detected link 2744 * @req_bw - requested bandwidth in kbps 2745 * @link_settings - returned most optimal link settings that can fit the 2746 * requested bandwidth 2747 * return - false if link can't support requested bandwidth, true if link 2748 * settings is found. 2749 */ 2750 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2751 struct dc_link_settings *link_settings, 2752 uint32_t req_bw); 2753 2754 /* return the max dp link settings can be driven by the link without considering 2755 * connected RX device and its capability 2756 */ 2757 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2758 struct dc_link_settings *max_link_enc_cap); 2759 2760 /* determine when the link is driving MST mode, what DP link channel coding 2761 * format will be used. The decision will remain unchanged until next HPD event. 2762 * 2763 * @link - a link with DP RX connection 2764 * return - if stream is committed to this link with MST signal type, type of 2765 * channel coding format dc will choose. 2766 */ 2767 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2768 const struct dc_link *link); 2769 2770 /* get max dp link settings the link can enable with all things considered. (i.e 2771 * TX/RX/Cable capabilities and dp override policies. 2772 * 2773 * @link - a link with DP RX connection 2774 * return - max dp link settings the link can enable. 2775 * 2776 */ 2777 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2778 2779 /* Get the highest encoding format that the link supports; highest meaning the 2780 * encoding format which supports the maximum bandwidth. 2781 * 2782 * @link - a link with DP RX connection 2783 * return - highest encoding format link supports. 2784 */ 2785 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2786 2787 /* get max frl link settings the link can enable with all things considered. 2788 * (i.e TX/RX capabilities and link verification result. 2789 * 2790 * @link - a link with FRL RX connection 2791 * return - max frl link settings the link can enable. 2792 * 2793 */ 2794 struct dc_hdmi_frl_link_settings *dc_link_get_frl_link_cap( 2795 struct dc_link *link); 2796 2797 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2798 * to a link with dp connector signal type. 2799 * @link - a link with dp connector signal type 2800 * return - true if connected, false otherwise 2801 */ 2802 bool dc_link_is_dp_sink_present(struct dc_link *link); 2803 2804 /* Force DP lane settings update to main-link video signal and notify the change 2805 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2806 * tuning purpose. The interface assumes link has already been enabled with DP 2807 * signal. 2808 * 2809 * @lt_settings - a container structure with desired hw_lane_settings 2810 */ 2811 void dc_link_set_drive_settings(struct dc *dc, 2812 struct link_training_settings *lt_settings, 2813 struct dc_link *link); 2814 2815 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2816 * test or debugging purpose. The test pattern will remain until next un-plug. 2817 * 2818 * @link - active link with DP signal output enabled. 2819 * @test_pattern - desired test pattern to output. 2820 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2821 * @test_pattern_color_space - for video test pattern choose a desired color 2822 * space. 2823 * @p_link_settings - For PHY pattern choose a desired link settings 2824 * @p_custom_pattern - some test pattern will require a custom input to 2825 * customize some pattern details. Otherwise keep it to NULL. 2826 * @cust_pattern_size - size of the custom pattern input. 2827 * 2828 */ 2829 bool dc_link_dp_set_test_pattern( 2830 struct dc_link *link, 2831 enum dp_test_pattern test_pattern, 2832 enum dp_test_pattern_color_space test_pattern_color_space, 2833 const struct link_training_settings *p_link_settings, 2834 const unsigned char *p_custom_pattern, 2835 unsigned int cust_pattern_size); 2836 2837 /* Force DP link settings to always use a specific value until reboot to a 2838 * specific link. If link has already been enabled, the interface will also 2839 * switch to desired link settings immediately. This is a debug interface to 2840 * generic dp issue trouble shooting. 2841 */ 2842 void dc_link_set_preferred_link_settings(struct dc *dc, 2843 struct dc_link_settings *link_setting, 2844 struct dc_link *link); 2845 2846 /* Force FRL link settings to always use a specific value until reboot to a 2847 * specific link. If link has already been enabled, the interface will also 2848 * switch to desired link settings immediately. This is a debug interface to 2849 * generic FRL issue trouble shooting. 2850 */ 2851 void dc_link_set_preferred_frl_link_settings(struct dc *dc, 2852 struct dc_hdmi_frl_link_settings *link_setting, 2853 struct dc_hdmi_frl_link_training_overrides *lt_overrides, 2854 struct dc_link *link); 2855 2856 /* Force DP link to customize a specific link training behavior by overriding to 2857 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2858 * display specific link training issues or apply some display specific 2859 * workaround in link training. 2860 * 2861 * @link_settings - if not NULL, force preferred link settings to the link. 2862 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2863 * will apply this particular override in future link training. If NULL is 2864 * passed in, dc resets previous overrides. 2865 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2866 * training settings. 2867 */ 2868 void dc_link_set_preferred_training_settings(struct dc *dc, 2869 struct dc_link_settings *link_setting, 2870 struct dc_link_training_overrides *lt_overrides, 2871 struct dc_link *link, 2872 bool skip_immediate_retrain); 2873 2874 /* Configure the sink-specific policy for future DP link training. */ 2875 void dc_link_set_skip_link_bw_clear(struct dc_link *link, bool skip); 2876 2877 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2878 bool dc_link_is_fec_supported(const struct dc_link *link); 2879 2880 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2881 * link enablement. 2882 * return - true if FEC should be enabled, false otherwise. 2883 */ 2884 bool dc_link_should_enable_fec(const struct dc_link *link); 2885 2886 /* determine lttpr mode the current link should be enabled with a specific link 2887 * settings. 2888 */ 2889 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2890 struct dc_link_settings *link_setting); 2891 2892 /* Force DP RX to update its power state. 2893 * NOTE: this interface doesn't update dp main-link. Calling this function will 2894 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2895 * RX power state back upon finish DM specific execution requiring DP RX in a 2896 * specific power state. 2897 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2898 * state. 2899 */ 2900 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2901 2902 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2903 * current value read from extended receiver cap from 02200h - 0220Fh. 2904 * Some DP RX has problems of providing accurate DP receiver caps from extended 2905 * field, this interface is a workaround to revert link back to use base caps. 2906 */ 2907 void dc_link_overwrite_extended_receiver_cap( 2908 struct dc_link *link); 2909 2910 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2911 bool wait_for_hpd); 2912 2913 /* Set backlight level of an embedded panel (eDP, LVDS). 2914 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2915 * and 16 bit fractional, where 1.0 is max backlight value. 2916 */ 2917 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2918 struct set_backlight_level_params *backlight_level_params); 2919 2920 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2921 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2922 bool isHDR, 2923 uint32_t backlight_millinits, 2924 uint32_t transition_time_in_ms); 2925 2926 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2927 uint32_t *backlight_millinits, 2928 uint32_t *backlight_millinits_peak); 2929 2930 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2931 2932 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2933 2934 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2935 bool wait, bool force_static, const unsigned int *power_opts); 2936 2937 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2938 2939 bool dc_link_setup_psr(struct dc_link *dc_link, 2940 const struct dc_stream_state *stream, struct psr_config *psr_config, 2941 struct psr_context *psr_context); 2942 2943 /* 2944 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2945 * 2946 * @link: pointer to the dc_link struct instance 2947 * @enable: enable(active) or disable(inactive) replay 2948 * @wait: state transition need to wait the active set completed. 2949 * @force_static: force disable(inactive) the replay 2950 * @power_opts: set power optimazation parameters to DMUB. 2951 * 2952 * return: allow Replay active will return true, else will return false. 2953 */ 2954 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2955 bool wait, bool force_static, const unsigned int *power_opts); 2956 2957 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2958 2959 /* 2960 * Enable or disable Panel Replay on the specified link: 2961 * 2962 * @link: pointer to the dc_link struct instance 2963 * @enable: enable or disable Panel Replay 2964 * 2965 * return: true if successful, false otherwise 2966 */ 2967 bool dc_link_set_pr_enable(struct dc_link *link, bool enable); 2968 2969 /* 2970 * Update Panel Replay state parameters: 2971 * 2972 * @link: pointer to the dc_link struct instance 2973 * @update_state_data: pointer to state update data structure 2974 * 2975 * return: true if successful, false otherwise 2976 */ 2977 bool dc_link_update_pr_state(struct dc_link *link, 2978 struct dmub_cmd_pr_update_state_data *update_state_data); 2979 2980 /* 2981 * Send general command to Panel Replay firmware: 2982 * 2983 * @link: pointer to the dc_link struct instance 2984 * @general_cmd_data: pointer to general command data structure 2985 * 2986 * return: true if successful, false otherwise 2987 */ 2988 bool dc_link_set_pr_general_cmd(struct dc_link *link, 2989 struct dmub_cmd_pr_general_cmd_data *general_cmd_data); 2990 2991 /* 2992 * Measure Panel Replay residency for the given link. 2993 * mode: PR_RESIDENCY_MODE_PHY, PR_RESIDENCY_MODE_ALPM, or 2994 * PR_RESIDENCY_MODE_ENABLEMENT_PERIOD 2995 */ 2996 void dc_link_edp_replay_residency(const struct dc_link *link, 2997 unsigned int *residency, bool is_start, enum pr_residency_mode mode); 2998 2999 /* 3000 * Get Panel Replay state: 3001 * 3002 * @link: pointer to the dc_link struct instance 3003 * @state: pointer to store the Panel Replay state 3004 * 3005 * return: true if successful, false otherwise 3006 */ 3007 bool dc_link_get_pr_state(const struct dc_link *link, uint64_t *state); 3008 3009 /* On eDP links this function call will stall until T12 has elapsed. 3010 * If the panel is not in power off state, this function will return 3011 * immediately. 3012 */ 3013 bool dc_link_wait_for_t12(struct dc_link *link); 3014 3015 /* Determine if dp trace has been initialized to reflect upto date result * 3016 * return - true if trace is initialized and has valid data. False dp trace 3017 * doesn't have valid result. 3018 */ 3019 bool dc_dp_trace_is_initialized(struct dc_link *link); 3020 3021 /* Query a dp trace flag to indicate if the current dp trace data has been 3022 * logged before 3023 */ 3024 bool dc_dp_trace_is_logged(struct dc_link *link, 3025 bool in_detection); 3026 3027 /* Set dp trace flag to indicate whether DM has already logged the current dp 3028 * trace data. DM can set is_logged to true upon logging and check 3029 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 3030 */ 3031 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 3032 bool in_detection, 3033 bool is_logged); 3034 3035 /* Obtain driver time stamp for last dp link training end. The time stamp is 3036 * formatted based on dm_get_timestamp DM function. 3037 * @in_detection - true to get link training end time stamp of last link 3038 * training in detection sequence. false to get link training end time stamp 3039 * of last link training in commit (dpms) sequence 3040 */ 3041 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 3042 bool in_detection); 3043 3044 /* Get how many link training attempts dc has done with latest sequence. 3045 * @in_detection - true to get link training count of last link 3046 * training in detection sequence. false to get link training count of last link 3047 * training in commit (dpms) sequence 3048 */ 3049 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 3050 bool in_detection); 3051 3052 /* Get how many link loss has happened since last link training attempts */ 3053 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 3054 3055 /* 3056 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 3057 */ 3058 /* 3059 * Send a request from DP-Tx requesting to allocate BW remotely after 3060 * allocating it locally. This will get processed by CM and a CB function 3061 * will be called. 3062 * 3063 * @link: pointer to the dc_link struct instance 3064 * @req_bw: The requested bw in Kbyte to allocated 3065 * 3066 * return: none 3067 */ 3068 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 3069 3070 /* 3071 * Handle the USB4 BW Allocation related functionality here: 3072 * Plug => Try to allocate max bw from timing parameters supported by the sink 3073 * Unplug => de-allocate bw 3074 * 3075 * @link: pointer to the dc_link struct instance 3076 * @peak_bw: Peak bw used by the link/sink 3077 * 3078 */ 3079 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 3080 struct dc_link *link, int peak_bw); 3081 3082 /* 3083 * Calculates the DP tunneling bandwidth required for the stream timing 3084 * and aggregates the stream bandwidth for the respective DP tunneling link 3085 * 3086 * return: dc_status 3087 */ 3088 enum dc_status dc_link_validate_dp_tunneling_bandwidth(const struct dc *dc, const struct dc_state *new_ctx); 3089 3090 /* 3091 * Get if ALPM is supported by the link 3092 */ 3093 void dc_link_get_alpm_support(struct dc_link *link, bool *auxless_support, 3094 bool *auxwake_support); 3095 3096 /* Sink Interfaces - A sink corresponds to a display output device */ 3097 3098 struct dc_container_id { 3099 // 128bit GUID in binary form 3100 unsigned char guid[16]; 3101 // 8 byte port ID -> ELD.PortID 3102 unsigned int portId[2]; 3103 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 3104 unsigned short manufacturerName; 3105 // 2 byte product code -> ELD.ProductCode 3106 unsigned short productCode; 3107 }; 3108 3109 3110 struct dc_sink_dsc_caps { 3111 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 3112 // 'false' if they are sink's DSC caps 3113 bool is_virtual_dpcd_dsc; 3114 // 'true' if MST topology supports DSC passthrough for sink 3115 // 'false' if MST topology does not support DSC passthrough 3116 bool is_dsc_passthrough_supported; 3117 struct dsc_dec_dpcd_caps dsc_dec_caps; 3118 }; 3119 3120 struct dc_sink_hblank_expansion_caps { 3121 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 3122 // 'false' if they are sink's HBlank expansion caps 3123 bool is_virtual_dpcd_hblank_expansion; 3124 struct hblank_expansion_dpcd_caps dpcd_caps; 3125 }; 3126 3127 struct dc_sink_fec_caps { 3128 bool is_rx_fec_supported; 3129 bool is_topology_fec_supported; 3130 }; 3131 3132 struct scdc_caps { 3133 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 3134 union hdmi_scdc_device_id_data device_id; 3135 }; 3136 3137 /* 3138 * The sink structure contains EDID and other display device properties 3139 */ 3140 struct dc_sink { 3141 enum signal_type sink_signal; 3142 struct dc_edid dc_edid; /* raw edid */ 3143 struct dc_edid_caps edid_caps; /* parse display caps */ 3144 struct dc_container_id *dc_container_id; 3145 uint32_t dongle_max_pix_clk; 3146 void *priv; 3147 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 3148 bool converter_disable_audio; 3149 3150 struct mccs_caps mccs_caps; 3151 struct scdc_caps scdc_caps; 3152 struct dc_sink_dsc_caps dsc_caps; 3153 struct dc_sink_fec_caps fec_caps; 3154 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 3155 3156 bool is_vsc_sdp_colorimetry_supported; 3157 3158 /* private to DC core */ 3159 struct dc_link *link; 3160 struct dc_context *ctx; 3161 3162 uint32_t sink_id; 3163 3164 /* private to dc_sink.c */ 3165 // refcount must be the last member in dc_sink, since we want the 3166 // sink structure to be logically cloneable up to (but not including) 3167 // refcount 3168 struct kref refcount; 3169 }; 3170 3171 void dc_sink_retain(struct dc_sink *sink); 3172 void dc_sink_release(struct dc_sink *sink); 3173 3174 struct dc_sink_init_data { 3175 enum signal_type sink_signal; 3176 struct dc_link *link; 3177 uint32_t dongle_max_pix_clk; 3178 bool converter_disable_audio; 3179 }; 3180 3181 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 3182 3183 /* Newer interfaces */ 3184 struct dc_cursor { 3185 struct dc_plane_address address; 3186 struct dc_cursor_attributes attributes; 3187 }; 3188 3189 3190 /* Interrupt interfaces */ 3191 enum dc_irq_source dc_interrupt_to_irq_source( 3192 struct dc *dc, 3193 uint32_t src_id, 3194 uint32_t ext_id); 3195 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 3196 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 3197 bool dc_get_flip_pending_on_otg(struct dc *dc, int otg_inst); 3198 enum dc_irq_source dc_get_hpd_irq_source_at_index( 3199 struct dc *dc, uint32_t link_index); 3200 3201 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 3202 3203 /* Power Interfaces */ 3204 3205 void dc_set_power_state( 3206 struct dc *dc, 3207 enum dc_acpi_cm_power_state power_state); 3208 void dc_resume(struct dc *dc); 3209 3210 void dc_power_down_on_boot(struct dc *dc); 3211 3212 void dc_disable_dangling_timing_generators(struct dc *dc); 3213 3214 /* 3215 * HDCP Interfaces 3216 */ 3217 enum hdcp_message_status dc_process_hdcp_msg( 3218 enum signal_type signal, 3219 struct dc_link *link, 3220 struct hdcp_protection_message *message_info); 3221 bool dc_is_dmcu_initialized(struct dc *dc); 3222 3223 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 3224 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 3225 3226 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 3227 unsigned int pitch, 3228 unsigned int height, 3229 enum surface_pixel_format format, 3230 struct dc_cursor_attributes *cursor_attr); 3231 3232 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 3233 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 3234 3235 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 3236 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 3237 bool dc_dmub_is_ips_idle_state(struct dc *dc); 3238 3239 /* set min and max memory clock to lowest and highest DPM level, respectively */ 3240 void dc_unlock_memory_clock_frequency(struct dc *dc); 3241 3242 /* set min memory clock to the min required for current mode, max to maxDPM */ 3243 void dc_lock_memory_clock_frequency(struct dc *dc); 3244 3245 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 3246 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 3247 3248 /* cleanup on driver unload */ 3249 void dc_hardware_release(struct dc *dc); 3250 3251 /* disables fw based mclk switch */ 3252 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 3253 3254 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 3255 3256 bool dc_set_replay_allow_active(struct dc *dc, bool active); 3257 3258 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 3259 3260 void dc_z10_restore(const struct dc *dc); 3261 void dc_z10_save_init(struct dc *dc); 3262 3263 bool dc_is_dmub_outbox_supported(struct dc *dc); 3264 bool dc_enable_dmub_notifications(struct dc *dc); 3265 3266 bool dc_abm_save_restore( 3267 struct dc *dc, 3268 struct dc_stream_state *stream, 3269 struct abm_save_restore *pData); 3270 3271 void dc_enable_dmub_outbox(struct dc *dc); 3272 3273 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 3274 uint32_t link_index, 3275 struct aux_payload *payload); 3276 3277 /* 3278 * smart power OLED Interfaces 3279 */ 3280 bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_t peak_nits, 3281 uint8_t debug_control, uint16_t fixed_CLL, uint32_t triggerline); 3282 bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *pCurrent_MaxCLL); 3283 3284 /* Get dc link index from dpia port index */ 3285 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 3286 uint8_t dpia_port_index); 3287 3288 bool dc_process_dmub_set_config_async(struct dc *dc, 3289 uint32_t link_index, 3290 struct set_config_cmd_payload *payload, 3291 struct dmub_notification *notify); 3292 3293 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 3294 uint32_t link_index, 3295 uint8_t mst_alloc_slots, 3296 uint8_t *mst_slots_in_use); 3297 3298 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 3299 3300 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 3301 uint32_t hpd_int_enable); 3302 3303 void dc_print_dmub_diagnostic_data(const struct dc *dc); 3304 3305 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 3306 3307 struct dc_power_profile { 3308 int power_level; /* Lower is better */ 3309 }; 3310 3311 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 3312 3313 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 3314 3315 bool dc_get_host_router_index(const struct dc_link *link, unsigned int *host_router_index); 3316 3317 void dc_log_preos_dmcub_info(const struct dc *dc); 3318 3319 /* DSC Interfaces */ 3320 #include "dc_dsc.h" 3321 3322 void dc_get_visual_confirm_for_stream( 3323 struct dc *dc, 3324 struct dc_stream_state *stream_state, 3325 struct tg_color *color); 3326 3327 /* Disable acc mode Interfaces */ 3328 void dc_disable_accelerated_mode(struct dc *dc); 3329 3330 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 3331 struct dc_stream_state *new_stream); 3332 3333 bool dc_is_cursor_limit_pending(struct dc *dc); 3334 bool dc_can_clear_cursor_limit(const struct dc *dc); 3335 3336 /** 3337 * dc_get_underflow_debug_data_for_otg() - Retrieve underflow debug data. 3338 * 3339 * @dc: Pointer to the display core context. 3340 * @primary_otg_inst: Instance index of the primary OTG that underflowed. 3341 * @out_data: Pointer to a dc_underflow_debug_data struct to be filled with debug information. 3342 * 3343 * This function collects and logs underflow-related HW states when underflow happens, 3344 * including OTG underflow status, current read positions, frame count, and per-HUBP debug data. 3345 * The results are stored in the provided out_data structure for further analysis or logging. 3346 */ 3347 void dc_get_underflow_debug_data_for_otg(struct dc *dc, unsigned int primary_otg_inst, struct dc_underflow_debug_data *out_data); 3348 3349 void dc_get_power_feature_status(struct dc *dc, unsigned int primary_otg_inst, struct power_features *out_data); 3350 3351 /* 3352 * Software state variables used to program register fields across the display pipeline 3353 */ 3354 struct dc_register_software_state { 3355 /* HUBP register programming variables for each pipe */ 3356 struct { 3357 bool valid_plane_state; 3358 bool valid_stream; 3359 bool min_dc_gfx_version9; 3360 uint32_t vtg_sel; /* DCHUBP_CNTL->HUBP_VTG_SEL from pipe_ctx->stream_res.tg->inst */ 3361 uint32_t hubp_clock_enable; /* HUBP_CLK_CNTL->HUBP_CLOCK_ENABLE from power management */ 3362 uint32_t surface_pixel_format; /* DCSURF_SURFACE_CONFIG->SURFACE_PIXEL_FORMAT from plane_state->format */ 3363 uint32_t rotation_angle; /* DCSURF_SURFACE_CONFIG->ROTATION_ANGLE from plane_state->rotation */ 3364 uint32_t h_mirror_en; /* DCSURF_SURFACE_CONFIG->H_MIRROR_EN from plane_state->horizontal_mirror */ 3365 uint32_t surface_dcc_en; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_EN from dcc->enable */ 3366 uint32_t surface_size_width; /* HUBP_SIZE->SURFACE_SIZE_WIDTH from plane_size.surface_size.width */ 3367 uint32_t surface_size_height; /* HUBP_SIZE->SURFACE_SIZE_HEIGHT from plane_size.surface_size.height */ 3368 uint32_t pri_viewport_width; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_WIDTH from scaler_data.viewport.width */ 3369 uint32_t pri_viewport_height; /* DCSURF_PRI_VIEWPORT_DIMENSION->PRI_VIEWPORT_HEIGHT from scaler_data.viewport.height */ 3370 uint32_t pri_viewport_x_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_X_START from scaler_data.viewport.x */ 3371 uint32_t pri_viewport_y_start; /* DCSURF_PRI_VIEWPORT_START->PRI_VIEWPORT_Y_START from scaler_data.viewport.y */ 3372 uint32_t cursor_enable; /* CURSOR_CONTROL->CURSOR_ENABLE from cursor_attributes.enable */ 3373 uint32_t cursor_width; /* CURSOR_SETTINGS->CURSOR_WIDTH from cursor_position.width */ 3374 uint32_t cursor_height; /* CURSOR_SETTINGS->CURSOR_HEIGHT from cursor_position.height */ 3375 3376 /* Additional DCC configuration */ 3377 uint32_t surface_dcc_ind_64b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_64B_BLK from dcc.independent_64b_blks */ 3378 uint32_t surface_dcc_ind_128b_blk; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_DCC_IND_128B_BLK from dcc.independent_128b_blks */ 3379 3380 /* Surface pitch configuration */ 3381 uint32_t surface_pitch; /* DCSURF_SURFACE_PITCH->PITCH from plane_size.surface_pitch */ 3382 uint32_t meta_pitch; /* DCSURF_SURFACE_PITCH->META_PITCH from dcc.meta_pitch */ 3383 uint32_t chroma_pitch; /* DCSURF_SURFACE_PITCH_C->PITCH_C from plane_size.chroma_pitch */ 3384 uint32_t meta_pitch_c; /* DCSURF_SURFACE_PITCH_C->META_PITCH_C from dcc.meta_pitch_c */ 3385 3386 /* Surface addresses */ 3387 uint32_t primary_surface_address_low; /* DCSURF_PRIMARY_SURFACE_ADDRESS->PRIMARY_SURFACE_ADDRESS from address.grph.addr.low_part */ 3388 uint32_t primary_surface_address_high; /* DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH->PRIMARY_SURFACE_ADDRESS_HIGH from address.grph.addr.high_part */ 3389 uint32_t primary_meta_surface_address_low; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS->PRIMARY_META_SURFACE_ADDRESS from address.grph.meta_addr.low_part */ 3390 uint32_t primary_meta_surface_address_high; /* DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH->PRIMARY_META_SURFACE_ADDRESS_HIGH from address.grph.meta_addr.high_part */ 3391 3392 /* TMZ configuration */ 3393 uint32_t primary_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_SURFACE_TMZ from address.tmz_surface */ 3394 uint32_t primary_meta_surface_tmz; /* DCSURF_SURFACE_CONTROL->PRIMARY_META_SURFACE_TMZ from address.tmz_surface */ 3395 3396 /* Tiling configuration */ 3397 uint32_t sw_mode; /* DCSURF_TILING_CONFIG->SW_MODE from tiling_info.gfx9.swizzle */ 3398 uint32_t num_pipes; /* DCSURF_ADDR_CONFIG->NUM_PIPES from tiling_info.gfx9.num_pipes */ 3399 uint32_t num_banks; /* DCSURF_ADDR_CONFIG->NUM_BANKS from tiling_info.gfx9.num_banks */ 3400 uint32_t pipe_interleave; /* DCSURF_ADDR_CONFIG->PIPE_INTERLEAVE from tiling_info.gfx9.pipe_interleave */ 3401 uint32_t num_shader_engines; /* DCSURF_ADDR_CONFIG->NUM_SE from tiling_info.gfx9.num_shader_engines */ 3402 uint32_t num_rb_per_se; /* DCSURF_ADDR_CONFIG->NUM_RB_PER_SE from tiling_info.gfx9.num_rb_per_se */ 3403 uint32_t num_pkrs; /* DCSURF_ADDR_CONFIG->NUM_PKRS from tiling_info.gfx9.num_pkrs */ 3404 3405 /* DML Request Size Configuration - Luma */ 3406 uint32_t rq_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->CHUNK_SIZE from rq_regs.rq_regs_l.chunk_size */ 3407 uint32_t rq_min_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_CHUNK_SIZE from rq_regs.rq_regs_l.min_chunk_size */ 3408 uint32_t rq_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->META_CHUNK_SIZE from rq_regs.rq_regs_l.meta_chunk_size */ 3409 uint32_t rq_min_meta_chunk_size; /* DCHUBP_REQ_SIZE_CONFIG->MIN_META_CHUNK_SIZE from rq_regs.rq_regs_l.min_meta_chunk_size */ 3410 uint32_t rq_dpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->DPTE_GROUP_SIZE from rq_regs.rq_regs_l.dpte_group_size */ 3411 uint32_t rq_mpte_group_size; /* DCHUBP_REQ_SIZE_CONFIG->MPTE_GROUP_SIZE from rq_regs.rq_regs_l.mpte_group_size */ 3412 uint32_t rq_swath_height_l; /* DCHUBP_REQ_SIZE_CONFIG->SWATH_HEIGHT_L from rq_regs.rq_regs_l.swath_height */ 3413 uint32_t rq_pte_row_height_l; /* DCHUBP_REQ_SIZE_CONFIG->PTE_ROW_HEIGHT_L from rq_regs.rq_regs_l.pte_row_height */ 3414 3415 /* DML Request Size Configuration - Chroma */ 3416 uint32_t rq_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->CHUNK_SIZE_C from rq_regs.rq_regs_c.chunk_size */ 3417 uint32_t rq_min_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_chunk_size */ 3418 uint32_t rq_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->META_CHUNK_SIZE_C from rq_regs.rq_regs_c.meta_chunk_size */ 3419 uint32_t rq_min_meta_chunk_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MIN_META_CHUNK_SIZE_C from rq_regs.rq_regs_c.min_meta_chunk_size */ 3420 uint32_t rq_dpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->DPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.dpte_group_size */ 3421 uint32_t rq_mpte_group_size_c; /* DCHUBP_REQ_SIZE_CONFIG_C->MPTE_GROUP_SIZE_C from rq_regs.rq_regs_c.mpte_group_size */ 3422 uint32_t rq_swath_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->SWATH_HEIGHT_C from rq_regs.rq_regs_c.swath_height */ 3423 uint32_t rq_pte_row_height_c; /* DCHUBP_REQ_SIZE_CONFIG_C->PTE_ROW_HEIGHT_C from rq_regs.rq_regs_c.pte_row_height */ 3424 3425 /* DML Expansion Modes */ 3426 uint32_t drq_expansion_mode; /* DCN_EXPANSION_MODE->DRQ_EXPANSION_MODE from rq_regs.drq_expansion_mode */ 3427 uint32_t prq_expansion_mode; /* DCN_EXPANSION_MODE->PRQ_EXPANSION_MODE from rq_regs.prq_expansion_mode */ 3428 uint32_t mrq_expansion_mode; /* DCN_EXPANSION_MODE->MRQ_EXPANSION_MODE from rq_regs.mrq_expansion_mode */ 3429 uint32_t crq_expansion_mode; /* DCN_EXPANSION_MODE->CRQ_EXPANSION_MODE from rq_regs.crq_expansion_mode */ 3430 3431 /* DML DLG parameters - nominal */ 3432 uint32_t dst_y_per_vm_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_VM_VBLANK from dlg_regs.dst_y_per_vm_vblank */ 3433 uint32_t dst_y_per_row_vblank; /* NOM_PARAMETERS_0->DST_Y_PER_ROW_VBLANK from dlg_regs.dst_y_per_row_vblank */ 3434 uint32_t dst_y_per_vm_flip; /* NOM_PARAMETERS_1->DST_Y_PER_VM_FLIP from dlg_regs.dst_y_per_vm_flip */ 3435 uint32_t dst_y_per_row_flip; /* NOM_PARAMETERS_1->DST_Y_PER_ROW_FLIP from dlg_regs.dst_y_per_row_flip */ 3436 3437 /* DML prefetch settings */ 3438 uint32_t dst_y_prefetch; /* PREFETCH_SETTINS->DST_Y_PREFETCH from dlg_regs.dst_y_prefetch */ 3439 uint32_t vratio_prefetch; /* PREFETCH_SETTINS->VRATIO_PREFETCH from dlg_regs.vratio_prefetch */ 3440 uint32_t vratio_prefetch_c; /* PREFETCH_SETTINS_C->VRATIO_PREFETCH_C from dlg_regs.vratio_prefetch_c */ 3441 3442 /* TTU parameters */ 3443 uint32_t qos_level_low_wm; /* TTU_CNTL1->QoSLevelLowWaterMark from ttu_regs.qos_level_low_wm */ 3444 uint32_t qos_level_high_wm; /* TTU_CNTL1->QoSLevelHighWaterMark from ttu_regs.qos_level_high_wm */ 3445 uint32_t qos_level_flip; /* TTU_CNTL2->QoS_LEVEL_FLIP_L from ttu_regs.qos_level_flip */ 3446 uint32_t min_ttu_vblank; /* DCN_GLOBAL_TTU_CNTL->MIN_TTU_VBLANK from ttu_regs.min_ttu_vblank */ 3447 } hubp[MAX_PIPES]; 3448 3449 /* HUBBUB register programming variables */ 3450 struct { 3451 /* Individual DET buffer control per pipe - software state that programs DET registers */ 3452 uint32_t det0_size; /* DCHUBBUB_DET0_CTRL->DET0_SIZE from hubbub->funcs->program_det_size(hubbub, 0, det_buffer_size_kb) */ 3453 uint32_t det1_size; /* DCHUBBUB_DET1_CTRL->DET1_SIZE from hubbub->funcs->program_det_size(hubbub, 1, det_buffer_size_kb) */ 3454 uint32_t det2_size; /* DCHUBBUB_DET2_CTRL->DET2_SIZE from hubbub->funcs->program_det_size(hubbub, 2, det_buffer_size_kb) */ 3455 uint32_t det3_size; /* DCHUBBUB_DET3_CTRL->DET3_SIZE from hubbub->funcs->program_det_size(hubbub, 3, det_buffer_size_kb) */ 3456 3457 /* Compression buffer control - software state that programs COMPBUF registers */ 3458 uint32_t compbuf_size; /* DCHUBBUB_COMPBUF_CTRL->COMPBUF_SIZE from hubbub->funcs->program_compbuf_size(hubbub, compbuf_size_kb, safe_to_increase) */ 3459 uint32_t compbuf_reserved_space_64b; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_64B from hubbub2->pixel_chunk_size / 32 */ 3460 uint32_t compbuf_reserved_space_zs; /* COMPBUF_RESERVED_SPACE->COMPBUF_RESERVED_SPACE_ZS from hubbub2->pixel_chunk_size / 128 */ 3461 } hubbub; 3462 3463 /* DPP register programming variables for each pipe (simplified for available fields) */ 3464 struct { 3465 uint32_t dpp_clock_enable; /* DPP_CONTROL->DPP_CLOCK_ENABLE from dppclk_enable */ 3466 3467 /* Recout (Rectangle of Interest) configuration */ 3468 uint32_t recout_start_x; /* RECOUT_START->RECOUT_START_X from pipe_ctx->plane_res.scl_data.recout.x */ 3469 uint32_t recout_start_y; /* RECOUT_START->RECOUT_START_Y from pipe_ctx->plane_res.scl_data.recout.y */ 3470 uint32_t recout_width; /* RECOUT_SIZE->RECOUT_WIDTH from pipe_ctx->plane_res.scl_data.recout.width */ 3471 uint32_t recout_height; /* RECOUT_SIZE->RECOUT_HEIGHT from pipe_ctx->plane_res.scl_data.recout.height */ 3472 3473 /* MPC (Multiple Pipe/Plane Combiner) size configuration */ 3474 uint32_t mpc_width; /* MPC_SIZE->MPC_WIDTH from pipe_ctx->plane_res.scl_data.h_active */ 3475 uint32_t mpc_height; /* MPC_SIZE->MPC_HEIGHT from pipe_ctx->plane_res.scl_data.v_active */ 3476 3477 /* DSCL mode configuration */ 3478 uint32_t dscl_mode; /* SCL_MODE->DSCL_MODE from pipe_ctx->plane_res.scl_data.dscl_prog_data.dscl_mode */ 3479 3480 /* Scaler ratios (simplified to integer parts) */ 3481 uint32_t horz_ratio_int; /* SCL_HORZ_FILTER_SCALE_RATIO->SCL_H_SCALE_RATIO integer part from ratios.horz */ 3482 uint32_t vert_ratio_int; /* SCL_VERT_FILTER_SCALE_RATIO->SCL_V_SCALE_RATIO integer part from ratios.vert */ 3483 3484 /* Basic scaler taps */ 3485 uint32_t h_taps; /* SCL_TAP_CONTROL->SCL_H_NUM_TAPS from taps.h_taps */ 3486 uint32_t v_taps; /* SCL_TAP_CONTROL->SCL_V_NUM_TAPS from taps.v_taps */ 3487 } dpp[MAX_PIPES]; 3488 3489 /* DCCG register programming variables */ 3490 struct { 3491 /* Core Display Clock Control */ 3492 uint32_t dispclk_khz; /* DENTIST_DISPCLK_CNTL->DENTIST_DISPCLK_WDIVIDER from clk_mgr.dispclk_khz */ 3493 uint32_t dc_mem_global_pwr_req_dis; /* DC_MEM_GLOBAL_PWR_REQ_CNTL->DC_MEM_GLOBAL_PWR_REQ_DIS from memory power management settings */ 3494 3495 /* DPP Clock Control - 4 fields per pipe */ 3496 uint32_t dppclk_khz[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK_R_GATE_DISABLE from dpp_clocks[pipe] */ 3497 uint32_t dppclk_enable[MAX_PIPES]; /* DPPCLK_CTRL->DPPCLK0_EN,DPPCLK1_EN,DPPCLK2_EN,DPPCLK3_EN from dccg31_update_dpp_dto() */ 3498 uint32_t dppclk_dto_enable[MAX_PIPES]; /* DPPCLK_DTO_CTRL->DPPCLK_DTO_ENABLE from dccg->dpp_clock_gated[dpp_inst] state */ 3499 uint32_t dppclk_dto_phase[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_PHASE from phase calculation req_dppclk/ref_dppclk */ 3500 uint32_t dppclk_dto_modulo[MAX_PIPES]; /* DPPCLK0_DTO_PARAM->DPPCLK0_DTO_MODULO from modulo = 0xff */ 3501 3502 /* DSC Clock Control - 4 fields per DSC resource */ 3503 uint32_t dscclk_khz[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK_DTO_ENABLE from dsc_clocks */ 3504 uint32_t dscclk_dto_enable[MAX_PIPES]; /* DSCCLK_DTO_CTRL->DSCCLK0_DTO_ENABLE,DSCCLK1_DTO_ENABLE,DSCCLK2_DTO_ENABLE,DSCCLK3_DTO_ENABLE */ 3505 uint32_t dscclk_dto_phase[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_PHASE from dccg31_enable_dscclk() */ 3506 uint32_t dscclk_dto_modulo[MAX_PIPES]; /* DSCCLK0_DTO_PARAM->DSCCLK0_DTO_MODULO from dccg31_enable_dscclk() */ 3507 3508 /* Pixel Clock Control - per pipe */ 3509 uint32_t pixclk_khz[MAX_PIPES]; /* PIXCLK_RESYNC_CNTL->PIXCLK_RESYNC_ENABLE from stream.timing.pix_clk_100hz */ 3510 uint32_t otg_pixel_rate_div[MAX_PIPES]; /* OTG_PIXEL_RATE_DIV->OTG_PIXEL_RATE_DIV from OTG pixel rate divider control */ 3511 uint32_t dtbclk_dto_enable[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_ENABLE from dccg31_set_dtbclk_dto() */ 3512 uint32_t pipe_dto_src_sel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->PIPE_DTO_SRC_SEL from dccg31_set_dtbclk_dto() source selection */ 3513 uint32_t dtbclk_dto_div[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->DTBCLK_DTO_DIV from dtbdto_div calculation */ 3514 uint32_t otg_add_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_ADD_PIXEL from dccg31_otg_add_pixel() */ 3515 uint32_t otg_drop_pixel[MAX_PIPES]; /* OTG0_PIXEL_RATE_CNTL->OTG_DROP_PIXEL from dccg31_otg_drop_pixel() */ 3516 3517 /* DTBCLK DTO Control - 4 DTOs */ 3518 uint32_t dtbclk_dto_modulo[4]; /* DTBCLK_DTO0_MODULO->DTBCLK_DTO0_MODULO from dccg31_set_dtbclk_dto() modulo calculation */ 3519 uint32_t dtbclk_dto_phase[4]; /* DTBCLK_DTO0_PHASE->DTBCLK_DTO0_PHASE from phase calculation pixclk_khz/ref_dtbclk_khz */ 3520 uint32_t dtbclk_dto_dbuf_en; /* DTBCLK_DTO_DBUF_EN->DTBCLK DTO data buffer enable */ 3521 3522 /* DP Stream Clock Control - 4 pipes */ 3523 uint32_t dpstreamclk_enable[MAX_PIPES]; /* DPSTREAMCLK_CNTL->DPSTREAMCLK_PIPE0_EN,DPSTREAMCLK_PIPE1_EN,DPSTREAMCLK_PIPE2_EN,DPSTREAMCLK_PIPE3_EN */ 3524 uint32_t dp_dto_modulo[4]; /* DP_DTO0_MODULO->DP_DTO0_MODULO from DP stream DTO programming */ 3525 uint32_t dp_dto_phase[4]; /* DP_DTO0_PHASE->DP_DTO0_PHASE from DP stream DTO programming */ 3526 uint32_t dp_dto_dbuf_en; /* DP_DTO_DBUF_EN->DP DTO data buffer enable */ 3527 3528 /* PHY Symbol Clock Control - 5 PHYs (A,B,C,D,E) */ 3529 uint32_t phy_symclk_force_en[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_EN from dccg31_set_physymclk() force_enable */ 3530 uint32_t phy_symclk_force_src_sel[5]; /* PHYASYMCLK_CLOCK_CNTL->PHYASYMCLK_FORCE_SRC_SEL from dccg31_set_physymclk() clk_src */ 3531 uint32_t phy_symclk_gate_disable[5]; /* DCCG_GATE_DISABLE_CNTL2->PHYASYMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.physymclk */ 3532 3533 /* SYMCLK32 SE Control - 4 instances */ 3534 uint32_t symclk32_se_src_sel[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_SRC_SEL from dccg31_enable_symclk32_se() with get_phy_mux_symclk() mapping */ 3535 uint32_t symclk32_se_enable[4]; /* SYMCLK32_SE_CNTL->SYMCLK32_SE0_EN from dccg31_enable_symclk32_se() enable */ 3536 uint32_t symclk32_se_gate_disable[4]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_SE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_se */ 3537 3538 /* SYMCLK32 LE Control - 2 instances */ 3539 uint32_t symclk32_le_src_sel[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_SRC_SEL from dccg31_enable_symclk32_le() phyd32clk source */ 3540 uint32_t symclk32_le_enable[2]; /* SYMCLK32_LE_CNTL->SYMCLK32_LE0_EN from dccg31_enable_symclk32_le() enable */ 3541 uint32_t symclk32_le_gate_disable[2]; /* DCCG_GATE_DISABLE_CNTL3->SYMCLK32_LE0_GATE_DISABLE from debug.root_clock_optimization.bits.symclk32_le */ 3542 3543 /* HDMI Clock Control */ 3544 uint32_t hdmicharclk_enable; /* HDMICHARCLK0_CLOCK_CNTL->HDMICHARCLK0_EN from dccg31_enable_hdmicharclk() */ 3545 uint32_t hdmicharclk_src_sel; /* HDMICHARCLK0_CLOCK_CNTL->HDMICHARCLK0_SRC_SEL from dccg31_enable_hdmicharclk() phypll_inst source */ 3546 uint32_t hdmistreamclk_src_sel; /* HDMISTREAMCLK_CNTL->HDMISTREAMCLK0_SRC_SEL from dccg31_set_hdmistreamclk() src selection */ 3547 uint32_t hdmistreamclk_dto_force_dis; /* HDMISTREAMCLK_CNTL->HDMISTREAMCLK0_DTO_FORCE_DIS from dccg31_set_hdmistreamclk() DTO force bypass */ 3548 uint32_t hdmistreamclk_dto_phase; /* HDMISTREAMCLK0_DTO_PARAM->HDMISTREAMCLK0_DTO_PHASE from dccg31_disable_hdmistreamclk() */ 3549 uint32_t hdmistreamclk_dto_modulo; /* HDMISTREAMCLK0_DTO_PARAM->HDMISTREAMCLK0_DTO_MODULO from dccg31_disable_hdmistreamclk() */ 3550 3551 /* DPIA Clock Control */ 3552 uint32_t dpiaclk_540m_dto_modulo; /* DPIACLK_540M_DTO_MODULO->DPIA 540MHz DTO modulo */ 3553 uint32_t dpiaclk_540m_dto_phase; /* DPIACLK_540M_DTO_PHASE->DPIA 540MHz DTO phase */ 3554 uint32_t dpiaclk_810m_dto_modulo; /* DPIACLK_810M_DTO_MODULO->DPIA 810MHz DTO modulo */ 3555 uint32_t dpiaclk_810m_dto_phase; /* DPIACLK_810M_DTO_PHASE->DPIA 810MHz DTO phase */ 3556 uint32_t dpiaclk_dto_cntl; /* DPIACLK_DTO_CNTL->DPIA clock DTO control */ 3557 uint32_t dpiasymclk_cntl; /* DPIASYMCLK_CNTL->DPIA symbol clock control */ 3558 3559 /* Clock Gating Control */ 3560 uint32_t dccg_gate_disable_cntl; /* DCCG_GATE_DISABLE_CNTL->Clock gate disable control from dccg31_init() */ 3561 uint32_t dpstreamclk_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ 3562 uint32_t dpstreamclk_root_gate_disable; /* DCCG_GATE_DISABLE_CNTL3->DPSTREAMCLK_ROOT_GATE_DISABLE from debug.root_clock_optimization.bits.dpstream */ 3563 3564 /* VSync Control */ 3565 uint32_t vsync_cnt_ctrl; /* DCCG_VSYNC_CNT_CTRL->VSync counter control */ 3566 uint32_t vsync_cnt_int_ctrl; /* DCCG_VSYNC_CNT_INT_CTRL->VSync counter interrupt control */ 3567 uint32_t vsync_otg_latch_value[6]; /* DCCG_VSYNC_OTG0_LATCH_VALUE->OTG0 VSync latch value (for OTG0-5) */ 3568 3569 /* Time Base Control */ 3570 uint32_t microsecond_time_base_div; /* MICROSECOND_TIME_BASE_DIV->Microsecond time base divider */ 3571 uint32_t millisecond_time_base_div; /* MILLISECOND_TIME_BASE_DIV->Millisecond time base divider */ 3572 } dccg; 3573 3574 /* DSC essential configuration for underflow analysis */ 3575 struct { 3576 /* DSC active state - critical for bandwidth analysis */ 3577 uint32_t dsc_clock_enable; /* DSC enabled - affects bandwidth requirements */ 3578 3579 /* DSC configuration affecting bandwidth and timing */ 3580 uint32_t dsc_num_slices_h; /* Horizontal slice count - affects throughput */ 3581 uint32_t dsc_num_slices_v; /* Vertical slice count - affects throughput */ 3582 uint32_t dsc_bits_per_pixel; /* Compression ratio - affects bandwidth */ 3583 3584 /* OPP integration - affects pipeline flow */ 3585 uint32_t dscrm_dsc_forward_enable; /* DSC forwarding to OPP enabled */ 3586 uint32_t dscrm_dsc_opp_pipe_source; /* Which OPP receives DSC output */ 3587 } dsc[MAX_PIPES]; 3588 3589 /* MPC register programming variables */ 3590 struct { 3591 /* MPCC blending tree and mode control */ 3592 uint32_t mpcc_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_MODE from blend_cfg.blend_mode */ 3593 uint32_t mpcc_alpha_blend_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_BLND_MODE from blend_cfg.alpha_mode */ 3594 uint32_t mpcc_alpha_multiplied_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_ALPHA_MULTIPLIED_MODE from blend_cfg.pre_multiplied_alpha */ 3595 uint32_t mpcc_blnd_active_overlap_only[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BLND_ACTIVE_OVERLAP_ONLY from blend_cfg.overlap_only */ 3596 uint32_t mpcc_global_alpha[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_ALPHA from blend_cfg.global_alpha */ 3597 uint32_t mpcc_global_gain[MAX_PIPES]; /* MPCC_CONTROL->MPCC_GLOBAL_GAIN from blend_cfg.global_gain */ 3598 uint32_t mpcc_bg_bpc[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BG_BPC from background color depth */ 3599 uint32_t mpcc_bot_gain_mode[MAX_PIPES]; /* MPCC_CONTROL->MPCC_BOT_GAIN_MODE from bottom layer gain control */ 3600 3601 /* MPCC blending tree connections */ 3602 uint32_t mpcc_bot_sel[MAX_PIPES]; /* MPCC_BOT_SEL->MPCC_BOT_SEL from mpcc_state->bot_sel */ 3603 uint32_t mpcc_top_sel[MAX_PIPES]; /* MPCC_TOP_SEL->MPCC_TOP_SEL from mpcc_state->dpp_id */ 3604 3605 /* MPCC output gamma control */ 3606 uint32_t mpcc_ogam_mode[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_MODE from output gamma mode */ 3607 uint32_t mpcc_ogam_select[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_SELECT from gamma LUT bank selection */ 3608 uint32_t mpcc_ogam_pwl_disable[MAX_PIPES]; /* MPCC_OGAM_CONTROL->MPCC_OGAM_PWL_DISABLE from PWL control */ 3609 3610 /* MPCC pipe assignment and status */ 3611 uint32_t mpcc_opp_id[MAX_PIPES]; /* MPCC_OPP_ID->MPCC_OPP_ID from mpcc_state->opp_id */ 3612 uint32_t mpcc_idle[MAX_PIPES]; /* MPCC_STATUS->MPCC_IDLE from mpcc idle status */ 3613 uint32_t mpcc_busy[MAX_PIPES]; /* MPCC_STATUS->MPCC_BUSY from mpcc busy status */ 3614 3615 /* MPC output processing */ 3616 uint32_t mpc_out_csc_mode; /* MPC_OUT_CSC_COEF->MPC_OUT_CSC_MODE from output_csc */ 3617 uint32_t mpc_out_gamma_mode; /* MPC_OUT_GAMMA_LUT->MPC_OUT_GAMMA_MODE from output_gamma */ 3618 } mpc; 3619 3620 /* OPP register programming variables for each pipe */ 3621 struct { 3622 /* Display Pattern Generator (DPG) Control - 19 fields from DPG_CONTROL register */ 3623 uint32_t dpg_enable; /* DPG_CONTROL->DPG_EN from test_pattern parameter (enable/disable) */ 3624 3625 /* Format Control (FMT) - 18 fields from FMT_CONTROL register */ 3626 uint32_t fmt_pixel_encoding; /* FMT_CONTROL->FMT_PIXEL_ENCODING from clamping->pixel_encoding */ 3627 uint32_t fmt_subsampling_mode; /* FMT_CONTROL->FMT_SUBSAMPLING_MODE from force_chroma_subsampling_1tap */ 3628 uint32_t fmt_cbcr_bit_reduction_bypass; /* FMT_CONTROL->FMT_CBCR_BIT_REDUCTION_BYPASS from pixel_encoding bypass control */ 3629 uint32_t fmt_stereosync_override; /* FMT_CONTROL->FMT_STEREOSYNC_OVERRIDE from stereo timing override */ 3630 uint32_t fmt_spatial_dither_frame_counter_max; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX from fmt_bit_depth->flags */ 3631 uint32_t fmt_spatial_dither_frame_counter_bit_swap; /* FMT_CONTROL->FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP from dither control */ 3632 uint32_t fmt_truncate_enable; /* FMT_CONTROL->FMT_TRUNCATE_EN from fmt_bit_depth->flags.TRUNCATE_ENABLED */ 3633 uint32_t fmt_truncate_depth; /* FMT_CONTROL->FMT_TRUNCATE_DEPTH from fmt_bit_depth->flags.TRUNCATE_DEPTH */ 3634 uint32_t fmt_truncate_mode; /* FMT_CONTROL->FMT_TRUNCATE_MODE from fmt_bit_depth->flags.TRUNCATE_MODE */ 3635 uint32_t fmt_spatial_dither_enable; /* FMT_CONTROL->FMT_SPATIAL_DITHER_EN from fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED */ 3636 uint32_t fmt_spatial_dither_mode; /* FMT_CONTROL->FMT_SPATIAL_DITHER_MODE from fmt_bit_depth->flags.SPATIAL_DITHER_MODE */ 3637 uint32_t fmt_spatial_dither_depth; /* FMT_CONTROL->FMT_SPATIAL_DITHER_DEPTH from fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH */ 3638 uint32_t fmt_temporal_dither_enable; /* FMT_CONTROL->FMT_TEMPORAL_DITHER_EN from fmt_bit_depth->flags.TEMPORAL_DITHER_ENABLED */ 3639 uint32_t fmt_clamp_data_enable; /* FMT_CONTROL->FMT_CLAMP_DATA_EN from clamping->clamping_range enable */ 3640 uint32_t fmt_clamp_color_format; /* FMT_CONTROL->FMT_CLAMP_COLOR_FORMAT from clamping->color_format */ 3641 uint32_t fmt_dynamic_exp_enable; /* FMT_CONTROL->FMT_DYNAMIC_EXP_EN from color_sp/color_dpth/signal */ 3642 uint32_t fmt_dynamic_exp_mode; /* FMT_CONTROL->FMT_DYNAMIC_EXP_MODE from color space mode mapping */ 3643 uint32_t fmt_bit_depth_control; /* Legacy field - kept for compatibility */ 3644 3645 /* OPP Pipe Control - 1 field from OPP_PIPE_CONTROL register */ 3646 uint32_t opp_pipe_clock_enable; /* OPP_PIPE_CONTROL->OPP_PIPE_CLOCK_EN from enable parameter (bool) */ 3647 3648 /* OPP CRC Control - 3 fields from OPP_PIPE_CRC_CONTROL register */ 3649 uint32_t opp_crc_enable; /* OPP_PIPE_CRC_CONTROL->CRC_EN from CRC enable control */ 3650 uint32_t opp_crc_select_source; /* OPP_PIPE_CRC_CONTROL->CRC_SELECT_SOURCE from CRC source selection */ 3651 uint32_t opp_crc_stereo_cont; /* OPP_PIPE_CRC_CONTROL->CRC_STEREO_CONT from stereo continuous CRC */ 3652 3653 /* Output Buffer (OPPBUF) Control - 6 fields from OPPBUF_CONTROL register */ 3654 uint32_t oppbuf_active_width; /* OPPBUF_CONTROL->OPPBUF_ACTIVE_WIDTH from oppbuf_params->active_width */ 3655 uint32_t oppbuf_pixel_repetition; /* OPPBUF_CONTROL->OPPBUF_PIXEL_REPETITION from oppbuf_params->pixel_repetition */ 3656 uint32_t oppbuf_display_segmentation; /* OPPBUF_CONTROL->OPPBUF_DISPLAY_SEGMENTATION from oppbuf_params->mso_segmentation */ 3657 uint32_t oppbuf_overlap_pixel_num; /* OPPBUF_CONTROL->OPPBUF_OVERLAP_PIXEL_NUM from oppbuf_params->mso_overlap_pixel_num */ 3658 uint32_t oppbuf_3d_vact_space1_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE1_SIZE from 3D timing space1_size */ 3659 uint32_t oppbuf_3d_vact_space2_size; /* OPPBUF_CONTROL->OPPBUF_3D_VACT_SPACE2_SIZE from 3D timing space2_size */ 3660 3661 /* DSC Forward Config - 3 fields from DSCRM_DSC_FORWARD_CONFIG register */ 3662 uint32_t dscrm_dsc_forward_enable; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN from DSC forward enable control */ 3663 uint32_t dscrm_dsc_opp_pipe_source; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_OPP_PIPE_SOURCE from opp_pipe parameter */ 3664 uint32_t dscrm_dsc_forward_enable_status; /* DSCRM_DSC_FORWARD_CONFIG->DSCRM_DSC_FORWARD_EN_STATUS from DSC forward status (read-only) */ 3665 } opp[MAX_PIPES]; 3666 3667 /* OPTC register programming variables for each pipe */ 3668 struct { 3669 uint32_t otg_master_inst; 3670 3671 /* OTG_CONTROL register - 5 fields for OTG control */ 3672 uint32_t otg_master_enable; /* OTG_CONTROL->OTG_MASTER_EN from timing enable/disable control */ 3673 uint32_t otg_disable_point_cntl; /* OTG_CONTROL->OTG_DISABLE_POINT_CNTL from disable timing control */ 3674 uint32_t otg_start_point_cntl; /* OTG_CONTROL->OTG_START_POINT_CNTL from start timing control */ 3675 uint32_t otg_field_number_cntl; /* OTG_CONTROL->OTG_FIELD_NUMBER_CNTL from interlace field control */ 3676 uint32_t otg_out_mux; /* OTG_CONTROL->OTG_OUT_MUX from output mux selection */ 3677 3678 /* OTG Horizontal Timing - 7 fields */ 3679 uint32_t otg_h_total; /* OTG_H_TOTAL->OTG_H_TOTAL from dc_crtc_timing->h_total */ 3680 uint32_t otg_h_blank_start; /* OTG_H_BLANK_START_END->OTG_H_BLANK_START from dc_crtc_timing->h_front_porch */ 3681 uint32_t otg_h_blank_end; /* OTG_H_BLANK_START_END->OTG_H_BLANK_END from dc_crtc_timing->h_addressable_video_pixel_width */ 3682 uint32_t otg_h_sync_start; /* OTG_H_SYNC_A->OTG_H_SYNC_A_START from dc_crtc_timing->h_sync_width */ 3683 uint32_t otg_h_sync_end; /* OTG_H_SYNC_A->OTG_H_SYNC_A_END from calculated sync end position */ 3684 uint32_t otg_h_sync_polarity; /* OTG_H_SYNC_A_CNTL->OTG_H_SYNC_A_POL from dc_crtc_timing->flags.HSYNC_POSITIVE_POLARITY */ 3685 uint32_t otg_h_timing_div_mode; /* OTG_H_TIMING_CNTL->OTG_H_TIMING_DIV_MODE from horizontal timing division mode */ 3686 3687 /* OTG Vertical Timing - 7 fields */ 3688 uint32_t otg_v_total; /* OTG_V_TOTAL->OTG_V_TOTAL from dc_crtc_timing->v_total */ 3689 uint32_t otg_v_blank_start; /* OTG_V_BLANK_START_END->OTG_V_BLANK_START from dc_crtc_timing->v_front_porch */ 3690 uint32_t otg_v_blank_end; /* OTG_V_BLANK_START_END->OTG_V_BLANK_END from dc_crtc_timing->v_addressable_video_line_width */ 3691 uint32_t otg_v_sync_start; /* OTG_V_SYNC_A->OTG_V_SYNC_A_START from dc_crtc_timing->v_sync_width */ 3692 uint32_t otg_v_sync_end; /* OTG_V_SYNC_A->OTG_V_SYNC_A_END from calculated sync end position */ 3693 uint32_t otg_v_sync_polarity; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_A_POL from dc_crtc_timing->flags.VSYNC_POSITIVE_POLARITY */ 3694 uint32_t otg_v_sync_mode; /* OTG_V_SYNC_A_CNTL->OTG_V_SYNC_MODE from sync mode selection */ 3695 3696 /* OTG DRR (Dynamic Refresh Rate) Control - 8 fields */ 3697 uint32_t otg_v_total_max; /* OTG_V_TOTAL_MAX->OTG_V_TOTAL_MAX from drr_params->vertical_total_max */ 3698 uint32_t otg_v_total_min; /* OTG_V_TOTAL_MIN->OTG_V_TOTAL_MIN from drr_params->vertical_total_min */ 3699 uint32_t otg_v_total_mid; /* OTG_V_TOTAL_MID->OTG_V_TOTAL_MID from drr_params->vertical_total_mid */ 3700 uint32_t otg_v_total_max_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MAX_SEL from DRR max selection enable */ 3701 uint32_t otg_v_total_min_sel; /* OTG_V_TOTAL_CONTROL->OTG_V_TOTAL_MIN_SEL from DRR min selection enable */ 3702 uint32_t otg_vtotal_mid_replacing_max_en; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_REPLACING_MAX_EN from DRR mid-frame enable */ 3703 uint32_t otg_vtotal_mid_frame_num; /* OTG_V_TOTAL_CONTROL->OTG_VTOTAL_MID_FRAME_NUM from drr_params->vertical_total_mid_frame_num */ 3704 uint32_t otg_set_v_total_min_mask; /* OTG_V_TOTAL_CONTROL->OTG_SET_V_TOTAL_MIN_MASK from DRR trigger mask */ 3705 uint32_t otg_force_lock_on_event; /* OTG_V_TOTAL_CONTROL->OTG_FORCE_LOCK_ON_EVENT from DRR force lock control */ 3706 3707 /* OPTC Data Source and ODM - 6 fields */ 3708 uint32_t optc_seg0_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG0_SRC_SEL from opp_id[0] ODM segment 0 source */ 3709 uint32_t optc_seg1_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG1_SRC_SEL from opp_id[1] ODM segment 1 source */ 3710 uint32_t optc_seg2_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG2_SRC_SEL from opp_id[2] ODM segment 2 source */ 3711 uint32_t optc_seg3_src_sel; /* OPTC_DATA_SOURCE_SELECT->OPTC_SEG3_SRC_SEL from opp_id[3] ODM segment 3 source */ 3712 uint32_t optc_num_of_input_segment; /* OPTC_DATA_SOURCE_SELECT->OPTC_NUM_OF_INPUT_SEGMENT from opp_cnt-1 number of input segments */ 3713 uint32_t optc_mem_sel; /* OPTC_MEMORY_CONFIG->OPTC_MEM_SEL from memory_mask ODM memory selection */ 3714 3715 /* OPTC Data Format and DSC - 4 fields */ 3716 uint32_t optc_data_format; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DATA_FORMAT from data format selection */ 3717 uint32_t optc_dsc_mode; /* OPTC_DATA_FORMAT_CONTROL->OPTC_DSC_MODE from dsc_mode parameter */ 3718 uint32_t optc_dsc_bytes_per_pixel; /* OPTC_BYTES_PER_PIXEL->OPTC_DSC_BYTES_PER_PIXEL from dsc_bytes_per_pixel parameter */ 3719 uint32_t optc_segment_width; /* OPTC_WIDTH_CONTROL->OPTC_SEGMENT_WIDTH from segment_width parameter */ 3720 uint32_t optc_dsc_slice_width; /* OPTC_WIDTH_CONTROL->OPTC_DSC_SLICE_WIDTH from dsc_slice_width parameter */ 3721 3722 /* OPTC Clock and Underflow Control - 4 fields */ 3723 uint32_t optc_input_pix_clk_en; /* OPTC_INPUT_CLOCK_CONTROL->OPTC_INPUT_PIX_CLK_EN from pixel clock enable */ 3724 uint32_t optc_underflow_occurred_status; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_OCCURRED_STATUS from underflow status (read-only) */ 3725 uint32_t optc_underflow_clear; /* OPTC_INPUT_GLOBAL_CONTROL->OPTC_UNDERFLOW_CLEAR from underflow clear control */ 3726 uint32_t otg_clock_enable; /* OTG_CLOCK_CONTROL->OTG_CLOCK_EN from OTG clock enable */ 3727 uint32_t otg_clock_gate_dis; /* OTG_CLOCK_CONTROL->OTG_CLOCK_GATE_DIS from clock gate disable */ 3728 3729 /* OTG Stereo and 3D Control - 6 fields */ 3730 uint32_t otg_stereo_enable; /* OTG_STEREO_CONTROL->OTG_STEREO_EN from stereo enable control */ 3731 uint32_t otg_stereo_sync_output_line_num; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_LINE_NUM from timing->stereo_3d_format line num */ 3732 uint32_t otg_stereo_sync_output_polarity; /* OTG_STEREO_CONTROL->OTG_STEREO_SYNC_OUTPUT_POLARITY from stereo polarity control */ 3733 uint32_t otg_3d_structure_en; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_EN from 3D structure enable */ 3734 uint32_t otg_3d_structure_v_update_mode; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_V_UPDATE_MODE from 3D vertical update mode */ 3735 uint32_t otg_3d_structure_stereo_sel_ovr; /* OTG_3D_STRUCTURE_CONTROL->OTG_3D_STRUCTURE_STEREO_SEL_OVR from 3D stereo selection override */ 3736 uint32_t otg_interlace_enable; /* OTG_INTERLACE_CONTROL->OTG_INTERLACE_ENABLE from dc_crtc_timing->flags.INTERLACE */ 3737 3738 /* OTG GSL (Global Sync Lock) Control - 5 fields */ 3739 uint32_t otg_gsl0_en; /* OTG_GSL_CONTROL->OTG_GSL0_EN from GSL group 0 enable */ 3740 uint32_t otg_gsl1_en; /* OTG_GSL_CONTROL->OTG_GSL1_EN from GSL group 1 enable */ 3741 uint32_t otg_gsl2_en; /* OTG_GSL_CONTROL->OTG_GSL2_EN from GSL group 2 enable */ 3742 uint32_t otg_gsl_master_en; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_EN from GSL master enable */ 3743 uint32_t otg_gsl_master_mode; /* OTG_GSL_CONTROL->OTG_GSL_MASTER_MODE from gsl_params->gsl_master mode */ 3744 3745 /* OTG DRR Advanced Control - 4 fields */ 3746 uint32_t otg_v_total_last_used_by_drr; /* OTG_DRR_CONTROL->OTG_V_TOTAL_LAST_USED_BY_DRR from last used DRR V_TOTAL (read-only) */ 3747 uint32_t otg_drr_trigger_window_start_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_START_X from window_start parameter */ 3748 uint32_t otg_drr_trigger_window_end_x; /* OTG_DRR_TRIGGER_WINDOW->OTG_DRR_TRIGGER_WINDOW_END_X from window_end parameter */ 3749 uint32_t otg_drr_v_total_change_limit; /* OTG_DRR_V_TOTAL_CHANGE->OTG_DRR_V_TOTAL_CHANGE_LIMIT from limit parameter */ 3750 3751 /* OTG DSC Position Control - 2 fields */ 3752 uint32_t otg_dsc_start_position_x; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_X from DSC start X position */ 3753 uint32_t otg_dsc_start_position_line_num; /* OTG_DSC_START_POSITION->OTG_DSC_START_POSITION_LINE_NUM from DSC start line number */ 3754 3755 /* OTG Double Buffer Control - 2 fields */ 3756 uint32_t otg_drr_timing_dbuf_update_mode; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_DRR_TIMING_DBUF_UPDATE_MODE from DRR double buffer mode */ 3757 uint32_t otg_blank_data_double_buffer_en; /* OTG_DOUBLE_BUFFER_CONTROL->OTG_BLANK_DATA_DOUBLE_BUFFER_EN from blank data double buffer enable */ 3758 3759 /* OTG Vertical Interrupts - 6 fields */ 3760 uint32_t otg_vertical_interrupt0_int_enable; /* OTG_VERTICAL_INTERRUPT0_CONTROL->OTG_VERTICAL_INTERRUPT0_INT_ENABLE from interrupt 0 enable */ 3761 uint32_t otg_vertical_interrupt0_line_start; /* OTG_VERTICAL_INTERRUPT0_POSITION->OTG_VERTICAL_INTERRUPT0_LINE_START from start_line parameter */ 3762 uint32_t otg_vertical_interrupt1_int_enable; /* OTG_VERTICAL_INTERRUPT1_CONTROL->OTG_VERTICAL_INTERRUPT1_INT_ENABLE from interrupt 1 enable */ 3763 uint32_t otg_vertical_interrupt1_line_start; /* OTG_VERTICAL_INTERRUPT1_POSITION->OTG_VERTICAL_INTERRUPT1_LINE_START from start_line parameter */ 3764 uint32_t otg_vertical_interrupt2_int_enable; /* OTG_VERTICAL_INTERRUPT2_CONTROL->OTG_VERTICAL_INTERRUPT2_INT_ENABLE from interrupt 2 enable */ 3765 uint32_t otg_vertical_interrupt2_line_start; /* OTG_VERTICAL_INTERRUPT2_POSITION->OTG_VERTICAL_INTERRUPT2_LINE_START from start_line parameter */ 3766 3767 /* OTG Global Sync Parameters - 6 fields */ 3768 uint32_t otg_vready_offset; /* OTG_VREADY_PARAM->OTG_VREADY_OFFSET from vready_offset parameter */ 3769 uint32_t otg_vstartup_start; /* OTG_VSTARTUP_PARAM->OTG_VSTARTUP_START from vstartup_start parameter */ 3770 uint32_t otg_vupdate_offset; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_OFFSET from vupdate_offset parameter */ 3771 uint32_t otg_vupdate_width; /* OTG_VUPDATE_PARAM->OTG_VUPDATE_WIDTH from vupdate_width parameter */ 3772 uint32_t master_update_lock_vupdate_keepout_start_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET from pstate_keepout start */ 3773 uint32_t master_update_lock_vupdate_keepout_end_offset; /* OTG_VUPDATE_KEEPOUT->MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET from pstate_keepout end */ 3774 3775 /* OTG Manual Trigger Control - 11 fields */ 3776 uint32_t otg_triga_source_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_SELECT from trigger A source selection */ 3777 uint32_t otg_triga_source_pipe_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_SOURCE_PIPE_SELECT from trigger A pipe selection */ 3778 uint32_t otg_triga_rising_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_RISING_EDGE_DETECT_CNTL from trigger A rising edge detect */ 3779 uint32_t otg_triga_falling_edge_detect_cntl; /* OTG_TRIGA_CNTL->OTG_TRIGA_FALLING_EDGE_DETECT_CNTL from trigger A falling edge detect */ 3780 uint32_t otg_triga_polarity_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_POLARITY_SELECT from trigger A polarity selection */ 3781 uint32_t otg_triga_frequency_select; /* OTG_TRIGA_CNTL->OTG_TRIGA_FREQUENCY_SELECT from trigger A frequency selection */ 3782 uint32_t otg_triga_delay; /* OTG_TRIGA_CNTL->OTG_TRIGA_DELAY from trigger A delay */ 3783 uint32_t otg_triga_clear; /* OTG_TRIGA_CNTL->OTG_TRIGA_CLEAR from trigger A clear */ 3784 uint32_t otg_triga_manual_trig; /* OTG_TRIGA_MANUAL_TRIG->OTG_TRIGA_MANUAL_TRIG from manual trigger A */ 3785 uint32_t otg_trigb_source_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_SOURCE_SELECT from trigger B source selection */ 3786 uint32_t otg_trigb_polarity_select; /* OTG_TRIGB_CNTL->OTG_TRIGB_POLARITY_SELECT from trigger B polarity selection */ 3787 uint32_t otg_trigb_manual_trig; /* OTG_TRIGB_MANUAL_TRIG->OTG_TRIGB_MANUAL_TRIG from manual trigger B */ 3788 3789 /* OTG Static Screen and Update Control - 6 fields */ 3790 uint32_t otg_static_screen_event_mask; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_EVENT_MASK from event_triggers parameter */ 3791 uint32_t otg_static_screen_frame_count; /* OTG_STATIC_SCREEN_CONTROL->OTG_STATIC_SCREEN_FRAME_COUNT from num_frames parameter */ 3792 uint32_t master_update_lock; /* OTG_MASTER_UPDATE_LOCK->MASTER_UPDATE_LOCK from update lock control */ 3793 uint32_t master_update_mode; /* OTG_MASTER_UPDATE_MODE->MASTER_UPDATE_MODE from update mode selection */ 3794 uint32_t otg_force_count_now_mode; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_MODE from force count mode */ 3795 uint32_t otg_force_count_now_clear; /* OTG_FORCE_COUNT_NOW_CNTL->OTG_FORCE_COUNT_NOW_CLEAR from force count clear */ 3796 3797 /* VTG Control - 3 fields */ 3798 uint32_t vtg0_enable; /* CONTROL->VTG0_ENABLE from VTG enable control */ 3799 uint32_t vtg0_fp2; /* CONTROL->VTG0_FP2 from VTG front porch 2 */ 3800 uint32_t vtg0_vcount_init; /* CONTROL->VTG0_VCOUNT_INIT from VTG vertical count init */ 3801 3802 /* OTG Status (Read-Only) - 12 fields */ 3803 uint32_t otg_v_blank; /* OTG_STATUS->OTG_V_BLANK from vertical blank status (read-only) */ 3804 uint32_t otg_v_active_disp; /* OTG_STATUS->OTG_V_ACTIVE_DISP from vertical active display (read-only) */ 3805 uint32_t otg_frame_count; /* OTG_STATUS_FRAME_COUNT->OTG_FRAME_COUNT from frame count (read-only) */ 3806 uint32_t otg_horz_count; /* OTG_STATUS_POSITION->OTG_HORZ_COUNT from horizontal position (read-only) */ 3807 uint32_t otg_vert_count; /* OTG_STATUS_POSITION->OTG_VERT_COUNT from vertical position (read-only) */ 3808 uint32_t otg_horz_count_hv; /* OTG_STATUS_HV_COUNT->OTG_HORZ_COUNT from horizontal count (read-only) */ 3809 uint32_t otg_vert_count_nom; /* OTG_STATUS_HV_COUNT->OTG_VERT_COUNT_NOM from vertical count nominal (read-only) */ 3810 uint32_t otg_flip_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_FLIP_PENDING from flip pending status (read-only) */ 3811 uint32_t otg_dc_reg_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_DC_REG_UPDATE_PENDING from DC register update pending (read-only) */ 3812 uint32_t otg_cursor_update_pending; /* OTG_PIPE_UPDATE_STATUS->OTG_CURSOR_UPDATE_PENDING from cursor update pending (read-only) */ 3813 uint32_t otg_vupdate_keepout_status; /* OTG_PIPE_UPDATE_STATUS->OTG_VUPDATE_KEEPOUT_STATUS from VUPDATE keepout status (read-only) */ 3814 } optc[MAX_PIPES]; 3815 3816 /* Metadata */ 3817 uint32_t active_pipe_count; 3818 uint32_t active_stream_count; 3819 bool state_valid; 3820 }; 3821 3822 /** 3823 * dc_capture_register_software_state() - Capture software state for register programming 3824 * @dc: DC context containing current display configuration 3825 * @state: Pointer to dc_register_software_state structure to populate 3826 * 3827 * Extracts all software state variables that are used to program hardware register 3828 * fields across the display driver pipeline. This provides a complete snapshot 3829 * of the software configuration that drives hardware register programming. 3830 * 3831 * The function traverses the DC context and extracts values from: 3832 * - Stream configurations (timing, format, DSC settings) 3833 * - Plane states (surface format, rotation, scaling, cursor) 3834 * - Pipe contexts (resource allocation, blending, viewport) 3835 * - Clock manager (display clocks, DPP clocks, pixel clocks) 3836 * - Resource context (DET buffer allocation, ODM configuration) 3837 * 3838 * This is essential for underflow debugging as it captures the exact software 3839 * state that determines how registers are programmed, allowing analysis of 3840 * whether underflow is caused by incorrect register programming or timing issues. 3841 * 3842 * Return: true if state was successfully captured, false on error 3843 */ 3844 bool dc_capture_register_software_state(struct dc *dc, struct dc_register_software_state *state); 3845 3846 /** 3847 * dc_get_qos_info() - Retrieve Quality of Service (QoS) information from display core 3848 * @dc: DC context containing current display configuration 3849 * @info: Pointer to dc_qos_info structure to populate with QoS metrics 3850 * 3851 * This function retrieves QoS metrics from the display core that can be used by 3852 * benchmark tools to analyze display system performance. The function may take 3853 * several milliseconds to execute due to hardware measurement requirements. 3854 * 3855 * QoS information includes: 3856 * - Bandwidth bounds (lower limits in Mbps) 3857 * - Latency bounds (upper limits in nanoseconds) 3858 * - Hardware-measured bandwidth metrics (peak/average in Mbps) 3859 * - Hardware-measured latency metrics (maximum/average in nanoseconds) 3860 * 3861 * The function will populate the provided dc_qos_info structure with current 3862 * QoS measurements. If hardware measurement functions are not available for 3863 * the current DCN version, the function returns false with zero'd info structure. 3864 * 3865 * Return: true if QoS information was successfully retrieved, false if measurement 3866 * functions are unavailable or hardware measurements cannot be performed 3867 */ 3868 bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info); 3869 3870 /** 3871 * dc_override_memory_bandwidth_request - Override the DCN nominal memory 3872 * bandwidth request sent to PMFW, independent of the current display mode. 3873 * For debug use only. 3874 * @dc: DC instance 3875 * @bw_mbps: requested bandwidth in MB/s; 0 clears the override 3876 * 3877 * Return: capped bandwidth value actually applied (MB/s) 3878 */ 3879 unsigned int dc_override_memory_bandwidth_request( 3880 struct dc *dc, 3881 unsigned int bw_mbps); 3882 3883 /** 3884 * Panel Polarity Control 3885 */ 3886 void dc_link_set_panel_polarity_enable(struct dc_link *link, bool enable); 3887 void dc_link_panel_polarity_reset(struct dc_link *link); 3888 bool dc_link_get_panel_polarity(struct dc_link *link, int32_t *polarity); 3889 3890 #endif /* DC_INTERFACE_H_ */ 3891