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Searched refs:fld (Results 1 – 25 of 42) sorted by relevance

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/linux/arch/riscv/kernel/
H A Dfpu.S71 fld f0, TASK_THREAD_F0_F0(a0)
72 fld f1, TASK_THREAD_F1_F0(a0)
73 fld f2, TASK_THREAD_F2_F0(a0)
74 fld f3, TASK_THREAD_F3_F0(a0)
75 fld f4, TASK_THREAD_F4_F0(a0)
76 fld f5, TASK_THREAD_F5_F0(a0)
77 fld f6, TASK_THREAD_F6_F0(a0)
78 fld f7, TASK_THREAD_F7_F0(a0)
79 fld f8, TASK_THREAD_F8_F0(a0)
80 fld f9, TASK_THREAD_F9_F0(a0)
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Den_stats.h45 #define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld) argument
46 #define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld) argument
47 #define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld) argument
48 #define MLX5E_DECLARE_XDPSQ_STAT(type, fld) "tx%d_xdp_"#fld, offsetof(type, fld) argument
49 #define MLX5E_DECLARE_RQ_XDPSQ_STAT(type, fld) "rx%d_xdp_tx_"#fld, offsetof(type, fld) argument
50 #define MLX5E_DECLARE_XSKRQ_STAT(type, fld) "rx%d_xsk_"#fld, offsetof(type, fld) argument
51 #define MLX5E_DECLARE_XSKSQ_STAT(type, fld) "tx%d_xsk_"#fld, offsetof(type, fld) argument
52 #define MLX5E_DECLARE_CH_STAT(type, fld) "ch%d_"#fld, offsetof(type, fld) argument
54 #define MLX5E_DECLARE_PTP_TX_STAT(type, fld) "ptp_tx%d_"#fld, offsetof(type, fld) argument
55 #define MLX5E_DECLARE_PTP_CH_STAT(type, fld) "ptp_ch_"#fld, offsetof(type, fld) argument
[all …]
/linux/scripts/coccinelle/misc/
H A Ddoubleinit.cocci18 identifier I, s, fld;
23 struct I s =@p0 { ..., .fld@p = E, ...};
26 identifier I, s, r.fld;
31 struct I s =@p0 { ..., .fld@p = E, ...};
35 fld << r.fld;
41 cocci.print_main(fld,p0)
47 fld << r.fld;
53 msg = "%s: first occurrence line %s, second occurrence line %s" % (fld,ps[0].line,pr[0].line)
/linux/drivers/net/ethernet/mellanox/mlx5/core/diag/
H A Dfs_tracepoint.c39 #define MASK_VAL(type, spec, name, mask, val, fld) \ argument
41 {.m = MLX5_GET(spec, mask, fld),\
42 .v = MLX5_GET(spec, val, fld)}
43 #define MASK_VAL_BE(type, spec, name, mask, val, fld) \ argument
45 {.m = MLX5_GET_BE(type, spec, mask, fld),\
46 .v = MLX5_GET_BE(type, spec, val, fld)}
49 #define GET_MASK_VAL(name, type, mask, val, fld) \ argument
50 (name.m = MLX5_GET(type, mask, fld), \
51 name.v = MLX5_GET(type, val, fld), \
66 #define MASK_VAL_L2(type, name, fld) \ in print_lyr_2_4_hdrs() argument
[all …]
/linux/arch/loongarch/kernel/
H A Dfpu.S65 EX fld.d $f0, \base, (0 * FPU_REG_WIDTH)
66 EX fld.d $f1, \base, (1 * FPU_REG_WIDTH)
67 EX fld.d $f2, \base, (2 * FPU_REG_WIDTH)
68 EX fld.d $f3, \base, (3 * FPU_REG_WIDTH)
69 EX fld.d $f4, \base, (4 * FPU_REG_WIDTH)
70 EX fld.d $f5, \base, (5 * FPU_REG_WIDTH)
71 EX fld.d $f6, \base, (6 * FPU_REG_WIDTH)
72 EX fld.d $f7, \base, (7 * FPU_REG_WIDTH)
73 EX fld.d $f8, \base, (8 * FPU_REG_WIDTH)
74 EX fld.d $f9, \base, (9 * FPU_REG_WIDTH)
[all …]
/linux/scripts/gcc-plugins/
H A Dlatent_entropy_plugin.c167 tree fld, lst = TYPE_FIELDS(type); in handle_latent_entropy_attribute() local
170 for (fld = lst; fld; nelt++, fld = TREE_CHAIN(fld)) { in handle_latent_entropy_attribute()
173 fieldtype = TREE_TYPE(fld); in handle_latent_entropy_attribute()
179 *node, name, fld); in handle_latent_entropy_attribute()
183 if (fld) in handle_latent_entropy_attribute()
188 for (fld = lst; fld; fld = TREE_CHAIN(fld)) { in handle_latent_entropy_attribute()
189 tree random_const, fld_t = TREE_TYPE(fld); in handle_latent_entropy_attribute()
192 CONSTRUCTOR_APPEND_ELT(vals, fld, random_const); in handle_latent_entropy_attribute()
/linux/drivers/accel/ivpu/
H A Divpu_hw_reg_io.h50 #define REGB_POLL_FLD(reg, fld, val, timeout_us) \ argument
55 __func__, #reg, reg, #fld, val); \
56 r = read_poll_timeout(REGB_RD32_SILENT, var, (FIELD_GET(reg##_##fld##_MASK, var) == (val)),\
59 __func__, #reg, reg, #fld, r ? "ETIMEDOUT" : "OK", var); \
63 #define REGV_POLL_FLD(reg, fld, val, timeout_us) \ argument
68 __func__, #reg, reg, #fld, val); \
69 r = read_poll_timeout(REGV_RD32_SILENT, var, (FIELD_GET(reg##_##fld##_MASK, var) == (val)),\
72 __func__, #reg, reg, #fld, r ? "ETIMEDOUT" : "OK", var); \
/linux/arch/arm64/include/asm/
H A Dkvm_host.h1473 #define __expand_field_sign_unsigned(id, fld, val) \ argument
1474 ((u64)SYS_FIELD_VALUE(id, fld, val))
1476 #define __expand_field_sign_signed(id, fld, val) \ argument
1478 u64 __val = SYS_FIELD_VALUE(id, fld, val); \
1479 sign_extend64(__val, id##_##fld##_WIDTH - 1); \
1482 #define get_idreg_field_unsigned(kvm, id, fld) \ argument
1485 FIELD_GET(id##_##fld##_MASK, __val); \
1488 #define get_idreg_field_signed(kvm, id, fld) \ argument
1490 u64 __val = get_idreg_field_unsigned(kvm, id, fld); \
1491 sign_extend64(__val, id##_##fld##_WIDTH - 1); \
[all …]
H A Del2_setup.h313 .macro __check_override idreg, fld, width, pass, fail, tmp1, tmp2
314 ubfx \tmp1, \tmp1, #\fld, #\width
320 ubfx \tmp2, \tmp2, #\fld, #\width
321 ubfx \tmp1, \tmp1, #\fld, #\width
330 .macro check_override idreg, fld, pass, fail, tmp1, tmp2
332 __check_override \idreg \fld 4 \pass \fail \tmp1 \tmp2
336 .macro __check_override idreg, fld, width, pass, fail, tmp, ignore
338 ubfx \tmp, \tmp, #\fld, #\width
343 .macro check_override idreg, fld, pass, fail, tmp, ignore
344 __check_override \idreg \fld 4 \pass \fail \tmp \ignore
/linux/arch/loongarch/include/asm/
H A Dasmmacro.h171 fld.d $f0, \tmp, THREAD_FPR0 - THREAD_FPR0
172 fld.d $f1, \tmp, THREAD_FPR1 - THREAD_FPR0
173 fld.d $f2, \tmp, THREAD_FPR2 - THREAD_FPR0
174 fld.d $f3, \tmp, THREAD_FPR3 - THREAD_FPR0
175 fld.d $f4, \tmp, THREAD_FPR4 - THREAD_FPR0
176 fld.d $f5, \tmp, THREAD_FPR5 - THREAD_FPR0
177 fld.d $f6, \tmp, THREAD_FPR6 - THREAD_FPR0
178 fld.d $f7, \tmp, THREAD_FPR7 - THREAD_FPR0
179 fld.d $f8, \tmp, THREAD_FPR8 - THREAD_FPR0
180 fld.d $f9, \tmp, THREAD_FPR9 - THREAD_FPR0
[all …]
/linux/drivers/clk/baikal-t1/
H A Dccu-pll.c385 struct ccu_pll_dbgfs_fld *fld = priv; in ccu_pll_dbgfs_fld_set() local
386 struct ccu_pll *pll = fld->pll; in ccu_pll_dbgfs_fld_set()
390 val = clamp_t(u64, val, fld->min, fld->max); in ccu_pll_dbgfs_fld_set()
391 data = ((val - 1) << fld->lsb) & fld->mask; in ccu_pll_dbgfs_fld_set()
394 regmap_update_bits(pll->sys_regs, pll->reg_ctl + fld->reg, fld->mask, in ccu_pll_dbgfs_fld_set()
427 struct ccu_pll_dbgfs_fld *fld = priv; in ccu_pll_dbgfs_fld_get() local
428 struct ccu_pll *pll = fld->pll; in ccu_pll_dbgfs_fld_get()
431 regmap_read(pll->sys_regs, pll->reg_ctl + fld->reg, &data); in ccu_pll_dbgfs_fld_get()
432 *val = ((data & fld->mask) >> fld->lsb) + 1; in ccu_pll_dbgfs_fld_get()
/linux/drivers/power/supply/
H A Dmp2629_charger.c164 enum mp2629_field fld, in mp2629_get_prop() argument
170 ret = regmap_field_read(charger->regmap_fields[fld], &rval); in mp2629_get_prop()
174 val->intval = rval * props[fld].step + props[fld].min; in mp2629_get_prop()
180 enum mp2629_field fld, in mp2629_set_prop() argument
185 if (val->intval < props[fld].min || val->intval > props[fld].max) in mp2629_set_prop()
188 rval = (val->intval - props[fld].min) / props[fld].step; in mp2629_set_prop()
189 return regmap_field_write(charger->regmap_fields[fld], rval); in mp2629_set_prop()
/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dtout.c106 #define MLX5_TIMEOUT_QUERY(fld, reg_out) \ argument
112 time_field = MLX5_ADDR_OF(dtor_reg, reg_out, fld); \
119 #define MLX5_TIMEOUT_FILL(fld, reg_out, dev, to_type, to_extra) \ argument
121 u64 fw_to = MLX5_TIMEOUT_QUERY(fld, reg_out); \
/linux/drivers/net/ethernet/intel/ice/
H A Dice_flow.c923 u8 seg, enum ice_flow_field fld, u64 match) in ice_flow_xtract_fld() argument
936 switch (fld) { in ice_flow_xtract_fld()
960 if (fld == ICE_FLOW_FIELD_IDX_IPV4_TTL) in ice_flow_xtract_fld()
962 else if (fld == ICE_FLOW_FIELD_IDX_IPV4_PROT) in ice_flow_xtract_fld()
979 if (fld == ICE_FLOW_FIELD_IDX_IPV6_TTL) in ice_flow_xtract_fld()
981 else if (fld == ICE_FLOW_FIELD_IDX_IPV6_PROT) in ice_flow_xtract_fld()
1050 sib = fld == ICE_FLOW_FIELD_IDX_ICMP_TYPE ? in ice_flow_xtract_fld()
1066 flds[fld].xtrct.prot_id = prot_id; in ice_flow_xtract_fld()
1067 flds[fld].xtrct.off = (ice_flds_info[fld].off / ese_bits) * in ice_flow_xtract_fld()
1069 flds[fld].xtrct.disp = (u8)(ice_flds_info[fld].off % ese_bits); in ice_flow_xtract_fld()
[all …]
/linux/drivers/media/platform/ti/vpe/
H A Dvpdma.h200 #define ADB_ADDR(dma_buf, str, fld) ((dma_buf)->addr + offsetof(str, fld)) argument
201 #define MMR_ADB_ADDR(buf, str, fld) ADB_ADDR(&(buf), struct str, fld) argument
/linux/drivers/net/ethernet/netronome/nfp/
H A Dnfp_net_xsk.c24 rx_ring->rxds[idx].fld.reserved = 0; in nfp_net_xsk_rx_bufs_stash()
25 rx_ring->rxds[idx].fld.meta_len_dd = 0; in nfp_net_xsk_rx_bufs_stash()
77 nfp_desc_set_dma_addr_48b(&rx_ring->rxds[wr_idx].fld, in nfp_net_xsk_rx_ring_fill_freelist()
/linux/tools/lib/bpf/
H A Dbpf_core_read.h47 #define __CORE_BITFIELD_PROBE_READ(dst, src, fld) \ argument
50 __CORE_RELO(src, fld, BYTE_SIZE), \
51 (const void *)src + __CORE_RELO(src, fld, BYTE_OFFSET))
57 #define __CORE_BITFIELD_PROBE_READ(dst, src, fld) \ argument
59 (void *)dst + (8 - __CORE_RELO(src, fld, BYTE_SIZE)), \
60 __CORE_RELO(src, fld, BYTE_SIZE), \
61 (const void *)src + __CORE_RELO(src, fld, BYTE_OFFSET))
/linux/drivers/irqchip/
H A Dirq-gic-v4.c96 unsigned long fld, reg = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); in gic_cpuif_has_vsgi() local
98 fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64PFR0_EL1_GIC_SHIFT); in gic_cpuif_has_vsgi()
100 return fld >= ID_AA64PFR0_EL1_GIC_V4P1; in gic_cpuif_has_vsgi()
/linux/arch/arm64/mm/
H A Dcontext.c45 int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1), in get_cpu_asid_bits() local
48 switch (fld) { in get_cpu_asid_bits()
51 smp_processor_id(), fld); in get_cpu_asid_bits()
/linux/scripts/coccinelle/null/
H A Dkmerr.cocci23 identifier f,fld;
27 ... when != x->fld
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_dev.c4068 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities, fld; in qed_hw_get_nvm_info() local
4165 fld = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_DRV_FLOW_CONTROL); in qed_hw_get_nvm_info()
4166 link->pause.autoneg = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); in qed_hw_get_nvm_info()
4167 link->pause.forced_rx = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); in qed_hw_get_nvm_info()
4168 link->pause.forced_tx = !!(fld & NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); in qed_hw_get_nvm_info()
4237 fld = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_EXTENDED_SPEED); in qed_hw_get_nvm_info()
4238 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_AN) in qed_hw_get_nvm_info()
4242 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G) in qed_hw_get_nvm_info()
4244 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G) in qed_hw_get_nvm_info()
4246 if (fld & NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_20G) in qed_hw_get_nvm_info()
[all …]
/linux/drivers/scsi/
H A Dvirtio_scsi.c810 #define virtscsi_config_get(vdev, fld) \ argument
812 __virtio_native_type(struct virtio_scsi_config, fld) __val; \
813 virtio_cread(vdev, struct virtio_scsi_config, fld, &__val); \
817 #define virtscsi_config_set(vdev, fld, val) \ argument
819 __virtio_native_type(struct virtio_scsi_config, fld) __val = (val); \
820 virtio_cwrite(vdev, struct virtio_scsi_config, fld, &__val); \
/linux/drivers/net/ethernet/ti/
H A Ddavinci_cpdma.c174 #define chan_read(chan, fld) readl((chan)->fld) argument
175 #define desc_read(desc, fld) readl(&(desc)->fld) argument
177 #define chan_write(chan, fld, v) writel(v, (chan)->fld) argument
178 #define desc_write(desc, fld, v) writel((u32)(v), &(desc)->fld) argument
/linux/drivers/net/ethernet/cisco/enic/
H A Dvnic_devcmd.h537 #define FILTER_FIELD_VALID(fld) (1 << (fld - 1)) argument
/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_smp.c227 int fld = blk % 3; in update_smp_state() local
231 switch (fld) { in update_smp_state()

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