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Searched refs:fence_udelay (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/clk/tegra/
H A Dclk-tegra20-emc.c96 fence_udelay(1, emc->reg); in emc_set_parent()
128 fence_udelay(1, emc->reg); in emc_set_rate()
163 fence_udelay(1, emc->reg); in emc_set_rate_and_parent()
H A Dclk-tegra210.c532 fence_udelay(1, clk_base); in tegra210_plle_hw_sequence_start()
537 fence_udelay(1, clk_base); in tegra210_plle_hw_sequence_start()
635 fence_udelay(1, clk_base); in tegra210_generic_mbist_war()
637 fence_udelay(1, clk_base); in tegra210_generic_mbist_war()
649 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
655 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
660 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
671 fence_udelay(1, clk_base); in tegra210_disp_mbist_war()
680 fence_udelay(1, clk_base); in tegra210_disp_mbist_war()
689 fence_udelay(1, clk_base); in tegra210_vic_mbist_war()
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H A Dclk-tegra-fixed.c117 fence_udelay(2, clk_base); in tegra_clk_osc_resume()
H A Dclk.c204 fence_udelay(5, clk_base); in tegra_clk_periph_resume()
210 fence_udelay(2, clk_base); in tegra_clk_periph_resume()
H A Dclk-sdmmc-mux.c158 fence_udelay(2, sdmmc_mux->reg); in clk_sdmmc_mux_set_rate()
H A Dclk.h918 #define fence_udelay(delay, reg) \ macro
H A Dclk-pll.c1864 fence_udelay(1, pll->clk_base); in _clk_plle_tegra_init_parent()