Lines Matching refs:fence_udelay
532 fence_udelay(1, clk_base); in tegra210_plle_hw_sequence_start()
537 fence_udelay(1, clk_base); in tegra210_plle_hw_sequence_start()
635 fence_udelay(1, clk_base); in tegra210_generic_mbist_war()
637 fence_udelay(1, clk_base); in tegra210_generic_mbist_war()
649 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
655 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
660 fence_udelay(1, clk_base); in tegra210_venc_mbist_war()
671 fence_udelay(1, clk_base); in tegra210_disp_mbist_war()
680 fence_udelay(1, clk_base); in tegra210_disp_mbist_war()
689 fence_udelay(1, clk_base); in tegra210_vic_mbist_war()
694 fence_udelay(1, vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW); in tegra210_vic_mbist_war()
700 fence_udelay(1, clk_base); in tegra210_vic_mbist_war()
714 fence_udelay(1, clk_base); in tegra210_ape_mbist_war()
735 fence_udelay(1, clk_base); in tegra210_ape_mbist_war()
2914 fence_udelay(5, clk_base); in tegra210_enable_pllu()
2922 fence_udelay(1, clk_base); in tegra210_enable_pllu()
2973 fence_udelay(1, clk_base); in tegra210_init_pllu()
2978 fence_udelay(1, clk_base); in tegra210_init_pllu()
3501 fence_udelay(2, clk_base); in tegra210_clk_resume()