Searched refs:fclk_p_state_change_support (Results 1 – 8 of 8) sorted by relevance
546 if (!new_clocks->fclk_p_state_change_support) { in dcn32_auto_dpm_test_log()637 bool fclk_p_state_change_support; in dcn32_update_clocks() local661 …k_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support; in dcn32_update_clocks()663 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support; in dcn32_update_clocks()665 …d_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fclk_p_stat… in dcn32_update_clocks()667 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; in dcn32_update_clocks()670 …mgr_base->ctx->dce_version != DCN_VERSION_3_21 && clk_mgr_base->clks.fclk_p_state_change_support) { in dcn32_update_clocks()735 …if (safe_to_lower && (clk_mgr_base->clks.fclk_p_state_change_support != clk_mgr_base->clks.fclk_pr… in dcn32_update_clocks()739 …e->ctx->dce_version != DCN_VERSION_3_21 && !clk_mgr_base->clks.fclk_p_state_change_support && upda… in dcn32_update_clocks()1087 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support) in dcn32_are_clock_states_equal()
436 if (!new_clocks->fclk_p_state_change_support) in dcn401_auto_dpm_test_log()786 bool fclk_p_state_change_support, uclk_p_state_change_support; in dcn401_build_update_bandwidth_clocks_sequence() local803 …k_mgr_base->clks.fclk_prev_p_state_change_support = clk_mgr_base->clks.fclk_p_state_change_support; in dcn401_build_update_bandwidth_clocks_sequence()804 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support || (total_plane_count == 0); in dcn401_build_update_bandwidth_clocks_sequence()805 …if (should_update_pstate_support(safe_to_lower, fclk_p_state_change_support, clk_mgr_base->clks.fc… in dcn401_build_update_bandwidth_clocks_sequence()806 clk_mgr_base->clks.fclk_p_state_change_support = fclk_p_state_change_support; in dcn401_build_update_bandwidth_clocks_sequence()821 …if (!clk_mgr_base->clks.fclk_p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_interna… in dcn401_build_update_bandwidth_clocks_sequence()948 if (clk_mgr_base->clks.fclk_p_state_change_support) { in dcn401_build_update_bandwidth_clocks_sequence()957 if (clk_mgr_base->clks.fclk_p_state_change_support) { in dcn401_build_update_bandwidth_clocks_sequence()1435 else if (a->fclk_p_state_change_support != b->fclk_p_state_change_support) in dcn401_are_clock_states_equal()
289 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; in dml2_calculate_rq_and_dlg_params()291 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; in dml2_calculate_rq_and_dlg_params()
604 bool fclk_p_state_change_support; member
1674 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = false; in dcn32_calculate_dlg_params()1676 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; in dcn32_calculate_dlg_params()1771 context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = true; in dcn32_calculate_dlg_params()
1082 …context->bw_ctx.bw.dcn.clk.fclk_p_state_change_support = in_ctx->v21.mode_programming.programming-… in dml21_copy_clocks_to_dc_state()
755 clocks->fclk_p_state_change_support = true; in dcn32_initialize_min_clocks()
72 clocks->fclk_p_state_change_support = true; in dcn401_initialize_min_clocks()