Searched refs:fclk_khz (Results 1 – 4 of 4) sorted by relevance
226 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz in rv1_update_clocks()237 new_clocks->fclk_khz = debug->force_fclk_khz; in rv1_update_clocks()239 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { in rv1_update_clocks()240 clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz; in rv1_update_clocks()264 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()284 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
351 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; in dcn2_update_clocks_fpga()378 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { in dcn2_update_clocks_fpga()379 clk_mgr->clks.fclk_khz = fclk_adj; in dcn2_update_clocks_fpga()390 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) in dcn2_update_clocks_fpga()391 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; in dcn2_update_clocks_fpga()392 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) in dcn2_update_clocks_fpga()393 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; in dcn2_update_clocks_fpga()396 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; in dcn2_update_clocks_fpga()
570 context->bw_ctx.bw.dcn.clk.fclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
684 int fclk_khz; member