Searched refs:fclk_khz (Results 1 – 6 of 6) sorted by relevance
1256 int fclk_adj = new_clocks->fclk_khz; in dcn35_update_clocks_fpga()1264 new_clocks->fclk_khz = 4320000; in dcn35_update_clocks_fpga()1291 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { in dcn35_update_clocks_fpga()1292 clk_mgr->clks.fclk_khz = fclk_adj; in dcn35_update_clocks_fpga()1303 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) in dcn35_update_clocks_fpga()1304 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; in dcn35_update_clocks_fpga()1305 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) in dcn35_update_clocks_fpga()1306 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; in dcn35_update_clocks_fpga()1309 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; in dcn35_update_clocks_fpga()
417 …out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabr… in dml2_validate_and_build_resource()475 …out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabr… in dml2_validate_and_build_resource()
859 fclk_khz_override = new_clocks->fclk_khz; in dcn60_auto_dpm_test_log()879 new_clocks->fclk_khz > 0 && in dcn60_auto_dpm_test_log()
1425 …ycles / (max_sop.uclk_khz / 1000.0) + min_return_fclk_cycles / (max_sop.fclk_khz / 1000.0)) * mode… in dcn5_mode_programming()1430 DML_LOG_VERBOSE("DML::%s: max_sop.fclk_khz = %d\n", __func__, max_sop.fclk_khz); in dcn5_mode_programming()1433 DML_LOG_VERBOSE("DML::%s: min_sop.fclk_khz = %d\n", __func__, min_sop.fclk_khz); in dcn5_mode_programming()1747 mode_lib->mp.FabricClock = programming->min_clocks.dcn4x.active.fclk_khz / 1000.0; in dcn5_mp_assign_qos_bound()
760 int fclk_khz; member
8147 info->dcn_bandwidth_ub_in_mbps = (uint32_t)(clk->fclk_khz / 1000 * 64); in dc_get_qos_info()