| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 226 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz in rv1_update_clocks()
237 new_clocks->fclk_khz = debug->force_fclk_khz; in rv1_update_clocks()
239 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { in rv1_update_clocks()
240 clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz; in rv1_update_clocks()
264 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
284 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/ |
| H A D | dml2_dpmm_dcn4.c | 86 …in_out->programming->min_clocks.dcn4x.active.fclk_khz = dml_round_up(min_fclk_bw > min_fclk_latenc… in calculate_system_active_minimums()
126 …in_out->programming->min_clocks.dcn4x.svp_prefetch.fclk_khz = dml_round_up(min_fclk_bw > min_fclk_… in calculate_svp_prefetch_minimums()
150 …in_out->programming->min_clocks.dcn4x.idle.fclk_khz = dml_round_up(min_fclk_avg > min_fclk_latency… in calculate_idle_minimums()
257 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.active.fclk_khz, &state_table->fclk); in map_soc_min_clocks_to_dpm_fine_grained()
264 …result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.svp_prefetch.fclk_khz, &state_table->… in map_soc_min_clocks_to_dpm_fine_grained()
271 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.idle.fclk_khz, &state_table->fclk); in map_soc_min_clocks_to_dpm_fine_grained()
286 display_cfg->min_clocks.dcn4x.active.fclk_khz <= state_table->fclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
289 display_cfg->min_clocks.dcn4x.active.fclk_khz = state_table->fclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
300 display_cfg->min_clocks.dcn4x.idle.fclk_khz <= state_table->fclk.clk_values_khz[index] && in map_soc_min_clocks_to_dpm_coarse_grained()
303 display_cfg->min_clocks.dcn4x.idle.fclk_khz = state_table->fclk.clk_values_khz[index]; in map_soc_min_clocks_to_dpm_coarse_grained()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 351 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; in dcn2_update_clocks_fpga()
378 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { in dcn2_update_clocks_fpga()
379 clk_mgr->clks.fclk_khz = fclk_adj; in dcn2_update_clocks_fpga()
390 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) in dcn2_update_clocks_fpga()
391 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; in dcn2_update_clocks_fpga()
392 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) in dcn2_update_clocks_fpga()
393 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; in dcn2_update_clocks_fpga()
396 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; in dcn2_update_clocks_fpga()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| H A D | dml_top_types.h | 372 unsigned long fclk_khz; member
382 unsigned long fclk_khz; member
387 unsigned long fclk_khz; member
392 unsigned long fclk_khz; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 1013 int fclk_adj = new_clocks->fclk_khz; in dcn35_update_clocks_fpga()
1021 new_clocks->fclk_khz = 4320000; in dcn35_update_clocks_fpga()
1048 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { in dcn35_update_clocks_fpga()
1049 clk_mgr->clks.fclk_khz = fclk_adj; in dcn35_update_clocks_fpga()
1060 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) in dcn35_update_clocks_fpga()
1061 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; in dcn35_update_clocks_fpga()
1062 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) in dcn35_update_clocks_fpga()
1063 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; in dcn35_update_clocks_fpga()
1066 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; in dcn35_update_clocks_fpga()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 415 fclk_khz_override = new_clocks->fclk_khz; in dcn401_auto_dpm_test_log()
436 new_clocks->fclk_khz > 0 && in dcn401_auto_dpm_test_log()
954 int active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz); in dcn401_build_update_bandwidth_clocks_sequence()
1114 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { in dcn401_build_update_bandwidth_clocks_sequence()
1115 clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz; in dcn401_build_update_bandwidth_clocks_sequence()
1119 active_fclk_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.fclk_khz); in dcn401_build_update_bandwidth_clocks_sequence()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/ |
| H A D | dml2_internal_shared_types.h | 191 unsigned long fclk_khz; member
200 unsigned long fclk_khz; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_wrapper.h | 61 unsigned int fclk_khz; member
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| H A D | dml2_utils.c | 187 context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz; in dml2_copy_clocks_to_dc_state()
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| H A D | dml2_wrapper.c | 578 …out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabr… in dml2_validate_and_build_resource()
636 …out_clks.fclk_khz = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].fabr… in dml2_validate_and_build_resource()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4.c | 431 …in_out->mode_support_result.global.active.fclk_khz = (unsigned long)(core->clean_me_up.mode_lib.ms… in core_dcn4_mode_support()
435 …in_out->mode_support_result.global.svp_prefetch.fclk_khz = (unsigned long)core->clean_me_up.mode_l… in core_dcn4_mode_support()
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| H A D | dml2_core_shared.c | 9839 mode_lib->mp.FabricClock = programming->min_clocks.dcn4x.active.fclk_khz / 1000.0; in dml2_core_shared_mode_programming()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 539 fclk_khz_override = new_clocks->fclk_khz; in dcn32_auto_dpm_test_log()
560 new_clocks->fclk_khz > 0 && in dcn32_auto_dpm_test_log()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 1157 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / in dcn_validate_bandwidth()
1160 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32); in dcn_validate_bandwidth()
1424 dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz); in dcn_find_dcfclk_suits_all()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 570 context->bw_ctx.bw.dcn.clk.fclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 1660 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn32_calculate_dlg_params()
1769 context->bw_ctx.bw.dcn.clk.fclk_khz = 0; in dcn32_calculate_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1163 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn20_calculate_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 529 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_log_hw_state()
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