1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __BCMASP_H
3 #define __BCMASP_H
4
5 #include <linux/netdevice.h>
6 #include <linux/phy.h>
7 #include <linux/io-64-nonatomic-hi-lo.h>
8 #include <uapi/linux/ethtool.h>
9
10 #define ASP_INTR2_OFFSET 0x1000
11 #define ASP_INTR2_STATUS 0x0
12 #define ASP_INTR2_SET 0x4
13 #define ASP_INTR2_CLEAR 0x8
14 #define ASP_INTR2_MASK_STATUS 0xc
15 #define ASP_INTR2_MASK_SET 0x10
16 #define ASP_INTR2_MASK_CLEAR 0x14
17
18 #define ASP_INTR2_RX_ECH(intr) BIT(intr)
19 #define ASP_INTR2_TX_DESC(intr) BIT((intr) + 14)
20 #define ASP_INTR2_UMC0_WAKE BIT(22)
21 #define ASP_INTR2_UMC1_WAKE BIT(28)
22 #define ASP_INTR2_PHY_EVENT(intr) ((intr) ? BIT(30) | BIT(31) : \
23 BIT(24) | BIT(25))
24
25 #define ASP_WAKEUP_INTR2_OFFSET 0x1200
26 #define ASP_WAKEUP_INTR2_STATUS 0x0
27 #define ASP_WAKEUP_INTR2_SET 0x4
28 #define ASP_WAKEUP_INTR2_CLEAR 0x8
29 #define ASP_WAKEUP_INTR2_MASK_STATUS 0xc
30 #define ASP_WAKEUP_INTR2_MASK_SET 0x10
31 #define ASP_WAKEUP_INTR2_MASK_CLEAR 0x14
32 #define ASP_WAKEUP_INTR2_MPD_0 BIT(0)
33 #define ASP_WAKEUP_INTR2_MPD_1 BIT(1)
34 #define ASP_WAKEUP_INTR2_FILT_0 BIT(2)
35 #define ASP_WAKEUP_INTR2_FILT_1 BIT(3)
36 #define ASP_WAKEUP_INTR2_FW BIT(4)
37
38 #define ASP_CTRL2_OFFSET 0x2000
39 #define ASP_CTRL2_CORE_CLOCK_SELECT 0x0
40 #define ASP_CTRL2_CORE_CLOCK_SELECT_MAIN BIT(0)
41 #define ASP_CTRL2_CPU_CLOCK_SELECT 0x4
42 #define ASP_CTRL2_CPU_CLOCK_SELECT_MAIN BIT(0)
43
44 #define ASP_TX_ANALYTICS_OFFSET 0x4c000
45 #define ASP_TX_ANALYTICS_CTRL 0x0
46
47 #define ASP_RX_ANALYTICS_OFFSET 0x98000
48 #define ASP_RX_ANALYTICS_CTRL 0x0
49
50 #define ASP_RX_CTRL_OFFSET 0x9f000
51 #define ASP_RX_CTRL_UMAC_0_FRAME_COUNT 0x8
52 #define ASP_RX_CTRL_UMAC_1_FRAME_COUNT 0xc
53 #define ASP_RX_CTRL_FB_0_FRAME_COUNT 0x14
54 #define ASP_RX_CTRL_FB_1_FRAME_COUNT 0x18
55 #define ASP_RX_CTRL_FB_8_FRAME_COUNT 0x1c
56 #define ASP_RX_CTRL_FB_9_FRAME_COUNT 0x20
57 #define ASP_RX_CTRL_FB_10_FRAME_COUNT 0x24
58 #define ASP_RX_CTRL_FB_OUT_FRAME_COUNT 0x28
59 #define ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT 0x2c
60 #define ASP_RX_CTRL_FLUSH 0x30
61 #define ASP_CTRL_UMAC0_FLUSH_MASK (BIT(0) | BIT(12))
62 #define ASP_CTRL_UMAC1_FLUSH_MASK (BIT(1) | BIT(13))
63 #define ASP_CTRL_SPB_FLUSH_MASK (BIT(8) | BIT(20))
64 #define ASP_RX_CTRL_FB_RX_FIFO_DEPTH 0x38
65
66 #define ASP_RX_FILTER_OFFSET 0x80000
67 #define ASP_RX_FILTER_BLK_CTRL 0x0
68 #define ASP_RX_FILTER_OPUT_EN BIT(0)
69 #define ASP_RX_FILTER_MDA_EN BIT(1)
70 #define ASP_RX_FILTER_LNR_MD BIT(2)
71 #define ASP_RX_FILTER_GEN_WK_EN BIT(3)
72 #define ASP_RX_FILTER_GEN_WK_CLR BIT(4)
73 #define ASP_RX_FILTER_NT_FLT_EN BIT(5)
74 #define ASP_RX_FILTER_MDA_CFG(sel) (((sel) * 0x14) + 0x100)
75 #define ASP_RX_FILTER_MDA_CFG_EN_SHIFT 8
76 #define ASP_RX_FILTER_MDA_CFG_UMC_SEL(sel) ((sel) > 1 ? BIT(17) : \
77 BIT((sel) + 9))
78 #define ASP_RX_FILTER_MDA_PAT_H(sel) (((sel) * 0x14) + 0x104)
79 #define ASP_RX_FILTER_MDA_PAT_L(sel) (((sel) * 0x14) + 0x108)
80 #define ASP_RX_FILTER_MDA_MSK_H(sel) (((sel) * 0x14) + 0x10c)
81 #define ASP_RX_FILTER_MDA_MSK_L(sel) (((sel) * 0x14) + 0x110)
82 #define ASP_RX_FILTER_MDA_CFG(sel) (((sel) * 0x14) + 0x100)
83 #define ASP_RX_FILTER_MDA_PAT_H(sel) (((sel) * 0x14) + 0x104)
84 #define ASP_RX_FILTER_MDA_PAT_L(sel) (((sel) * 0x14) + 0x108)
85 #define ASP_RX_FILTER_MDA_MSK_H(sel) (((sel) * 0x14) + 0x10c)
86 #define ASP_RX_FILTER_MDA_MSK_L(sel) (((sel) * 0x14) + 0x110)
87 #define ASP_RX_FILTER_NET_CFG(sel) (((sel) * 0xa04) + 0x400)
88 #define ASP_RX_FILTER_NET_CFG_CH(sel) ((sel) << 0)
89 #define ASP_RX_FILTER_NET_CFG_EN BIT(9)
90 #define ASP_RX_FILTER_NET_CFG_L2_EN BIT(10)
91 #define ASP_RX_FILTER_NET_CFG_L3_EN BIT(11)
92 #define ASP_RX_FILTER_NET_CFG_L4_EN BIT(12)
93 #define ASP_RX_FILTER_NET_CFG_L3_FRM(sel) ((sel) << 13)
94 #define ASP_RX_FILTER_NET_CFG_L4_FRM(sel) ((sel) << 15)
95 #define ASP_RX_FILTER_NET_CFG_UMC(sel) BIT((sel) + 19)
96 #define ASP_RX_FILTER_NET_CFG_DMA_EN BIT(27)
97
98 #define ASP_RX_FILTER_NET_OFFSET_MAX 32
99 #define ASP_RX_FILTER_NET_PAT(sel, block, off) \
100 (((sel) * 0xa04) + ((block) * 0x200) + (off) + 0x600)
101 #define ASP_RX_FILTER_NET_MASK(sel, block, off) \
102 (((sel) * 0xa04) + ((block) * 0x200) + (off) + 0x700)
103
104 #define ASP_RX_FILTER_NET_OFFSET(sel) (((sel) * 0xa04) + 0xe00)
105 #define ASP_RX_FILTER_NET_OFFSET_L2(val) ((val) << 0)
106 #define ASP_RX_FILTER_NET_OFFSET_L3_0(val) ((val) << 8)
107 #define ASP_RX_FILTER_NET_OFFSET_L3_1(val) ((val) << 16)
108 #define ASP_RX_FILTER_NET_OFFSET_L4(val) ((val) << 24)
109
110 enum asp_rx_net_filter_block {
111 ASP_RX_FILTER_NET_L2 = 0,
112 ASP_RX_FILTER_NET_L3_0,
113 ASP_RX_FILTER_NET_L3_1,
114 ASP_RX_FILTER_NET_L4,
115 ASP_RX_FILTER_NET_BLOCK_MAX
116 };
117
118 #define ASP_EDPKT_OFFSET 0x9c000
119 #define ASP_EDPKT_ENABLE 0x4
120 #define ASP_EDPKT_ENABLE_EN BIT(0)
121 #define ASP_EDPKT_HDR_CFG 0xc
122 #define ASP_EDPKT_HDR_SZ_SHIFT 2
123 #define ASP_EDPKT_HDR_SZ_32 0
124 #define ASP_EDPKT_HDR_SZ_64 1
125 #define ASP_EDPKT_HDR_SZ_96 2
126 #define ASP_EDPKT_HDR_SZ_128 3
127 #define ASP_EDPKT_BURST_BUF_PSCAL_TOUT 0x10
128 #define ASP_EDPKT_BURST_BUF_WRITE_TOUT 0x14
129 #define ASP_EDPKT_BURST_BUF_READ_TOUT 0x18
130 #define ASP_EDPKT_RX_TS_COUNTER 0x38
131 #define ASP_EDPKT_ENDI 0x48
132 #define ASP_EDPKT_ENDI_DESC_SHIFT 8
133 #define ASP_EDPKT_ENDI_NO_BT_SWP 0
134 #define ASP_EDPKT_ENDI_BT_SWP_WD 1
135 #define ASP_EDPKT_RX_PKT_CNT 0x138
136 #define ASP_EDPKT_HDR_EXTR_CNT 0x13c
137 #define ASP_EDPKT_HDR_OUT_CNT 0x140
138 #define ASP_EDPKT_SPARE_REG 0x174
139 #define ASP_EDPKT_SPARE_REG_EPHY_LPI BIT(4)
140 #define ASP_EDPKT_SPARE_REG_GPHY_LPI BIT(3)
141
142 #define ASP_CTRL_OFFSET 0x101000
143 #define ASP_CTRL_ASP_SW_INIT 0x04
144 #define ASP_CTRL_ASP_SW_INIT_ACPUSS_CORE BIT(0)
145 #define ASP_CTRL_ASP_SW_INIT_ASP_TX BIT(1)
146 #define ASP_CTRL_ASP_SW_INIT_AS_RX BIT(2)
147 #define ASP_CTRL_ASP_SW_INIT_ASP_RGMII_UMAC0 BIT(3)
148 #define ASP_CTRL_ASP_SW_INIT_ASP_RGMII_UMAC1 BIT(4)
149 #define ASP_CTRL_ASP_SW_INIT_ASP_XMEMIF BIT(5)
150 #define ASP_CTRL_CLOCK_CTRL 0x04
151 #define ASP_CTRL_CLOCK_CTRL_ASP_TX_DISABLE BIT(0)
152 #define ASP_CTRL_CLOCK_CTRL_ASP_RX_DISABLE BIT(1)
153 #define ASP_CTRL_CLOCK_CTRL_ASP_RGMII_SHIFT 2
154 #define ASP_CTRL_CLOCK_CTRL_ASP_RGMII_MASK (0x7 << ASP_CTRL_CLOCK_CTRL_ASP_RGMII_SHIFT)
155 #define ASP_CTRL_CLOCK_CTRL_ASP_RGMII_DIS(x) BIT(ASP_CTRL_CLOCK_CTRL_ASP_RGMII_SHIFT + (x))
156 #define ASP_CTRL_CLOCK_CTRL_ASP_ALL_DISABLE GENMASK(4, 0)
157 #define ASP_CTRL_CORE_CLOCK_SELECT 0x08
158 #define ASP_CTRL_CORE_CLOCK_SELECT_MAIN BIT(0)
159 #define ASP_CTRL_SCRATCH_0 0x0c
160
161 struct bcmasp_tx_cb {
162 struct sk_buff *skb;
163 unsigned int bytes_sent;
164 bool last;
165
166 DEFINE_DMA_UNMAP_ADDR(dma_addr);
167 DEFINE_DMA_UNMAP_LEN(dma_len);
168 };
169
170 struct bcmasp_res {
171 /* Per interface resources */
172 /* Port */
173 void __iomem *umac;
174 void __iomem *umac2fb;
175 void __iomem *rgmii;
176
177 /* TX slowpath/configuration */
178 void __iomem *tx_spb_ctrl;
179 void __iomem *tx_spb_top;
180 void __iomem *tx_epkt_core;
181 void __iomem *tx_pause_ctrl;
182 };
183
184 #define DESC_ADDR(x) ((x) & GENMASK_ULL(39, 0))
185 #define DESC_FLAGS(x) ((x) & GENMASK_ULL(63, 40))
186
187 struct bcmasp_desc {
188 u64 buf;
189 #define DESC_CHKSUM BIT_ULL(40)
190 #define DESC_CRC_ERR BIT_ULL(41)
191 #define DESC_RX_SYM_ERR BIT_ULL(42)
192 #define DESC_NO_OCT_ALN BIT_ULL(43)
193 #define DESC_PKT_TRUC BIT_ULL(44)
194 /* 39:0 (TX/RX) bits 0-39 of buf addr
195 * 40 (RX) checksum
196 * 41 (RX) crc_error
197 * 42 (RX) rx_symbol_error
198 * 43 (RX) non_octet_aligned
199 * 44 (RX) pkt_truncated
200 * 45 Reserved
201 * 56:46 (RX) mac_filter_id
202 * 60:57 (RX) rx_port_num (0-unicmac0, 1-unimac1)
203 * 61 Reserved
204 * 63:62 (TX) forward CRC, overwrite CRC
205 */
206 u32 size;
207 u32 flags;
208 #define DESC_INT_EN BIT(0)
209 #define DESC_SOF BIT(1)
210 #define DESC_EOF BIT(2)
211 #define DESC_EPKT_CMD BIT(3)
212 #define DESC_SCRAM_ST BIT(8)
213 #define DESC_SCRAM_END BIT(9)
214 #define DESC_PCPP BIT(10)
215 #define DESC_PPPP BIT(11)
216 /* 0 (TX) tx_int_en
217 * 1 (TX/RX) SOF
218 * 2 (TX/RX) EOF
219 * 3 (TX) epkt_command
220 * 6:4 (TX) PA
221 * 7 (TX) pause at desc end
222 * 8 (TX) scram_start
223 * 9 (TX) scram_end
224 * 10 (TX) PCPP
225 * 11 (TX) PPPP
226 * 14:12 Reserved
227 * 15 (TX) pid ch Valid
228 * 19:16 (TX) data_pkt_type
229 * 32:20 (TX) pid_channel (RX) nw_filter_id
230 */
231 };
232
233 struct bcmasp_intf;
234
235 struct bcmasp_intf_stats64 {
236 /* Rx Stats */
237 u64_stats_t rx_packets;
238 u64_stats_t rx_bytes;
239 u64_stats_t rx_errors;
240 u64_stats_t rx_dropped;
241 u64_stats_t rx_crc_errs;
242 u64_stats_t rx_sym_errs;
243
244 /* Tx Stats*/
245 u64_stats_t tx_packets;
246 u64_stats_t tx_bytes;
247
248 struct u64_stats_sync syncp;
249 };
250
251 struct bcmasp_mib_counters {
252 u32 edpkt_ts;
253 u32 edpkt_rx_pkt_cnt;
254 u32 edpkt_hdr_ext_cnt;
255 u32 edpkt_hdr_out_cnt;
256 u32 umac_frm_cnt;
257 u32 fb_frm_cnt;
258 u32 fb_rx_fifo_depth;
259 u32 fb_out_frm_cnt;
260 u32 fb_filt_out_frm_cnt;
261 u32 alloc_rx_skb_failed;
262 u32 tx_dma_failed;
263 u32 mc_filters_full_cnt;
264 u32 uc_filters_full_cnt;
265 u32 filters_combine_cnt;
266 u32 promisc_filters_cnt;
267 u32 tx_realloc_offload_failed;
268 u32 tx_timeout_cnt;
269 };
270
271 struct bcmasp_intf_ops {
272 unsigned long (*rx_desc_read)(struct bcmasp_intf *intf);
273 void (*rx_buffer_write)(struct bcmasp_intf *intf, dma_addr_t addr);
274 void (*rx_desc_write)(struct bcmasp_intf *intf, dma_addr_t addr);
275 unsigned long (*tx_read)(struct bcmasp_intf *intf);
276 void (*tx_write)(struct bcmasp_intf *intf, dma_addr_t addr);
277 };
278
279 struct bcmasp_priv;
280
281 struct bcmasp_intf {
282 struct list_head list;
283 struct net_device *ndev;
284 struct bcmasp_priv *parent;
285
286 /* ASP Ch */
287 int channel;
288 int port;
289 const struct bcmasp_intf_ops *ops;
290
291 /* Used for splitting shared resources */
292 int index;
293
294 struct napi_struct tx_napi;
295 /* TX ring, starts on a new cacheline boundary */
296 void __iomem *tx_spb_dma;
297 int tx_spb_index;
298 int tx_spb_clean_index;
299 struct bcmasp_desc *tx_spb_cpu;
300 dma_addr_t tx_spb_dma_addr;
301 dma_addr_t tx_spb_dma_valid;
302 dma_addr_t tx_spb_dma_read;
303 struct bcmasp_tx_cb *tx_cbs;
304
305 /* RX ring, starts on a new cacheline boundary */
306 void __iomem *rx_edpkt_cfg;
307 void __iomem *rx_edpkt_dma;
308 int rx_edpkt_index;
309 int rx_buf_order;
310 struct bcmasp_desc *rx_edpkt_cpu;
311 dma_addr_t rx_edpkt_dma_addr;
312 dma_addr_t rx_edpkt_dma_read;
313 dma_addr_t rx_edpkt_dma_valid;
314
315 /* RX buffer prefetcher ring*/
316 void *rx_ring_cpu;
317 dma_addr_t rx_ring_dma;
318 dma_addr_t rx_ring_dma_valid;
319 struct napi_struct rx_napi;
320
321 struct bcmasp_res res;
322 unsigned int crc_fwd;
323
324 /* PHY device */
325 struct device_node *phy_dn;
326 struct device_node *ndev_dn;
327 phy_interface_t phy_interface;
328 bool internal_phy;
329 int old_pause;
330 int old_link;
331 int old_duplex;
332
333 u32 msg_enable;
334
335 /* Statistics */
336 struct bcmasp_intf_stats64 stats64;
337 struct bcmasp_mib_counters mib;
338
339 u32 wolopts;
340 u8 sopass[SOPASS_MAX];
341 };
342
343 #define NUM_NET_FILTERS 32
344 struct bcmasp_net_filter {
345 struct ethtool_rx_flow_spec fs;
346
347 bool claimed;
348 bool wake_filter;
349
350 int port;
351 int ch;
352 unsigned int hw_index;
353 };
354
355 #define NUM_MDA_FILTERS 32
356 struct bcmasp_mda_filter {
357 /* Current owner of this filter */
358 int port;
359 bool en;
360 u8 addr[ETH_ALEN];
361 u8 mask[ETH_ALEN];
362 };
363
364 struct bcmasp_plat_data {
365 void (*core_clock_select)(struct bcmasp_priv *priv, bool slow);
366 void (*eee_fixup)(struct bcmasp_intf *priv, bool en);
367 unsigned int num_mda_filters;
368 unsigned int num_net_filters;
369 unsigned int tx_chan_offset;
370 unsigned int rx_ctrl_offset;
371 };
372
373 struct bcmasp_priv {
374 struct platform_device *pdev;
375 struct clk *clk;
376
377 int irq;
378 u32 irq_mask;
379
380 /* Used if shared wol irq */
381 struct mutex wol_lock;
382 int wol_irq;
383 unsigned long wol_irq_enabled_mask;
384
385 void (*core_clock_select)(struct bcmasp_priv *priv, bool slow);
386 void (*eee_fixup)(struct bcmasp_intf *intf, bool en);
387 unsigned int num_mda_filters;
388 unsigned int num_net_filters;
389 unsigned int tx_chan_offset;
390 unsigned int rx_ctrl_offset;
391
392 void __iomem *base;
393
394 struct list_head intfs;
395
396 struct bcmasp_mda_filter *mda_filters;
397
398 /* MAC destination address filters lock */
399 spinlock_t mda_lock;
400
401 /* Protects accesses to ASP_CTRL_CLOCK_CTRL */
402 spinlock_t clk_lock;
403
404 struct bcmasp_net_filter *net_filters;
405
406 /* Network filter lock */
407 struct mutex net_lock;
408 };
409
bcmasp_intf_rx_desc_read(struct bcmasp_intf * intf)410 static inline unsigned long bcmasp_intf_rx_desc_read(struct bcmasp_intf *intf)
411 {
412 return intf->ops->rx_desc_read(intf);
413 }
414
bcmasp_intf_rx_buffer_write(struct bcmasp_intf * intf,dma_addr_t addr)415 static inline void bcmasp_intf_rx_buffer_write(struct bcmasp_intf *intf,
416 dma_addr_t addr)
417 {
418 intf->ops->rx_buffer_write(intf, addr);
419 }
420
bcmasp_intf_rx_desc_write(struct bcmasp_intf * intf,dma_addr_t addr)421 static inline void bcmasp_intf_rx_desc_write(struct bcmasp_intf *intf,
422 dma_addr_t addr)
423 {
424 intf->ops->rx_desc_write(intf, addr);
425 }
426
bcmasp_intf_tx_read(struct bcmasp_intf * intf)427 static inline unsigned long bcmasp_intf_tx_read(struct bcmasp_intf *intf)
428 {
429 return intf->ops->tx_read(intf);
430 }
431
bcmasp_intf_tx_write(struct bcmasp_intf * intf,dma_addr_t addr)432 static inline void bcmasp_intf_tx_write(struct bcmasp_intf *intf,
433 dma_addr_t addr)
434 {
435 intf->ops->tx_write(intf, addr);
436 }
437
438 #define __BCMASP_IO_MACRO(name, m) \
439 static inline u32 name##_rl(struct bcmasp_intf *intf, u32 off) \
440 { \
441 u32 reg = readl_relaxed(intf->m + off); \
442 return reg; \
443 } \
444 static inline void name##_wl(struct bcmasp_intf *intf, u32 val, u32 off)\
445 { \
446 writel_relaxed(val, intf->m + off); \
447 }
448
449 #define BCMASP_IO_MACRO(name) __BCMASP_IO_MACRO(name, res.name)
450 #define BCMASP_FP_IO_MACRO(name) __BCMASP_IO_MACRO(name, name)
451
452 BCMASP_IO_MACRO(umac);
453 BCMASP_IO_MACRO(umac2fb);
454 BCMASP_IO_MACRO(rgmii);
455 BCMASP_FP_IO_MACRO(tx_spb_dma);
456 BCMASP_IO_MACRO(tx_spb_ctrl);
457 BCMASP_IO_MACRO(tx_spb_top);
458 BCMASP_IO_MACRO(tx_epkt_core);
459 BCMASP_IO_MACRO(tx_pause_ctrl);
460 BCMASP_FP_IO_MACRO(rx_edpkt_dma);
461 BCMASP_FP_IO_MACRO(rx_edpkt_cfg);
462
463 #define __BCMASP_FP_IO_MACRO_Q(name, m) \
464 static inline u64 name##_rq(struct bcmasp_intf *intf, u32 off) \
465 { \
466 u64 reg = readq_relaxed(intf->m + off); \
467 return reg; \
468 } \
469 static inline void name##_wq(struct bcmasp_intf *intf, u64 val, u32 off)\
470 { \
471 writeq_relaxed(val, intf->m + off); \
472 }
473
474 #define BCMASP_FP_IO_MACRO_Q(name) __BCMASP_FP_IO_MACRO_Q(name, name)
475
476 BCMASP_FP_IO_MACRO_Q(tx_spb_dma);
477 BCMASP_FP_IO_MACRO_Q(rx_edpkt_dma);
478 BCMASP_FP_IO_MACRO_Q(rx_edpkt_cfg);
479
480 #define PKT_OFFLOAD_NOP (0 << 28)
481 #define PKT_OFFLOAD_HDR_OP (1 << 28)
482 #define PKT_OFFLOAD_HDR_WRBACK BIT(19)
483 #define PKT_OFFLOAD_HDR_COUNT(x) ((x) << 16)
484 #define PKT_OFFLOAD_HDR_SIZE_1(x) ((x) << 4)
485 #define PKT_OFFLOAD_HDR_SIZE_2(x) (x)
486 #define PKT_OFFLOAD_HDR2_SIZE_2(x) ((x) << 24)
487 #define PKT_OFFLOAD_HDR2_SIZE_3(x) ((x) << 12)
488 #define PKT_OFFLOAD_HDR2_SIZE_4(x) (x)
489 #define PKT_OFFLOAD_EPKT_OP (2 << 28)
490 #define PKT_OFFLOAD_EPKT_WRBACK BIT(23)
491 #define PKT_OFFLOAD_EPKT_IP(x) ((x) << 21)
492 #define PKT_OFFLOAD_EPKT_TP(x) ((x) << 19)
493 #define PKT_OFFLOAD_EPKT_LEN(x) ((x) << 16)
494 #define PKT_OFFLOAD_EPKT_CSUM_L4 BIT(15)
495 #define PKT_OFFLOAD_EPKT_CSUM_L3 BIT(14)
496 #define PKT_OFFLOAD_EPKT_ID(x) ((x) << 12)
497 #define PKT_OFFLOAD_EPKT_SEQ(x) ((x) << 10)
498 #define PKT_OFFLOAD_EPKT_TS(x) ((x) << 8)
499 #define PKT_OFFLOAD_EPKT_BLOC(x) (x)
500 #define PKT_OFFLOAD_END_OP (7 << 28)
501
502 struct bcmasp_pkt_offload {
503 __be32 nop;
504 __be32 header;
505 __be32 header2;
506 __be32 epkt;
507 __be32 end;
508 };
509
510 #define BCMASP_CORE_IO_MACRO(name, offset) \
511 static inline u32 name##_core_rl(struct bcmasp_priv *priv, \
512 u32 off) \
513 { \
514 u32 reg = readl_relaxed(priv->base + (offset) + off); \
515 return reg; \
516 } \
517 static inline void name##_core_wl(struct bcmasp_priv *priv, \
518 u32 val, u32 off) \
519 { \
520 writel_relaxed(val, priv->base + (offset) + off); \
521 }
522
523 BCMASP_CORE_IO_MACRO(intr2, ASP_INTR2_OFFSET);
524 BCMASP_CORE_IO_MACRO(wakeup_intr2, ASP_WAKEUP_INTR2_OFFSET);
525 BCMASP_CORE_IO_MACRO(tx_analytics, ASP_TX_ANALYTICS_OFFSET);
526 BCMASP_CORE_IO_MACRO(rx_analytics, ASP_RX_ANALYTICS_OFFSET);
527 BCMASP_CORE_IO_MACRO(rx_filter, ASP_RX_FILTER_OFFSET);
528 BCMASP_CORE_IO_MACRO(rx_edpkt, ASP_EDPKT_OFFSET);
529 BCMASP_CORE_IO_MACRO(ctrl, ASP_CTRL_OFFSET);
530 BCMASP_CORE_IO_MACRO(ctrl2, ASP_CTRL2_OFFSET);
531
532 #define BCMASP_CORE_IO_MACRO_OFFSET(name, offset) \
533 static inline u32 name##_core_rl(struct bcmasp_priv *priv, \
534 u32 off) \
535 { \
536 u32 reg = readl_relaxed(priv->base + priv->name##_offset + \
537 (offset) + off); \
538 return reg; \
539 } \
540 static inline void name##_core_wl(struct bcmasp_priv *priv, \
541 u32 val, u32 off) \
542 { \
543 writel_relaxed(val, priv->base + priv->name##_offset + \
544 (offset) + off); \
545 }
546 BCMASP_CORE_IO_MACRO_OFFSET(rx_ctrl, ASP_RX_CTRL_OFFSET);
547
548 struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv,
549 struct device_node *ndev_dn, int i);
550
551 void bcmasp_interface_destroy(struct bcmasp_intf *intf);
552
553 void bcmasp_enable_tx_irq(struct bcmasp_intf *intf, int en);
554
555 void bcmasp_enable_rx_irq(struct bcmasp_intf *intf, int en);
556
557 void bcmasp_enable_phy_irq(struct bcmasp_intf *intf, int en);
558
559 void bcmasp_flush_rx_port(struct bcmasp_intf *intf);
560
561 extern const struct ethtool_ops bcmasp_ethtool_ops;
562
563 int bcmasp_interface_suspend(struct bcmasp_intf *intf);
564
565 int bcmasp_interface_resume(struct bcmasp_intf *intf);
566
567 void bcmasp_set_promisc(struct bcmasp_intf *intf, bool en);
568
569 void bcmasp_set_allmulti(struct bcmasp_intf *intf, bool en);
570
571 void bcmasp_set_broad(struct bcmasp_intf *intf, bool en);
572
573 void bcmasp_set_oaddr(struct bcmasp_intf *intf, const unsigned char *addr,
574 bool en);
575
576 int bcmasp_set_en_mda_filter(struct bcmasp_intf *intf, unsigned char *addr,
577 unsigned char *mask);
578
579 void bcmasp_disable_all_filters(struct bcmasp_intf *intf);
580
581 void bcmasp_core_clock_set_intf(struct bcmasp_intf *intf, bool en);
582
583 struct bcmasp_net_filter *bcmasp_netfilt_get_init(struct bcmasp_intf *intf,
584 u32 loc, bool wake_filter,
585 bool init);
586
587 bool bcmasp_netfilt_check_dup(struct bcmasp_intf *intf,
588 struct ethtool_rx_flow_spec *fs);
589
590 void bcmasp_netfilt_release(struct bcmasp_intf *intf,
591 struct bcmasp_net_filter *nfilt);
592
593 int bcmasp_netfilt_get_active(struct bcmasp_intf *intf);
594
595 int bcmasp_netfilt_get_all_active(struct bcmasp_intf *intf, u32 *rule_locs,
596 u32 *rule_cnt);
597
598 void bcmasp_netfilt_suspend(struct bcmasp_intf *intf);
599
600 void bcmasp_enable_wol(struct bcmasp_intf *intf, bool en);
601 #endif
602