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Searched refs:fb_div (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pll.c87 unsigned int *fb_div, unsigned int *ref_div) in amdgpu_pll_get_fb_ref_div() argument
98 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in amdgpu_pll_get_fb_ref_div()
101 if (*fb_div > fb_div_max) { in amdgpu_pll_get_fb_ref_div()
102 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); in amdgpu_pll_get_fb_ref_div()
103 *fb_div = fb_div_max; in amdgpu_pll_get_fb_ref_div()
134 unsigned fb_div_min, fb_div_max, fb_div; in amdgpu_pll_compute() local
211 ref_div_max, &fb_div, &ref_div); in amdgpu_pll_compute()
212 diff = abs(target_clock - (pll->reference_freq * fb_div) / in amdgpu_pll_compute()
226 &fb_div, &ref_div); in amdgpu_pll_compute()
230 amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); in amdgpu_pll_compute()
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H A Datombios_crtc.c582 u32 fb_div, in amdgpu_atombios_crtc_program_pll() argument
609 args.v1.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
619 args.v2.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
629 args.v3.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
646 args.v5.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
676 args.v6.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
825 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local
854 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll()
861 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
867 u32 amount = (((fb_div * 10) + frac_fb_div) * in amdgpu_atombios_crtc_set_pll()
H A Datombios_crtc.h49 u32 fb_div,
/linux/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c43 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
45 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_engine_clock()
46 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; in radeon_legacy_get_engine_clock()
47 fb_div <<= 1; in radeon_legacy_get_engine_clock()
48 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
56 sclk = fb_div / ref_div; in radeon_legacy_get_engine_clock()
73 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
75 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_memory_clock()
76 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK; in radeon_legacy_get_memory_clock()
77 fb_div <<= 1; in radeon_legacy_get_memory_clock()
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H A Dradeon_display.c936 unsigned *fb_div, unsigned *ref_div) in avivo_get_fb_ref_div() argument
943 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in avivo_get_fb_ref_div()
946 if (*fb_div > fb_div_max) { in avivo_get_fb_ref_div()
947 *ref_div = (*ref_div * fb_div_max)/(*fb_div); in avivo_get_fb_ref_div()
948 *fb_div = fb_div_max; in avivo_get_fb_ref_div()
977 unsigned fb_div_min, fb_div_max, fb_div; in radeon_compute_pll_avivo() local
1057 ref_div_max, &fb_div, &ref_div); in radeon_compute_pll_avivo()
1058 diff = abs(target_clock - (pll->reference_freq * fb_div) / in radeon_compute_pll_avivo()
1072 &fb_div, &ref_div); in radeon_compute_pll_avivo()
1076 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); in radeon_compute_pll_avivo()
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H A Drs780_dpm.c88 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
405 static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div) in rs780_force_fbdiv() argument
414 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div), in rs780_force_fbdiv()
416 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div), in rs780_force_fbdiv()
459 rs780_force_fbdiv(rdev, max_dividers.fb_div); in rs780_set_engine_clock_scaling()
461 if (max_dividers.fb_div > min_dividers.fb_div) { in rs780_set_engine_clock_scaling()
463 MIN_FEEDBACK_DIV(min_dividers.fb_div) | in rs780_set_engine_clock_scaling()
464 MAX_FEEDBACK_DIV(max_dividers.fb_div), in rs780_set_engine_clock_scaling()
1047 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1054 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
H A Drv730_dpm.c157 mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div); in rv730_populate_mclk_value()
171 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000); in rv730_populate_mclk_value()
H A Drv770.c56 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local
76 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks()
80 fb_div |= 1; in rv770_set_uvd_clocks()
110 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks()
H A Dni_dpm.c2096 u32 fb_div; in ni_init_smc_spll_table() local
2117 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in ni_init_smc_spll_table()
2121 fb_div &= ~0x00001FFF; in ni_init_smc_spll_table()
2122 fb_div >>= 1; in ni_init_smc_spll_table()
2131 if (fb_div & ~(SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) in ni_init_smc_spll_table()
2140 …tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in ni_init_smc_spll_table()
H A Dr600.c205 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local
234 &fb_div, &vclk_div, &dclk_div); in r600_set_uvd_clocks()
239 fb_div >>= 1; in r600_set_uvd_clocks()
241 fb_div |= 1; in r600_set_uvd_clocks()
257 UPLL_FB_DIV(fb_div) | in r600_set_uvd_clocks()
H A Dsi_dpm.c2787 u32 fb_div, p_div; in si_init_smc_spll_table() local
2807 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in si_init_smc_spll_table()
2811 fb_div &= ~0x00001FFF; in si_init_smc_spll_table()
2812 fb_div >>= 1; in si_init_smc_spll_table()
2817 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) in si_init_smc_spll_table()
2827 …tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in si_init_smc_spll_table()
H A Drv6xx_dpm.c529 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
607 rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div); in rv6xx_program_mclk_stepping_entry()
H A Dradeon_atombios.c2850 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2864 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); in radeon_atom_get_clock_dividers()
2871 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; in radeon_atom_get_clock_dividers()
H A Dci_dpm.c3137 fbdiv = dividers.fb_div & 0x3FFFFFF; in ci_calculate_sclk_params()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c654 struct fixed31_32 fb_div; in calculate_ss() local
674 fb_div = dc_fixpt_from_fraction( in calculate_ss()
676 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); in calculate_ss()
682 fb_div, dc_fixpt_from_fraction(ss_data->percentage, in calculate_ss()
/linux/drivers/video/fbdev/aty/
H A Dradeon_base.c1539 int fb_div, pll_output_freq = 0; in radeon_calc_pll_regs() local
1628 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, in radeon_calc_pll_regs()
1631 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); in radeon_calc_pll_regs()
1634 pr_debug("fb_div = 0x%x\n", fb_div); in radeon_calc_pll_regs()
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_dpm.c2957 u32 fb_div, p_div; in si_init_smc_spll_table() local
2976 …fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK) >> CG_SPLL_FUN… in si_init_smc_spll_table()
2980 fb_div &= ~0x00001FFF; in si_init_smc_spll_table()
2981 fb_div >>= 1; in si_init_smc_spll_table()
2986 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) in si_init_smc_spll_table()
2996 …tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in si_init_smc_spll_table()