1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML2_INTERNAL_SHARED_TYPES_H__ 6 #define __DML2_INTERNAL_SHARED_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 #include "dml_top_types.h" 10 #include "dml2_core_shared_types.h" 11 /* 12 * DML2 MCG Types and Interfaces 13 */ 14 15 #define DML_MCG_MAX_CLK_TABLE_SIZE 20 16 17 struct dram_bw_to_min_clk_table_entry { 18 unsigned long long pre_derate_dram_bw_kbps; 19 unsigned long min_uclk_khz; 20 unsigned long min_fclk_khz; 21 unsigned long min_dcfclk_khz; 22 }; 23 24 struct dml2_mcg_dram_bw_to_min_clk_table { 25 struct dram_bw_to_min_clk_table_entry entries[DML_MCG_MAX_CLK_TABLE_SIZE]; 26 27 unsigned int num_entries; 28 }; 29 30 struct dml2_mcg_min_clock_table { 31 struct { 32 unsigned int dispclk; 33 unsigned int dppclk; 34 unsigned int dscclk; 35 unsigned int dtbclk; 36 unsigned int phyclk; 37 unsigned int fclk; 38 unsigned int dcfclk; 39 } max_clocks_khz; 40 41 struct { 42 unsigned int dispclk; 43 unsigned int dppclk; 44 unsigned int dtbclk; 45 } max_ss_clocks_khz; 46 47 struct { 48 unsigned int dprefclk; 49 unsigned int xtalclk; 50 unsigned int pcierefclk; 51 unsigned int dchubrefclk; 52 unsigned int amclk; 53 } fixed_clocks_khz; 54 55 struct dml2_mcg_dram_bw_to_min_clk_table dram_bw_table; 56 }; 57 58 struct dml2_mcg_build_min_clock_table_params_in_out { 59 /* 60 * Input 61 */ 62 struct dml2_soc_bb *soc_bb; 63 struct { 64 bool perform_pseudo_build; 65 } clean_me_up; 66 67 /* 68 * Output 69 */ 70 struct dml2_mcg_min_clock_table *min_clk_table; 71 }; 72 struct dml2_mcg_instance { 73 bool (*build_min_clock_table)(struct dml2_mcg_build_min_clock_table_params_in_out *in_out); 74 }; 75 76 /* 77 * DML2 DPMM Types and Interfaces 78 */ 79 80 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out { 81 /* 82 * Input 83 */ 84 struct dml2_core_ip_params *ip; 85 struct dml2_soc_bb *soc_bb; 86 struct dml2_mcg_min_clock_table *min_clk_table; 87 const struct display_configuation_with_meta *display_cfg; 88 struct { 89 bool perform_pseudo_map; 90 struct dml2_core_internal_soc_bb *soc_bb; 91 } clean_me_up; 92 93 /* 94 * Output 95 */ 96 struct dml2_display_cfg_programming *programming; 97 }; 98 99 struct dml2_dpmm_map_watermarks_params_in_out { 100 /* 101 * Input 102 */ 103 const struct display_configuation_with_meta *display_cfg; 104 const struct dml2_core_instance *core; 105 106 /* 107 * Output 108 */ 109 struct dml2_display_cfg_programming *programming; 110 }; 111 112 struct dml2_dpmm_scratch { 113 struct dml2_display_cfg_programming programming; 114 }; 115 116 struct dml2_dpmm_instance { 117 bool (*map_mode_to_soc_dpm)(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out *in_out); 118 bool (*map_watermarks)(struct dml2_dpmm_map_watermarks_params_in_out *in_out); 119 120 struct dml2_dpmm_scratch dpmm_scratch; 121 }; 122 123 /* 124 * DML2 Core Types and Interfaces 125 */ 126 127 struct dml2_core_initialize_in_out { 128 enum dml2_project_id project_id; 129 struct dml2_core_instance *instance; 130 struct dml2_soc_bb *soc_bb; 131 struct dml2_ip_capabilities *ip_caps; 132 133 struct dml2_mcg_min_clock_table *minimum_clock_table; 134 135 void *explicit_ip_bb; 136 unsigned int explicit_ip_bb_size; 137 138 // FIXME_STAGE2 can remove but dcn3 version still need this 139 struct { 140 struct soc_bounding_box_st *soc_bb; 141 struct soc_states_st *soc_states; 142 } legacy; 143 }; 144 145 struct core_bandwidth_requirements { 146 int urgent_bandwidth_kbytes_per_sec; 147 int average_bandwidth_kbytes_per_sec; 148 }; 149 150 struct core_plane_support_info { 151 int dpps_used; 152 int dram_change_latency_hiding_margin_in_active; 153 int active_latency_hiding_us; 154 int mall_svp_size_requirement_ways; 155 int nominal_vblank_pstate_latency_hiding_us; 156 int vactive_det_fill_delay_us[dml2_pstate_type_count]; 157 }; 158 159 struct core_stream_support_info { 160 unsigned int odms_used; 161 unsigned int num_odm_output_segments; // for odm split mode (e.g. a value of 2 for odm_mode_mso_1to2) 162 163 /* FAMS2 SubVP support info */ 164 unsigned int phantom_min_v_active; 165 unsigned int phantom_v_startup; 166 167 unsigned int phantom_v_active; 168 unsigned int phantom_v_total; 169 int vblank_reserved_time_us; 170 int num_dsc_slices; 171 bool dsc_enable; 172 }; 173 174 struct core_display_cfg_support_info { 175 bool is_supported; 176 177 struct core_stream_support_info stream_support_info[DML2_MAX_PLANES]; 178 struct core_plane_support_info plane_support_info[DML2_MAX_PLANES]; 179 180 struct { 181 struct dml2_core_internal_mode_support_info support_info; 182 } clean_me_up; 183 }; 184 185 struct dml2_core_mode_support_result { 186 struct { 187 struct { 188 unsigned long urgent_bw_sdp_kbps; 189 unsigned long average_bw_sdp_kbps; 190 unsigned long urgent_bw_dram_kbps; 191 unsigned long average_bw_dram_kbps; 192 unsigned long dcfclk_khz; 193 unsigned long fclk_khz; 194 } svp_prefetch; 195 196 struct { 197 unsigned long urgent_bw_sdp_kbps; 198 unsigned long average_bw_sdp_kbps; 199 unsigned long urgent_bw_dram_kbps; 200 unsigned long average_bw_dram_kbps; 201 unsigned long dcfclk_khz; 202 unsigned long fclk_khz; 203 } active; 204 205 unsigned int dispclk_khz; 206 unsigned int dpprefclk_khz; 207 unsigned int dtbrefclk_khz; 208 unsigned int dcfclk_deepsleep_khz; 209 unsigned int socclk_khz; 210 211 unsigned int uclk_pstate_supported; 212 unsigned int fclk_pstate_supported; 213 struct dml2_core_internal_watermarks watermarks; 214 } global; 215 216 struct { 217 unsigned int dscclk_khz; 218 unsigned int dtbclk_khz; 219 unsigned int phyclk_khz; 220 } per_stream[DML2_MAX_PLANES]; 221 222 struct { 223 unsigned int dppclk_khz; 224 unsigned int mall_svp_allocation_mblks; 225 unsigned int mall_full_frame_allocation_mblks; 226 } per_plane[DML2_MAX_PLANES]; 227 228 struct core_display_cfg_support_info cfg_support_info; 229 }; 230 231 struct dml2_optimization_stage1_state { 232 bool performed; 233 bool success; 234 235 int min_clk_index_for_latency; 236 }; 237 238 struct dml2_optimization_stage2_state { 239 bool performed; 240 bool success; 241 242 // Whether or not each plane supports mcache 243 // The number of valid elements == display_cfg.num_planes 244 // The indexing of pstate_switch_modes matches plane_descriptors[] 245 bool per_plane_mcache_support[DML2_MAX_PLANES]; 246 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 247 }; 248 249 #define DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS 8 250 #define DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE 10 251 #define DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE 3 252 253 struct dml2_implicit_svp_meta { 254 bool valid; 255 unsigned long v_active; 256 unsigned long v_total; 257 unsigned long v_front_porch; 258 }; 259 260 struct dml2_pstate_per_method_common_meta { 261 /* generic params */ 262 int allow_start_otg_vline; 263 int allow_end_otg_vline; 264 /* scheduling params */ 265 double allow_time_us; 266 double disallow_time_us; 267 double period_us; 268 }; 269 270 struct dml2_pstate_meta { 271 bool valid; 272 double otg_vline_time_us; 273 int scheduling_delay_otg_vlines; 274 int vertical_interrupt_ack_delay_otg_vlines; 275 int allow_to_target_delay_otg_vlines; 276 int contention_delay_otg_vlines; 277 int min_allow_width_otg_vlines; 278 int nom_vtotal; 279 int vblank_start; 280 double nom_refresh_rate_hz; 281 double nom_frame_time_us; 282 int max_vtotal; 283 double min_refresh_rate_hz; 284 double max_frame_time_us; 285 int blackout_otg_vlines; 286 int max_allow_delay_otg_vlines; 287 double nom_vblank_time_us; 288 struct { 289 double max_vactive_det_fill_delay_us; 290 double vactive_latency_hiding_us; 291 double reserved_vblank_required_us; 292 int max_vactive_det_fill_delay_otg_vlines; 293 int reserved_blank_required_vlines; 294 struct dml2_pstate_per_method_common_meta common; 295 } method_vactive; 296 struct { 297 struct dml2_pstate_per_method_common_meta common; 298 } method_vblank; 299 struct { 300 int programming_delay_otg_vlines; 301 int df_throttle_delay_otg_vlines; 302 int prefetch_to_mall_delay_otg_vlines; 303 unsigned long phantom_vactive; 304 unsigned long phantom_vfp; 305 unsigned long phantom_vtotal; 306 struct dml2_pstate_per_method_common_meta common; 307 } method_subvp; 308 struct { 309 int programming_delay_otg_vlines; 310 int stretched_vtotal; 311 struct dml2_pstate_per_method_common_meta common; 312 } method_drr; 313 }; 314 315 /* mask of synchronized timings by stream index */ 316 struct dml2_pmo_synchronized_timing_groups { 317 unsigned int num_timing_groups; 318 unsigned int synchronized_timing_group_masks[DML2_MAX_PLANES]; 319 bool group_is_drr_enabled[DML2_MAX_PLANES]; 320 bool group_is_drr_active[DML2_MAX_PLANES]; 321 double group_line_time_us[DML2_MAX_PLANES]; 322 }; 323 324 struct dml2_optimization_stage3_state { 325 bool performed; 326 bool success; 327 328 // The pstate support mode for each plane 329 // The number of valid elements == display_cfg.num_planes 330 // The indexing of pstate_switch_modes matches plane_descriptors[] 331 enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES]; 332 333 // Meta-data for implicit SVP generation, indexed by stream index 334 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; 335 336 // Meta-data for FAMS2 337 bool fams2_required; 338 struct dml2_pstate_meta stream_pstate_meta[DML2_MAX_PLANES]; 339 340 int min_clk_index_for_latency; 341 }; 342 343 struct dml2_optimization_stage4_state { 344 bool performed; 345 bool success; 346 bool unoptimizable_streams[DML2_MAX_DCN_PIPES]; 347 }; 348 349 struct dml2_optimization_stage5_state { 350 bool performed; 351 bool success; 352 353 bool optimal_reserved_time_in_vblank_us; 354 bool vblank_includes_z8_optimization; 355 }; 356 357 struct display_configuation_with_meta { 358 struct dml2_display_cfg display_config; 359 360 struct dml2_core_mode_support_result mode_support_result; 361 362 // Stage 1 = Min Clocks for Latency 363 struct dml2_optimization_stage1_state stage1; 364 365 // Stage 2 = MCache 366 struct dml2_optimization_stage2_state stage2; 367 368 // Stage 3 = UCLK PState 369 struct dml2_optimization_stage3_state stage3; 370 371 // Stage 4 = Vmin 372 struct dml2_optimization_stage4_state stage4; 373 374 // Stage 5 = Stutter 375 struct dml2_optimization_stage5_state stage5; 376 }; 377 378 struct dml2_pmo_pstate_strategy { 379 enum dml2_pstate_method per_stream_pstate_method[DML2_MAX_PLANES]; 380 bool allow_state_increase; 381 }; 382 struct dml2_core_mode_support_in_out { 383 /* 384 * Inputs 385 */ 386 struct dml2_core_instance *instance; 387 const struct display_configuation_with_meta *display_cfg; 388 389 struct dml2_mcg_min_clock_table *min_clk_table; 390 int min_clk_index; 391 /* 392 * Outputs 393 */ 394 struct dml2_core_mode_support_result mode_support_result; 395 396 struct { 397 // Inputs 398 struct dml_display_cfg_st *display_cfg; 399 400 // Outputs 401 struct dml_mode_support_info_st *support_info; 402 unsigned int out_lowest_state_idx; 403 unsigned int min_fclk_khz; 404 unsigned int min_dcfclk_khz; 405 unsigned int min_dram_speed_mts; 406 unsigned int min_socclk_khz; 407 unsigned int min_dscclk_khz; 408 unsigned int min_dtbclk_khz; 409 unsigned int min_phyclk_khz; 410 } legacy; 411 }; 412 413 struct dml2_core_mode_programming_in_out { 414 /* 415 * Inputs 416 */ 417 struct dml2_core_instance *instance; 418 const struct display_configuation_with_meta *display_cfg; 419 const struct core_display_cfg_support_info *cfg_support_info; 420 /* 421 * Outputs (also Input the clk freq are also from programming struct) 422 */ 423 struct dml2_display_cfg_programming *programming; 424 425 }; 426 427 struct dml2_core_populate_informative_in_out { 428 /* 429 * Inputs 430 */ 431 struct dml2_core_instance *instance; 432 433 // If this is set, then the mode was supported, and mode programming 434 // was successfully run. 435 // Otherwise, mode programming was not run, because mode support failed. 436 bool mode_is_supported; 437 438 /* 439 * Outputs 440 */ 441 struct dml2_display_cfg_programming *programming; 442 }; 443 444 struct dml2_calculate_mcache_allocation_in_out { 445 /* 446 * Inputs 447 */ 448 struct dml2_core_instance *instance; 449 const struct dml2_plane_parameters *plane_descriptor; 450 unsigned int plane_index; 451 452 /* 453 * Outputs 454 */ 455 struct dml2_mcache_surface_allocation *mcache_allocation; 456 }; 457 458 struct dml2_core_internal_state_inputs { 459 unsigned int dummy; 460 }; 461 462 struct dml2_core_internal_state_intermediates { 463 unsigned int dummy; 464 }; 465 466 struct dml2_core_mode_support_locals { 467 union { 468 struct dml2_core_calcs_mode_support_ex mode_support_ex_params; 469 }; 470 struct dml2_display_cfg svp_expanded_display_cfg; 471 struct dml2_calculate_mcache_allocation_in_out calc_mcache_allocation_params; 472 }; 473 474 struct dml2_core_mode_programming_locals { 475 union { 476 struct dml2_core_calcs_mode_programming_ex mode_programming_ex_params; 477 }; 478 struct dml2_display_cfg svp_expanded_display_cfg; 479 }; 480 481 struct dml2_core_scratch { 482 struct dml2_core_mode_support_locals mode_support_locals; 483 struct dml2_core_mode_programming_locals mode_programming_locals; 484 int main_stream_index_from_svp_stream_index[DML2_MAX_PLANES]; 485 int svp_stream_index_from_main_stream_index[DML2_MAX_PLANES]; 486 int main_plane_index_to_phantom_plane_index[DML2_MAX_PLANES]; 487 int phantom_plane_index_to_main_plane_index[DML2_MAX_PLANES]; 488 }; 489 490 struct dml2_core_instance { 491 enum dml2_project_id project_id; 492 struct dml2_mcg_min_clock_table *minimum_clock_table; 493 struct dml2_core_internal_state_inputs inputs; 494 struct dml2_core_internal_state_intermediates intermediates; 495 496 struct dml2_core_scratch scratch; 497 498 bool (*initialize)(struct dml2_core_initialize_in_out *in_out); 499 bool (*mode_support)(struct dml2_core_mode_support_in_out *in_out); 500 bool (*mode_programming)(struct dml2_core_mode_programming_in_out *in_out); 501 bool (*populate_informative)(struct dml2_core_populate_informative_in_out *in_out); 502 bool (*calculate_mcache_allocation)(struct dml2_calculate_mcache_allocation_in_out *in_out); 503 504 struct { 505 struct dml2_core_internal_display_mode_lib mode_lib; 506 } clean_me_up; 507 }; 508 509 /* 510 * DML2 PMO Types and Interfaces 511 */ 512 513 struct dml2_pmo_initialize_in_out { 514 /* 515 * Input 516 */ 517 struct dml2_pmo_instance *instance; 518 struct dml2_soc_bb *soc_bb; 519 struct dml2_ip_capabilities *ip_caps; 520 struct dml2_pmo_options *options; 521 int mcg_clock_table_size; 522 }; 523 524 struct dml2_pmo_optimize_dcc_mcache_in_out { 525 /* 526 * Input 527 */ 528 struct dml2_pmo_instance *instance; 529 const struct dml2_display_cfg *display_config; 530 bool *dcc_mcache_supported; 531 struct core_display_cfg_support_info *cfg_support_info; 532 533 /* 534 * Output 535 */ 536 struct dml2_display_cfg *optimized_display_cfg; 537 }; 538 539 struct dml2_pmo_init_for_vmin_in_out { 540 /* 541 * Input 542 */ 543 struct dml2_pmo_instance *instance; 544 struct display_configuation_with_meta *base_display_config; 545 }; 546 547 struct dml2_pmo_test_for_vmin_in_out { 548 /* 549 * Input 550 */ 551 struct dml2_pmo_instance *instance; 552 const struct display_configuation_with_meta *display_config; 553 const struct dml2_soc_vmin_clock_limits *vmin_limits; 554 }; 555 556 struct dml2_pmo_optimize_for_vmin_in_out { 557 /* 558 * Input 559 */ 560 struct dml2_pmo_instance *instance; 561 struct display_configuation_with_meta *base_display_config; 562 563 /* 564 * Output 565 */ 566 struct display_configuation_with_meta *optimized_display_config; 567 }; 568 569 struct dml2_pmo_init_for_pstate_support_in_out { 570 /* 571 * Input 572 */ 573 struct dml2_pmo_instance *instance; 574 struct display_configuation_with_meta *base_display_config; 575 }; 576 577 struct dml2_pmo_test_for_pstate_support_in_out { 578 /* 579 * Input 580 */ 581 struct dml2_pmo_instance *instance; 582 struct display_configuation_with_meta *base_display_config; 583 }; 584 585 struct dml2_pmo_optimize_for_pstate_support_in_out { 586 /* 587 * Input 588 */ 589 struct dml2_pmo_instance *instance; 590 struct display_configuation_with_meta *base_display_config; 591 bool last_candidate_failed; 592 593 /* 594 * Output 595 */ 596 struct display_configuation_with_meta *optimized_display_config; 597 }; 598 599 struct dml2_pmo_init_for_stutter_in_out { 600 /* 601 * Input 602 */ 603 struct dml2_pmo_instance *instance; 604 struct display_configuation_with_meta *base_display_config; 605 }; 606 607 struct dml2_pmo_test_for_stutter_in_out { 608 /* 609 * Input 610 */ 611 struct dml2_pmo_instance *instance; 612 struct display_configuation_with_meta *base_display_config; 613 }; 614 615 struct dml2_pmo_optimize_for_stutter_in_out { 616 /* 617 * Input 618 */ 619 struct dml2_pmo_instance *instance; 620 struct display_configuation_with_meta *base_display_config; 621 bool last_candidate_failed; 622 623 /* 624 * Output 625 */ 626 struct display_configuation_with_meta *optimized_display_config; 627 }; 628 629 #define PMO_NO_DRR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw - dml2_pstate_method_na + 1)) - 1) << dml2_pstate_method_na) 630 #define PMO_DRR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_vactive_drr + 1)) - 1) << dml2_pstate_method_fw_vactive_drr) 631 #define PMO_DRR_CLAMPED_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_clamped - dml2_pstate_method_fw_vactive_drr + 1)) - 1) << dml2_pstate_method_fw_vactive_drr) 632 #define PMO_DRR_VAR_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_drr + 1)) - 1) << dml2_pstate_method_fw_drr) 633 #define PMO_FW_STRATEGY_MASK (((1 << (dml2_pstate_method_reserved_fw_drr_var - dml2_pstate_method_fw_svp + 1)) - 1) << dml2_pstate_method_fw_svp) 634 635 #define PMO_DCN4_MAX_DISPLAYS 4 636 #define PMO_DCN4_MAX_NUM_VARIANTS 2 637 #define PMO_DCN4_MAX_BASE_STRATEGIES 10 638 639 struct dml2_scheduling_check_locals { 640 struct dml2_pstate_per_method_common_meta group_common_pstate_meta[DML2_MAX_PLANES]; 641 unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES]; 642 unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES]; 643 }; 644 645 struct dml2_pmo_scratch { 646 union { 647 struct { 648 double reserved_time_candidates[DML2_MAX_PLANES][DML2_PMO_LEGACY_PREFETCH_MAX_TWAIT_OPTIONS]; 649 int reserved_time_candidates_count[DML2_MAX_PLANES]; 650 int current_candidate[DML2_MAX_PLANES]; 651 int min_latency_index; 652 int max_latency_index; 653 int cur_latency_index; 654 int stream_mask; 655 } pmo_dcn3; 656 struct { 657 struct dml2_pmo_pstate_strategy expanded_override_strategy_list[2 * 2 * 2 * 2]; 658 unsigned int num_expanded_override_strategies; 659 struct dml2_pmo_pstate_strategy pstate_strategy_candidates[DML2_PMO_PSTATE_CANDIDATE_LIST_SIZE]; 660 int num_pstate_candidates; 661 int cur_pstate_candidate; 662 663 unsigned int stream_plane_mask[DML2_MAX_PLANES]; 664 665 unsigned int stream_vactive_capability_mask; 666 667 int min_latency_index; 668 int max_latency_index; 669 int cur_latency_index; 670 671 // Stores all the implicit SVP meta information indexed by stream index of the display 672 // configuration under inspection, built at optimization stage init 673 struct dml2_implicit_svp_meta stream_svp_meta[DML2_MAX_PLANES]; 674 struct dml2_pstate_meta stream_pstate_meta[DML2_MAX_PLANES]; 675 676 unsigned int optimal_vblank_reserved_time_for_stutter_us[DML2_PMO_STUTTER_CANDIDATE_LIST_SIZE]; 677 unsigned int num_stutter_candidates; 678 unsigned int cur_stutter_candidate; 679 bool z8_vblank_optimizable; 680 681 /* mask of synchronized timings by stream index */ 682 unsigned int num_timing_groups; 683 unsigned int synchronized_timing_group_masks[DML2_MAX_PLANES]; 684 bool group_is_drr_enabled[DML2_MAX_PLANES]; 685 bool group_is_drr_active[DML2_MAX_PLANES]; 686 double group_line_time_us[DML2_MAX_PLANES]; 687 688 /* scheduling check locals */ 689 struct dml2_pstate_per_method_common_meta group_common_pstate_meta[DML2_MAX_PLANES]; 690 unsigned int sorted_group_gtl_disallow_index[DML2_MAX_PLANES]; 691 unsigned int sorted_group_gtl_period_index[DML2_MAX_PLANES]; 692 double group_phase_offset[DML2_MAX_PLANES]; 693 } pmo_dcn4; 694 }; 695 }; 696 697 struct dml2_pmo_init_data { 698 union { 699 struct { 700 /* populated once during initialization */ 701 struct dml2_pmo_pstate_strategy expanded_strategy_list_1_display[PMO_DCN4_MAX_BASE_STRATEGIES * 2]; 702 struct dml2_pmo_pstate_strategy expanded_strategy_list_2_display[PMO_DCN4_MAX_BASE_STRATEGIES * 4 * 4]; 703 struct dml2_pmo_pstate_strategy expanded_strategy_list_3_display[PMO_DCN4_MAX_BASE_STRATEGIES * 6 * 6 * 6]; 704 struct dml2_pmo_pstate_strategy expanded_strategy_list_4_display[PMO_DCN4_MAX_BASE_STRATEGIES * 8 * 8 * 8 * 8]; 705 unsigned int num_expanded_strategies_per_list[PMO_DCN4_MAX_DISPLAYS]; 706 } pmo_dcn4; 707 }; 708 }; 709 710 struct dml2_pmo_instance { 711 struct dml2_soc_bb *soc_bb; 712 struct dml2_ip_capabilities *ip_caps; 713 714 struct dml2_pmo_options *options; 715 716 int disp_clk_vmin_threshold; 717 int mpc_combine_limit; 718 int odm_combine_limit; 719 int mcg_clock_table_size; 720 union { 721 struct { 722 struct { 723 int prefetch_end_to_mall_start_us; 724 int fw_processing_delay_us; 725 int refresh_rate_limit_min; 726 int refresh_rate_limit_max; 727 } subvp; 728 } v1; 729 struct { 730 struct { 731 int refresh_rate_limit_min; 732 int refresh_rate_limit_max; 733 } subvp; 734 struct { 735 int refresh_rate_limit_min; 736 int refresh_rate_limit_max; 737 } drr; 738 } v2; 739 } fams_params; 740 741 bool (*initialize)(struct dml2_pmo_initialize_in_out *in_out); 742 bool (*optimize_dcc_mcache)(struct dml2_pmo_optimize_dcc_mcache_in_out *in_out); 743 744 bool (*init_for_vmin)(struct dml2_pmo_init_for_vmin_in_out *in_out); 745 bool (*test_for_vmin)(struct dml2_pmo_test_for_vmin_in_out *in_out); 746 bool (*optimize_for_vmin)(struct dml2_pmo_optimize_for_vmin_in_out *in_out); 747 748 bool (*init_for_uclk_pstate)(struct dml2_pmo_init_for_pstate_support_in_out *in_out); 749 bool (*test_for_uclk_pstate)(struct dml2_pmo_test_for_pstate_support_in_out *in_out); 750 bool (*optimize_for_uclk_pstate)(struct dml2_pmo_optimize_for_pstate_support_in_out *in_out); 751 752 bool (*init_for_stutter)(struct dml2_pmo_init_for_stutter_in_out *in_out); 753 bool (*test_for_stutter)(struct dml2_pmo_test_for_stutter_in_out *in_out); 754 bool (*optimize_for_stutter)(struct dml2_pmo_optimize_for_stutter_in_out *in_out); 755 756 struct dml2_pmo_init_data init_data; 757 struct dml2_pmo_scratch scratch; 758 }; 759 760 /* 761 * DML2 MCache Types 762 */ 763 764 struct top_mcache_validate_admissability_in_out { 765 struct dml2_instance *dml2_instance; 766 767 const struct dml2_display_cfg *display_cfg; 768 const struct core_display_cfg_support_info *cfg_support_info; 769 struct dml2_mcache_surface_allocation *mcache_allocations; 770 771 bool per_plane_status[DML2_MAX_PLANES]; 772 773 struct { 774 const struct dml_mode_support_info_st *mode_support_info; 775 } legacy; 776 }; 777 778 struct top_mcache_assign_ids_in_out { 779 /* 780 * Input 781 */ 782 const struct dml2_mcache_surface_allocation *mcache_allocations; 783 int plane_count; 784 785 int per_pipe_viewport_x_start[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 786 int per_pipe_viewport_x_end[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; 787 int pipe_count_per_plane[DML2_MAX_PLANES]; 788 789 struct dml2_display_mcache_regs *current_mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp 790 791 /* 792 * Output 793 */ 794 struct dml2_display_mcache_regs mcache_regs[DML2_MAX_PLANES][DML2_MAX_DCN_PIPES]; //One set per pipe/hubp 795 struct dml2_build_mcache_programming_in_out *mcache_programming; 796 }; 797 798 struct top_mcache_calc_mcache_count_and_offsets_in_out { 799 /* 800 * Inputs 801 */ 802 struct dml2_instance *dml2_instance; 803 const struct dml2_display_cfg *display_config; 804 805 /* 806 * Outputs 807 */ 808 struct dml2_mcache_surface_allocation *mcache_allocations; 809 }; 810 811 struct top_mcache_assign_global_mcache_ids_in_out { 812 /* 813 * Inputs/Outputs 814 */ 815 struct dml2_mcache_surface_allocation *allocations; 816 int num_allocations; 817 }; 818 819 /* 820 * DML2 Top Types 821 */ 822 823 struct dml2_initialize_instance_locals { 824 int dummy; 825 }; 826 827 struct dml2_optimization_init_function_locals { 828 union { 829 struct { 830 struct dml2_pmo_init_for_pstate_support_in_out init_params; 831 } uclk_pstate; 832 struct { 833 struct dml2_pmo_init_for_stutter_in_out stutter_params; 834 } stutter; 835 struct { 836 struct dml2_pmo_init_for_vmin_in_out init_params; 837 } vmin; 838 }; 839 }; 840 841 struct dml2_optimization_test_function_locals { 842 union { 843 struct { 844 struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params; 845 struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params; 846 struct top_mcache_validate_admissability_in_out validate_admissibility_params; 847 } test_mcache; 848 struct { 849 struct dml2_pmo_test_for_vmin_in_out pmo_test_vmin_params; 850 } test_vmin; 851 struct { 852 struct dml2_pmo_test_for_pstate_support_in_out test_params; 853 } uclk_pstate; 854 struct { 855 struct dml2_pmo_test_for_stutter_in_out stutter_params; 856 } stutter; 857 }; 858 }; 859 860 struct dml2_optimization_optimize_function_locals { 861 union { 862 struct { 863 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 864 } optimize_mcache; 865 struct { 866 struct dml2_pmo_optimize_for_vmin_in_out pmo_optimize_vmin_params; 867 } optimize_vmin; 868 struct { 869 struct dml2_pmo_optimize_for_pstate_support_in_out optimize_params; 870 } uclk_pstate; 871 struct { 872 struct dml2_pmo_optimize_for_stutter_in_out stutter_params; 873 } stutter; 874 }; 875 }; 876 877 struct dml2_optimization_phase_locals { 878 struct display_configuation_with_meta cur_candidate_display_cfg; 879 struct display_configuation_with_meta next_candidate_display_cfg; 880 struct dml2_core_mode_support_in_out mode_support_params; 881 struct dml2_optimization_init_function_locals init_function_locals; 882 struct dml2_optimization_test_function_locals test_function_locals; 883 struct dml2_optimization_optimize_function_locals optimize_function_locals; 884 }; 885 886 struct dml2_check_mode_supported_locals { 887 struct dml2_display_cfg display_cfg_working_copy; 888 struct dml2_core_mode_support_in_out mode_support_params; 889 struct dml2_optimization_phase_locals optimization_phase_locals; 890 struct display_configuation_with_meta base_display_config_with_meta; 891 struct display_configuation_with_meta optimized_display_config_with_meta; 892 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params; 893 }; 894 895 struct optimization_init_function_params { 896 struct dml2_optimization_init_function_locals *locals; 897 struct dml2_instance *dml; 898 struct display_configuation_with_meta *display_config; 899 }; 900 901 struct optimization_test_function_params { 902 struct dml2_optimization_test_function_locals *locals; 903 struct dml2_instance *dml; 904 struct display_configuation_with_meta *display_config; 905 }; 906 907 struct optimization_optimize_function_params { 908 bool last_candidate_supported; 909 struct dml2_optimization_optimize_function_locals *locals; 910 struct dml2_instance *dml; 911 struct display_configuation_with_meta *display_config; 912 struct display_configuation_with_meta *optimized_display_config; 913 }; 914 915 struct optimization_phase_params { 916 struct dml2_instance *dml; 917 const struct display_configuation_with_meta *display_config; // Initial Display Configuration 918 bool (*init_function)(const struct optimization_init_function_params *params); // Test function to determine optimization is complete 919 bool (*test_function)(const struct optimization_test_function_params *params); // Test function to determine optimization is complete 920 bool (*optimize_function)(const struct optimization_optimize_function_params *params); // Function which produces a more optimized display configuration 921 struct display_configuation_with_meta *optimized_display_config; // The optimized display configuration 922 923 bool all_or_nothing; 924 }; 925 926 struct dml2_build_mode_programming_locals { 927 struct dml2_core_mode_support_in_out mode_support_params; 928 struct dml2_core_mode_programming_in_out mode_programming_params; 929 struct dml2_core_populate_informative_in_out informative_params; 930 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 931 struct display_configuation_with_meta base_display_config_with_meta; 932 struct display_configuation_with_meta optimized_display_config_with_meta; 933 struct dml2_dpmm_map_mode_to_soc_dpm_params_in_out dppm_map_mode_params; 934 struct dml2_dpmm_map_watermarks_params_in_out dppm_map_watermarks_params; 935 struct dml2_optimization_phase_locals optimization_phase_locals; 936 struct optimization_phase_params min_clock_for_latency_phase; 937 struct optimization_phase_params mcache_phase; 938 struct optimization_phase_params uclk_pstate_phase; 939 struct optimization_phase_params vmin_phase; 940 struct optimization_phase_params stutter_phase; 941 }; 942 943 struct dml2_legacy_core_build_mode_programming_wrapper_locals { 944 struct dml2_core_mode_support_in_out mode_support_params; 945 struct dml2_core_mode_programming_in_out mode_programming_params; 946 struct dml2_core_populate_informative_in_out informative_params; 947 struct top_mcache_calc_mcache_count_and_offsets_in_out calc_mcache_count_params; 948 struct top_mcache_validate_admissability_in_out validate_admissibility_params; 949 struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; 950 struct top_mcache_assign_global_mcache_ids_in_out assign_global_mcache_ids_params; 951 struct dml2_pmo_optimize_dcc_mcache_in_out optimize_mcache_params; 952 struct dml2_display_cfg optimized_display_cfg; 953 struct core_display_cfg_support_info core_support_info; 954 }; 955 956 struct dml2_top_mcache_verify_mcache_size_locals { 957 struct dml2_calculate_mcache_allocation_in_out calc_mcache_params; 958 }; 959 960 struct dml2_top_mcache_validate_admissability_locals { 961 struct { 962 int pipe_vp_startx[DML2_MAX_DCN_PIPES]; 963 int pipe_vp_endx[DML2_MAX_DCN_PIPES]; 964 } plane0; 965 struct { 966 int pipe_vp_startx[DML2_MAX_DCN_PIPES]; 967 int pipe_vp_endx[DML2_MAX_DCN_PIPES]; 968 } plane1; 969 }; 970 971 struct dml2_top_display_cfg_support_info { 972 const struct dml2_display_cfg *display_config; 973 struct core_display_cfg_support_info core_info; 974 }; 975 976 struct dml2_top_funcs { 977 bool (*check_mode_supported)(struct dml2_check_mode_supported_in_out *in_out); 978 bool (*build_mode_programming)(struct dml2_build_mode_programming_in_out *in_out); 979 bool (*build_mcache_programming)(struct dml2_build_mcache_programming_in_out *in_out); 980 }; 981 982 struct dml2_instance { 983 enum dml2_project_id project_id; 984 985 struct dml2_core_instance core_instance; 986 struct dml2_mcg_instance mcg_instance; 987 struct dml2_dpmm_instance dpmm_instance; 988 struct dml2_pmo_instance pmo_instance; 989 990 struct dml2_soc_bb soc_bbox; 991 struct dml2_ip_capabilities ip_caps; 992 993 struct dml2_mcg_min_clock_table min_clk_table; 994 struct dml2_pmo_options pmo_options; 995 struct dml2_top_funcs funcs; 996 997 struct { 998 struct dml2_initialize_instance_locals initialize_instance_locals; 999 struct dml2_top_mcache_verify_mcache_size_locals mcache_verify_mcache_size_locals; 1000 struct dml2_top_mcache_validate_admissability_locals mcache_validate_admissability_locals; 1001 struct dml2_check_mode_supported_locals check_mode_supported_locals; 1002 struct dml2_build_mode_programming_locals build_mode_programming_locals; 1003 } scratch; 1004 1005 struct { 1006 struct { 1007 struct dml2_legacy_core_build_mode_programming_wrapper_locals legacy_core_build_mode_programming_wrapper_locals; 1008 } scratch; 1009 } legacy; 1010 }; 1011 #endif 1012