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Searched refs:ethsys (Results 1 – 13 of 13) sorted by relevance

/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi430 ethsys: syscon@1b000000 { label
431 compatible = "mediatek,mt7629-ethsys", "syscon";
445 <&ethsys CLK_ETH_ESW_EN>,
446 <&ethsys CLK_ETH_GP0_EN>,
447 <&ethsys CLK_ETH_GP1_EN>,
448 <&ethsys CLK_ETH_GP2_EN>,
449 <&ethsys CLK_ETH_FE_EN>,
471 mediatek,ethsys = <&ethsys>;
H A Dmt2701.dtsi720 ethsys: syscon@1b000000 { label
721 compatible = "mediatek,mt2701-ethsys", "syscon";
734 <&ethsys CLK_ETHSYS_ESW>,
735 <&ethsys CLK_ETHSYS_GP1>,
736 <&ethsys CLK_ETHSYS_GP2>,
739 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
740 <&ethsys MT2701_ETHSYS_GMAC_RST>,
741 <&ethsys MT2701_ETHSYS_PPE_RST>;
744 mediatek,ethsys = <&ethsys>;
H A Dmt7623.dtsi940 ethsys: syscon@1b000000 { label
941 compatible = "mediatek,mt7623-ethsys",
942 "mediatek,mt2701-ethsys",
953 clocks = <&ethsys CLK_ETHSYS_HSDMA>;
968 <&ethsys CLK_ETHSYS_ESW>,
969 <&ethsys CLK_ETHSYS_GP1>,
970 <&ethsys CLK_ETHSYS_GP2>,
973 resets = <&ethsys MT2701_ETHSYS_FE_RST>,
974 <&ethsys MT2701_ETHSYS_GMAC_RST>,
975 <&ethsys MT2701_ETHSYS_PPE_RST>;
[all …]
H A Dmt7623a.dtsi54 resets = <&ethsys MT2701_ETHSYS_MCM_RST>;
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_path.c144 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in set_mux_gmac1_gmac2_to_sgmii_rgmii()
159 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in set_mux_gmac1_gmac2_to_sgmii_rgmii()
173 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in set_mux_gmac12_to_gephy_sgmii()
190 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in set_mux_gmac12_to_gephy_sgmii()
H A Dmtk_eth_soc.c485 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, in mt7621_gmac0_rgmii_adjust()
622 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
625 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); in mtk_mac_config()
636 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); in mtk_mac_config()
638 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_config()
682 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, in mtk_mac_finish()
3572 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3577 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, in ethsys_reset()
3701 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); in mtk_hw_reset()
3725 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, in mtk_hw_reset()
[all …]
H A Dmtk_eth_soc.h1246 struct regmap *ethsys; member
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a.dtsi490 ethsys: syscon@15000000 { label
491 compatible = "mediatek,mt7986-ethsys",
531 clocks = <&ethsys CLK_ETH_FE_EN>,
532 <&ethsys CLK_ETH_GP2_EN>,
533 <&ethsys CLK_ETH_GP1_EN>,
534 <&ethsys CLK_ETH_WOCPU1_EN>,
535 <&ethsys CLK_ETH_WOCPU0_EN>,
558 mediatek,ethsys = <&ethsys>;
H A Dmt7622.dtsi925 ethsys: clock-controller@1b000000 { label
926 compatible = "mediatek,mt7622-ethsys",
937 clocks = <&ethsys CLK_ETH_HSDMA_EN>;
971 <&ethsys CLK_ETH_ESW_EN>,
972 <&ethsys CLK_ETH_GP0_EN>,
973 <&ethsys CLK_ETH_GP1_EN>,
974 <&ethsys CLK_ETH_GP2_EN>,
986 mediatek,ethsys = <&ethsys>;
H A Dmt7988a.dtsi202 compatible = "mediatek,mt7988-ethsys", "syscon";
H A Dmt7981b.dtsi217 compatible = "mediatek,mt7981-ethsys", "syscon";
/linux/Documentation/devicetree/bindings/crypto/
H A Dmediatek-crypto.txt22 clocks = <&ethsys CLK_ETHSYS_CRYPTO>;
/linux/drivers/clk/mediatek/
H A DKconfig54 bool "Clock driver for MediaTek MT2701 ethsys"
57 This driver supports MediaTek MT2701 ethsys clocks.