Searched refs:ep0state (Results 1 – 11 of 11) sorted by relevance
254 if (dev->ep0state == EP0_SUSPEND) in goku_ep_disable()362 if (unlikely(ep->num == 0 && dev->ep0state != EP0_IN)) in write_fifo()380 dev->ep0state = EP0_STATUS; in write_fifo()420 if (unlikely(ep->num == 0 && ep->dev->ep0state != EP0_OUT)) in read_fifo()486 ep->dev->ep0state = EP0_STATUS; in read_fifo()732 if (dev->ep0state == EP0_SUSPEND) in goku_queue()825 if (dev->ep0state == EP0_SUSPEND) in goku_dequeue()895 ep->dev->ep0state = EP0_STALL; in goku_set_halt()1091 static const char *udc_ep_state(enum ep0state state) in udc_ep_state()1162 udc_ep_state(dev->ep0state)); in udc_proc_read()[all …]
98 enum ep0_state ep0state; member178 label, state_name[the_controller->ep0state], udccs0, in dump_udccs0()198 state_name[dev->ep0state], in dump_state()
229 enum ep0state { enum245 enum ep0state ep0state; member
314 enum usbf_ep0state ep0state; member1793 ep0->udc->ep0state = EP0_IDLE; in usbf_ep0_enable()1927 if (ep0->udc->ep0state == EP0_IN_STATUS_START_PHASE) in usbf_ep0_queue()1933 if (ep0->udc->ep0state == EP0_IN_STATUS_PHASE) { in usbf_ep0_queue()2059 ep->udc->ep0state = EP0_IDLE; in usbf_ep_dequeue()2465 udc->ep0state = EP0_IN_DATA_PHASE; in usbf_handle_ep0_setup()2471 udc->ep0state = EP0_OUT_DATA_PHASE; in usbf_handle_ep0_setup()2477 udc->ep0state = EP0_IN_STATUS_START_PHASE; in usbf_handle_ep0_setup()2540 udc->ep0state = next_ep0state; in usbf_handle_ep0_data_status()2572 udc->ep0state = EP0_OUT_STATUS_PHASE; in usbf_handle_ep0_out_status_start()[all …]
563 dev->ep0state = EP0_IDLE; in ep0_idle()883 switch (dev->ep0state) { in pxa25x_ep_queue()900 dev->ep0state = EP0_END_XFER; in pxa25x_ep_queue()915 DMSG("ep0 i/o, odd state %d\n", dev->ep0state); in pxa25x_ep_queue()1033 ep->dev->ep0state = EP0_STALL; in pxa25x_ep_set_halt()1385 dev->ep0state = EP0_IDLE; in udc_reinit()1580 if (dev->ep0state == EP0_STALL in udc_watchdog()1615 if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) { in handle_ep0()1621 switch (dev->ep0state) { in handle_ep0()1697 dev->ep0state = EP0_IN_DATA_PHASE; in handle_ep0()[all …]
166 int ep0state; member1393 udc->ep0state = WAIT_FOR_SETUP; in udc_reinit()1472 udc->ep0state = WAIT_FOR_SETUP; in udc_ep0_in_req()1493 udc->ep0state = WAIT_FOR_SETUP; in udc_ep0_out_req()1511 udc->ep0state = WAIT_FOR_SETUP; in udc_ep0_out_req()1804 udc->ep0state = DATA_IN; in lpc32xx_ep_queue()1808 udc->ep0state = DATA_OUT; in lpc32xx_ep_queue()2296 udc->ep0state = WAIT_FOR_SETUP; in udc_handle_ep0_setup()2332 udc->ep0state = WAIT_FOR_SETUP; in udc_handle_ep0_in()2339 if (udc->ep0state == DATA_IN) in udc_handle_ep0_in()[all …]
404 #define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state]459 enum ep0_state ep0state; member
195 enum gr_ep0state ep0state; member
115 if (dwc->ep0state != EP0_DATA_PHASE) { in __dwc3_gadget_ep0_queue()139 if (dwc->ep0state == EP0_STATUS_PHASE) in __dwc3_gadget_ep0_queue()181 dwc->ep0state = EP0_DATA_PHASE; in __dwc3_gadget_ep0_queue()252 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_stall_and_restart()955 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_complete_status()968 switch (dwc->ep0state) { in dwc3_ep0_xfer_complete()981 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); in dwc3_ep0_xfer_complete()1109 if (dwc->ep0state != EP0_STATUS_PHASE) in dwc3_ep0_send_delayed_status()1177 dwc->ep0state = EP0_STATUS_PHASE; in dwc3_ep0_xfernotready()
146 if (dwc->ep0state != EP0_SETUP_PHASE) { in dwc3_ep0_reset_state()148 if (dwc->ep0state == EP0_DATA_PHASE) in dwc3_ep0_reset_state()1778 if (ret == -ETIMEDOUT && dep->dwc->ep0state != EP0_SETUP_PHASE) { in __dwc3_stop_active_transfer()2734 if (dwc->ep0state != EP0_SETUP_PHASE) { in dwc3_gadget_soft_disconnect()2991 dwc->ep0state = EP0_SETUP_PHASE; in __dwc3_gadget_start()3989 if (dep->number <= 1 && dwc->ep0state != EP0_DATA_PHASE) in dwc3_stop_active_transfer()4006 if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) { in dwc3_stop_active_transfer()
566 dwc3_decode_event(__entry->event, __entry->ep0state))