Searched refs:ep0state (Results 1 – 10 of 10) sorted by relevance
316 int ep0state; member971 udc->ep0state = EP0_SHUTDOWN; in bcm63xx_init_udc_hw()1538 udc->ep0state = EP0_IN_FAKE_STATUS_PHASE; in bcm63xx_ep0_do_idle()1542 udc->ep0state = EP0_IN_FAKE_STATUS_PHASE; in bcm63xx_ep0_do_idle()1544 udc->ep0state = bcm63xx_ep0_do_setup(udc); in bcm63xx_ep0_do_idle()1545 return udc->ep0state == EP0_IDLE ? -EAGAIN : 0; in bcm63xx_ep0_do_idle()1556 udc->ep0state = EP0_SHUTDOWN; in bcm63xx_ep0_do_idle()1580 enum bcm63xx_ep0_state ep0state = udc->ep0state; in bcm63xx_ep0_one_round() local1583 switch (udc->ep0state) { in bcm63xx_ep0_one_round()1588 ep0state = EP0_IDLE; in bcm63xx_ep0_one_round()[all …]
229 enum ep0state { enum245 enum ep0state ep0state; member
193 seq_printf(seq, "ep0state = %s\n", gr_ep0state_string(dev->ep0state)); in gr_dfs_show()599 if (dev->ep0state == GR_EP0_SUSPEND) { in gr_queue()695 dev->ep0state = GR_EP0_STALL; in gr_control_stall()751 if (dev->ep0state != value) in gr_set_ep0state()754 dev->ep0state = value; in gr_set_ep0state()1059 if (dev->ep0state == GR_EP0_STALL) { in gr_ep0_setup()1065 if (dev->ep0state == GR_EP0_ISTATUS) { in gr_ep0_setup()1073 } else if (dev->ep0state != GR_EP0_SETUP) { in gr_ep0_setup()1076 gr_ep0state_string(dev->ep0state)); in gr_ep0_setup()1082 gr_ep0state_string(dev->ep0state)); in gr_ep0_setup()[all …]
313 enum usbf_ep0state ep0state; member1792 ep0->udc->ep0state = EP0_IDLE; in usbf_ep0_enable()1926 if (ep0->udc->ep0state == EP0_IN_STATUS_START_PHASE) in usbf_ep0_queue()1932 if (ep0->udc->ep0state == EP0_IN_STATUS_PHASE) { in usbf_ep0_queue()2058 ep->udc->ep0state = EP0_IDLE; in usbf_ep_dequeue()2464 udc->ep0state = EP0_IN_DATA_PHASE; in usbf_handle_ep0_setup()2470 udc->ep0state = EP0_OUT_DATA_PHASE; in usbf_handle_ep0_setup()2476 udc->ep0state = EP0_IN_STATUS_START_PHASE; in usbf_handle_ep0_setup()2539 udc->ep0state = next_ep0state; in usbf_handle_ep0_data_status()2571 udc->ep0state = EP0_OUT_STATUS_PHASE; in usbf_handle_ep0_out_status_start()[all …]
166 int ep0state; member1393 udc->ep0state = WAIT_FOR_SETUP; in udc_reinit()1472 udc->ep0state = WAIT_FOR_SETUP; in udc_ep0_in_req()1493 udc->ep0state = WAIT_FOR_SETUP; in udc_ep0_out_req()1511 udc->ep0state = WAIT_FOR_SETUP; in udc_ep0_out_req()1804 udc->ep0state = DATA_IN; in lpc32xx_ep_queue()1808 udc->ep0state = DATA_OUT; in lpc32xx_ep_queue()2296 udc->ep0state = WAIT_FOR_SETUP; in udc_handle_ep0_setup()2332 udc->ep0state = WAIT_FOR_SETUP; in udc_handle_ep0_in()2339 if (udc->ep0state == DATA_IN) in udc_handle_ep0_in()[all …]
195 enum gr_ep0state ep0state; member
480 udc->ep0state = state; in set_ep0state()1108 switch (dev->ep0state) { in pxa_ep_queue()1976 switch (udc->ep0state) { in handle_ep0()
115 if (dwc->ep0state != EP0_DATA_PHASE) { in __dwc3_gadget_ep0_queue() 139 if (dwc->ep0state == EP0_STATUS_PHASE) in __dwc3_gadget_ep0_queue() 181 dwc->ep0state = EP0_DATA_PHASE; in __dwc3_gadget_ep0_queue() 257 dwc->ep0state = EP0_SETUP_PHASE; in __dwc3_gadget_ep0_set_halt() 964 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_ep0_xfer_complete() 977 switch (dwc->ep0state) { in dwc3_ep0_xfer_complete() 990 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); in __dwc3_ep0_do_control_data() 1118 if (dwc->ep0state != EP0_STATUS_PHASE) in dwc3_ep0_end_control_data() 1186 dwc->ep0state in dwc3_ep0_xfernotready() [all...]
146 if (dwc->ep0state != EP0_SETUP_PHASE) { in dwc3_ep0_reset_state() 148 if (dwc->ep0state == EP0_DATA_PHASE) in dwc3_ep0_reset_state() 1786 * ep0state returns to EP0_SETUP_PHASE. in __dwc3_stop_active_transfer() 1788 if (ret == -ETIMEDOUT && dep->dwc->ep0state != EP0_SETUP_PHASE) { in __dwc3_stop_active_transfer() 2764 if (dwc->ep0state != EP0_SETUP_PHASE) { in dwc3_gadget_soft_disconnect() 3024 dwc->ep0state = EP0_SETUP_PHASE; in dwc3_gadget_start() 4064 if (dep->number <= 1 && dwc->ep0state != EP0_DATA_PHASE) in dwc3_stop_active_transfer() 4081 if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) { in dwc3_stop_active_transfer()
566 dwc3_decode_event(__entry->event, __entry->ep0state))