| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | selftest_rc6.c | 194 struct intel_engine_cs *engine, **engines; in randomised_engines() local
204 engines = kmalloc_objs(*engines, n); in randomised_engines()
205 if (!engines) in randomised_engines()
210 engines[n++] = engine; in randomised_engines()
212 i915_prandom_shuffle(engines, sizeof(*engines), n, prng); in randomised_engines()
215 return engines; in randomised_engines()
221 struct intel_engine_cs **engines; in live_rc6_ctx_wa() local
230 engines = randomised_engines(gt, &prng, &count); in live_rc6_ctx_wa()
231 if (!engines) in live_rc6_ctx_wa()
235 struct intel_engine_cs *engine = engines[n]; in live_rc6_ctx_wa()
[all …]
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| /linux/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_context.c | 396 struct i915_gem_proto_engine *engines; member
425 if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_INVALID) { in set_proto_ctx_engines_balance()
452 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) { in set_proto_ctx_engines_balance()
470 set->engines[idx].type = I915_GEM_ENGINE_TYPE_PHYSICAL; in set_proto_ctx_engines_balance()
471 set->engines[idx].engine = siblings[0]; in set_proto_ctx_engines_balance()
474 set->engines[idx].type = I915_GEM_ENGINE_TYPE_BALANCED; in set_proto_ctx_engines_balance()
475 set->engines[idx].num_siblings = num_siblings; in set_proto_ctx_engines_balance()
476 set->engines[idx].siblings = siblings; in set_proto_ctx_engines_balance()
517 if (set->engines[idx].type == I915_GEM_ENGINE_TYPE_INVALID) { in set_proto_ctx_engines_bond()
522 if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_PHYSICAL) { in set_proto_ctx_engines_bond()
[all …]
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| /linux/Documentation/devicetree/bindings/fsi/ |
| H A D | fsi.txt | 5 engines within those slaves. However, we have a facility to match devicetree
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
16 represent the FSI slaves and their slave engines. As a basic outline:
41 adding subordinate device tree nodes as children of FSI engines.
79 Each slave provides an address-space, under which the engines are accessible.
91 FSI engines (devices)
116 additional engines, but they don't necessarily need to be describe in the
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| /linux/drivers/gpu/drm/i915/gt/uc/ |
| H A D | selftest_guc_multi_lrc.c | 13 static void logical_sort(struct intel_engine_cs **engines, int num_engines) in logical_sort() argument
20 if (engines[j]->logical_mask & BIT(i)) { in logical_sort()
21 sorted[i] = engines[j]; in logical_sort()
26 memcpy(*engines, *sorted, in logical_sort()
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| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_query.c | 189 struct drm_xe_query_engines *engines; in query_engines() local
203 engines = kzalloc(size, GFP_KERNEL); in query_engines()
204 if (!engines) in query_engines()
212 engines->engines[i].instance.engine_class = in query_engines()
214 engines->engines[i].instance.engine_instance = in query_engines()
216 engines->engines[i].instance.gt_id = gt->info.id; in query_engines()
221 engines->num_engines = i; in query_engines()
223 if (copy_to_user(query_ptr, engines, size)) { in query_engines()
224 kfree(engines); in query_engines()
227 kfree(engines); in query_engines()
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| H A D | xe_gt_sriov_pf_debugfs.c | 378 char engines[128]; in sched_group_engines_read() local
380 engines[0] = '\0'; in sched_group_engines_read()
385 u32 mask = groups[group].engines[guc_class]; in sched_group_engines_read()
388 strlcat(engines, hwe->name, sizeof(engines)); in sched_group_engines_read()
389 strlcat(engines, " ", sizeof(engines)); in sched_group_engines_read()
392 strlcat(engines, "\n", sizeof(engines)); in sched_group_engines_read()
395 return simple_read_from_buffer(buf, count, ppos, engines, strlen(engines)); in sched_group_engines_read()
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| /linux/Documentation/netlabel/ |
| H A D | introduction.rst | 15 is composed of three main components, the protocol engines, the communication
21 The protocol engines are responsible for both applying and retrieving the
25 refrain from calling the protocol engines directly, instead they should use
45 independent interface to the underlying NetLabel protocol engines. In addition
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| /linux/Documentation/misc-devices/ |
| H A D | mrvl_cn10k_dpi.rst | 12 mailbox logic, and a set of DMA engines & DMA command queues.
20 the DMA engines and VF device's DMA command queues. Also, driver creates
38 a pem port to which DMA engines are wired.
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| /linux/drivers/gpu/drm/omapdrm/ |
| H A D | omap_dmm_tiler.c | 292 if (dmm->engines[i].async) in omap_dmm_irq_handler()
293 release_engine(&dmm->engines[i]); in omap_dmm_irq_handler()
295 complete(&dmm->engines[i].compl); in omap_dmm_irq_handler()
753 kfree(omap_dmm->engines); in omap_dmm_remove()
888 omap_dmm->engines = kzalloc_objs(*omap_dmm->engines, in omap_dmm_probe()
890 if (!omap_dmm->engines) { in omap_dmm_probe()
896 omap_dmm->engines[i].id = i; in omap_dmm_probe()
897 omap_dmm->engines[i].dmm = omap_dmm; in omap_dmm_probe()
898 omap_dmm->engines[i].refill_va = omap_dmm->refill_va + in omap_dmm_probe()
900 omap_dmm->engines[i].refill_pa = omap_dmm->refill_pa + in omap_dmm_probe()
[all …]
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-hsi | 8 engines (APE) with cellular modem engines (CMT) in cellular
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| /linux/include/uapi/drm/ |
| H A D | i915_drm.h | 2328 struct i915_engine_class_instance engines[]; member
2337 struct i915_engine_class_instance engines[N__]; \
2366 struct i915_engine_class_instance engines[]; member
2376 struct i915_engine_class_instance engines[N__]; \
2493 struct i915_engine_class_instance engines[]; member
2505 struct i915_engine_class_instance engines[N__]; \
2568 struct i915_engine_class_instance engines[]; member
2573 struct i915_engine_class_instance engines[N__]; \
3384 struct drm_i915_engine_info engines[]; member
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| /linux/tools/include/uapi/drm/ |
| H A D | i915_drm.h | 2328 struct i915_engine_class_instance engines[]; member
2337 struct i915_engine_class_instance engines[N__]; \
2366 struct i915_engine_class_instance engines[]; member
2376 struct i915_engine_class_instance engines[N__]; \
2493 struct i915_engine_class_instance engines[]; member
2505 struct i915_engine_class_instance engines[N__]; \
2568 struct i915_engine_class_instance engines[]; member
2573 struct i915_engine_class_instance engines[N__]; \
3384 struct drm_i915_engine_info engines[]; member
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| /linux/drivers/gpu/drm/nouveau/nvif/ |
| H A D | fifo.c | 62 device->runlist[i].engines = a->v.runlist[i].data; in nvif_fifo_runlists()
80 if (device->runlist[i].engines & engine) in nvif_fifo_runlist()
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| /linux/drivers/gpu/drm/i915/gem/selftests/ |
| H A D | mock_context.c | 32 INIT_LIST_HEAD(&ctx->stale.engines); in mock_context()
52 RCU_INIT_POINTER(ctx->engines, e); in mock_context()
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| H A D | huge_pages.c | 1195 struct i915_gem_engines *engines; in igt_write_huge() local
1263 engines = i915_gem_context_lock_engines(ctx); in igt_write_huge()
1270 ce = engines->engines[order[i] % engines->num_engines]; in igt_write_huge()
1616 struct i915_gem_engines *engines; in igt_ppgtt_mixed() local
1714 engines = i915_gem_context_lock_engines(ctx); in igt_ppgtt_mixed()
1720 ce = engines->engines[order[i] % engines->num_engines]; in igt_ppgtt_mixed()
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| /linux/drivers/gpu/drm/i915/ |
| H A D | Kconfig.profile | 45 The driver sends a periodic heartbeat down all active engines to
70 certain platforms and certain engines which will be reflected in the
74 int "Preempt timeout for compute engines (ms, jiffy granularity)"
89 certain platforms and certain engines which will be reflected in the
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| /linux/Documentation/devicetree/bindings/powerpc/4xx/ |
| H A D | ppc440spe-adma.txt | 5 for DMA engines and Memory Queue Module node. The latter is used
40 for both DMA engines>.
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce80/ |
| H A D | dce80_resource.c | 858 if (pool->base.engines[i] != NULL) in dce80_resource_destruct()
859 dce110_engine_destroy(&pool->base.engines[i]); in dce80_resource_destruct()
1062 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce80_construct()
1063 if (pool->base.engines[i] == NULL) { in dce80_construct()
1262 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce81_construct()
1263 if (pool->base.engines[i] == NULL) { in dce81_construct()
1460 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); in dce83_construct()
1461 if (pool->base.engines[i] == NULL) { in dce83_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dce60/ |
| H A D | dce60_resource.c | 852 if (pool->base.engines[i] != NULL) in dce60_resource_destruct()
853 dce110_engine_destroy(&pool->base.engines[i]); in dce60_resource_destruct()
1051 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); in dce60_construct()
1052 if (pool->base.engines[i] == NULL) { in dce60_construct()
1249 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); in dce61_construct()
1250 if (pool->base.engines[i] == NULL) { in dce61_construct()
1446 pool->base.engines[i] = dce60_aux_engine_create(ctx, i); in dce64_construct()
1447 if (pool->base.engines[i] == NULL) { in dce64_construct()
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| /linux/drivers/gpu/drm/i915/selftests/ |
| H A D | i915_request.c | 3192 struct p_thread *engines; in perf_parallel_engines() local
3195 engines = kzalloc_objs(*engines, nengines); in perf_parallel_engines()
3196 if (!engines) in perf_parallel_engines()
3219 memset(&engines[idx].p, 0, sizeof(engines[idx].p)); in perf_parallel_engines()
3228 engines[idx].worker = worker; in perf_parallel_engines()
3229 engines[idx].result = 0; in perf_parallel_engines()
3230 engines[idx].p.engine = engine; in perf_parallel_engines()
3231 engines[idx].engine = engine; in perf_parallel_engines()
3233 kthread_init_work(&engines[idx].work, *fn); in perf_parallel_engines()
3234 kthread_queue_work(worker, &engines[idx].work); in perf_parallel_engines()
[all …]
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| /linux/drivers/gpu/drm/nouveau/include/nvif/ |
| H A D | device.h | 14 u64 engines; member
|
| /linux/Documentation/arch/powerpc/ |
| H A D | vas-api.rst | 14 unit comprises of one or more hardware engines or co-processor types
62 access to all GZIP engines in the system. The only valid operations on
79 engines (typically, one per P9 chip) there is just one
130 "Discovery of available VAS engines" section below.
168 that the application can use to copy/paste its CRB to the hardware engines.
190 Discovery of available VAS engines
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| /linux/Documentation/gpu/rfc/ |
| H A D | i915_scheduler.rst | 43 * Features like timeslicing / preemption / virtual engines would
104 * Export engines logical mapping
109 Export engines logical mapping
116 engines in logical order which is a new requirement compared to execlists.
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| /linux/drivers/hsi/ |
| H A D | Kconfig | 10 application engines and cellular modems.
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| /linux/drivers/dma/idxd/ |
| H A D | defaults.c | 44 engine = idxd->engines[0]; in idxd_load_iaa_device_defaults()
|