Home
last modified time | relevance | path

Searched refs:engine_mask (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/xe/
H A Dxe_hw_engine.c512 if (!(gt->info.engine_mask & BIT(id))) in hw_engine_init_early()
696 xe_gt_assert(gt, gt->info.engine_mask & BIT(id)); in hw_engine_init()
836 if (!(gt->info.engine_mask & BIT(i))) in read_media_fuses()
840 gt->info.engine_mask &= ~BIT(i); in read_media_fuses()
846 if (!(gt->info.engine_mask & BIT(i))) in read_media_fuses()
850 gt->info.engine_mask &= ~BIT(i); in read_media_fuses()
895 if (!(gt->info.engine_mask & BIT(i))) in read_copy_fuses()
899 gt->info.engine_mask &= ~BIT(i); in read_copy_fuses()
912 if (hweight64(gt->info.engine_mask & in read_compute_fuses_from_dss()
921 if (!(gt->info.engine_mask & BIT(i))) in read_compute_fuses_from_dss()
[all …]
H A Dxe_gt_idle.c134 if ((gt->info.engine_mask & BIT(i))) in xe_gt_idle_enable_pg()
251 if (gt->info.engine_mask & in xe_gt_idle_pg_print()
269 if (gt->info.engine_mask & media_slices[n].engines) in xe_gt_idle_pg_print()
278 if (gt->info.engine_mask & BIT(XE_HW_ENGINE_GSCCS0)) { in xe_gt_idle_pg_print()
H A Dxe_ring_ops.c216 bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK); in emit_render_cache_flush()
453 bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK); in __emit_job_gen12_render_compute()
H A Dxe_rtp.c434 u64 render_compute_mask = gt->info.engine_mask & in xe_rtp_match_first_render_or_compute()
H A Dxe_guc_ads.c740 u32 engine_mask = guc_get_capture_engine_mask(gt, &info_map, j); in guc_capture_prep_lists() local
742 if (!engine_mask) { in guc_capture_prep_lists()
/linux/drivers/gpu/drm/i915/gvt/
H A Dscheduler.h148 intel_engine_mask_t engine_mask);
153 intel_engine_mask_t engine_mask,
167 intel_engine_mask_t engine_mask);
H A Dvgpu.c438 intel_engine_mask_t engine_mask) in intel_gvt_reset_vgpu_locked() argument
442 intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask; in intel_gvt_reset_vgpu_locked()
446 vgpu->id, dmlr, engine_mask); in intel_gvt_reset_vgpu_locked()
463 if (engine_mask == ALL_ENGINES || dmlr) { in intel_gvt_reset_vgpu_locked()
465 if (engine_mask == ALL_ENGINES) in intel_gvt_reset_vgpu_locked()
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_types.h262 intel_engine_mask_t engine_mask; member
308 intel_engine_mask_t engine_mask; member
H A Dintel_engine_cs.c789 gt->info.engine_mask &= ~BIT(_VCS(i)); in engine_mask_apply_media_fuses()
808 gt->info.engine_mask &= ~BIT(_VECS(i)); in engine_mask_apply_media_fuses()
837 info->engine_mask &= ~BIT(_CCS(i)); in engine_mask_apply_compute_fuses()
856 GEM_BUG_ON(!info->engine_mask); in init_engine_mask()
873 if (__HAS_ENGINE(info->engine_mask, GSC0) && !intel_uc_wants_gsc_uc(&gt->uc)) { in init_engine_mask()
875 info->engine_mask &= ~BIT(GSC0); in init_engine_mask()
896 info->engine_mask &= ~GENMASK(CCS3, CCS0); in init_engine_mask()
898 info->engine_mask |= BIT(_CCS(first_ccs)); in init_engine_mask()
901 return info->engine_mask; in init_engine_mask()
956 const unsigned int engine_mask = init_engine_mask(gt); in intel_engines_init_mmio() local
[all …]
H A Dintel_breadcrumbs_types.h50 intel_engine_mask_t engine_mask; member
H A Dintel_gt.h150 intel_engine_mask_t engine_mask);
193 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_umsch_mm.h49 uint32_t engine_mask; member
169 uint32_t engine_mask; member
H A Dumsch_mm_v4_0.c283 set_hw_resources.engine_mask = umsch->engine_mask; in umsch_mm_v4_0_set_hw_resources()
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_gsc_uc.c108 GEM_BUG_ON(!gt_is_root(gt) && !gt->info.engine_mask); in gsc_engine_supported()
113 mask = gt->info.engine_mask; in gsc_engine_supported()
H A Dintel_guc_ads.c738 u32 engine_mask = guc_get_capture_engine_mask(&info_map, j); in guc_capture_prep_lists() local
741 if (!engine_mask) { in guc_capture_prep_lists()
/linux/drivers/gpu/drm/amd/include/
H A Dumsch_mm_4_0_api_def.h216 uint32_t engine_mask; member
/linux/drivers/gpu/drm/i915/
H A Di915_pci.c754 .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2) | BIT(GSC0),