Searched refs:engineClock (Results 1 – 4 of 4) sorted by relevance
100 uint32_t engineClock; member
913 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in smu7_setup_dpm_tables_v1()914 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; in smu7_setup_dpm_tables_v1()3105 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu7_hwmgr_backend_init()3472 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()3495 minimum_clocks.engineClock = stable_pstate_sclk; in smu7_apply_state_adjust_rules()3527 if (sclk < minimum_clocks.engineClock) in smu7_apply_state_adjust_rules()3528 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in smu7_apply_state_adjust_rules()3529 max_limits->sclk : minimum_clocks.engineClock; in smu7_apply_state_adjust_rules()5179 .engineClock / in smu7_emit_clock_levels()5609 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { in smu7_check_clk_voltage_valid()[all …]
437 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega12_hwmgr_backend_init()
480 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega20_hwmgr_backend_init()