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Searched refs:engineClock (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_processpptables.c208 hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX; in init_powerplay_table_information()
210 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_powerplay_table_information()
228 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 in init_powerplay_table_information()
H A Dsmu8_hwmgr.c417 data->boot_power_level.engineClock = in smu8_construct_boot_state()
1366 return smu8_ps->levels[0].engineClock; in smu8_dpm_get_sclk()
1368 return smu8_ps->levels[smu8_ps->level-1].engineClock; in smu8_dpm_get_sclk()
1402 smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk; in smu8_dpm_get_pp_table_entry_callback()
1623 level->coreClock = ps->levels[level_index].engineClock; in smu8_get_performance_level()
1627 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) { in smu8_get_performance_level()
1628 level->coreClock = ps->levels[i].engineClock; in smu8_get_performance_level()
1651 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex)); in smu8_get_current_shallow_sleep_clocks()
1652 …clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1]… in smu8_get_current_shallow_sleep_clocks()
H A Dsmu8_hwmgr.h100 uint32_t engineClock; member
H A Dvega10_hwmgr.c922 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega10_hwmgr_backend_init()
1365 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in vega10_setup_default_dpm_tables()
1366 hwmgr->platform_descriptor.overdriveLimit.engineClock = in vega10_setup_default_dpm_tables()
1623 hwmgr->platform_descriptor.overdriveLimit.engineClock; in vega10_populate_single_gfx_level()
3328 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()
3359 minimum_clocks.engineClock = stable_pstate_sclk; in vega10_apply_state_adjust_rules()
3381 if (sclk < minimum_clocks.engineClock) in vega10_apply_state_adjust_rules()
3382 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in vega10_apply_state_adjust_rules()
3383 max_limits->sclk : minimum_clocks.engineClock; in vega10_apply_state_adjust_rules()
4813 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in vega10_emit_clock_levels()
[all …]
H A Dprocesspptables.c1115 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_overdrive_limits_V1_4()
1153 hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock); in init_overdrive_limits_V2_1()
1173 hwmgr->platform_descriptor.overdriveLimit.engineClock = 0; in init_overdrive_limits()
H A Dvega10_processpptables.c326 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
329 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
H A Dprocess_pptables_v1_0.c889 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
H A Dvega12_hwmgr.c437 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega12_hwmgr_backend_init()
H A Dvega20_hwmgr.c480 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega20_hwmgr_backend_init()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_types.h747 unsigned int engineClock; member