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Searched refs:ecc (Results 1 – 25 of 315) sorted by relevance

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/linux/drivers/mtd/nand/
H A Decc-mtk.c126 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc, in mtk_ecc_wait_idle() argument
129 struct device *dev = ecc->dev; in mtk_ecc_wait_idle()
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val, in mtk_ecc_wait_idle()
143 struct mtk_ecc *ecc = id; in mtk_ecc_irq() local
146 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]) in mtk_ecc_irq()
149 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]); in mtk_ecc_irq()
150 if (dec & ecc->sectors) { in mtk_ecc_irq()
155 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]); in mtk_ecc_irq()
156 ecc->sectors = 0; in mtk_ecc_irq()
157 complete(&ecc->done); in mtk_ecc_irq()
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H A Decc-sw-bch.c26 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_calculate()
30 bch_encode(engine_conf->bch, buf, nand->ecc.ctx.conf.step_size, code); in nand_ecc_sw_bch_calculate()
52 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_correct()
53 unsigned int step_size = nand->ecc.ctx.conf.step_size; in nand_ecc_sw_bch_correct()
84 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_cleanup()
110 struct nand_ecc_sw_bch_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_bch_init()
111 unsigned int eccsize = nand->ecc.ctx.conf.step_size; in nand_ecc_sw_bch_init()
172 struct nand_ecc_props *conf = &nand->ecc.ctx.conf; in nand_ecc_sw_bch_init_ctx()
189 conf->step_size = nand->ecc.user_conf.step_size; in nand_ecc_sw_bch_init_ctx()
190 conf->strength = nand->ecc.user_conf.strength; in nand_ecc_sw_bch_init_ctx()
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H A Decc-sw-hamming.c365 struct nand_ecc_sw_hamming_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_hamming_calculate()
366 unsigned int step_size = nand->ecc.ctx.conf.step_size; in nand_ecc_sw_hamming_calculate()
458 struct nand_ecc_sw_hamming_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_hamming_correct()
459 unsigned int step_size = nand->ecc.ctx.conf.step_size; in nand_ecc_sw_hamming_correct()
469 struct nand_ecc_props *conf = &nand->ecc.ctx.conf; in nand_ecc_sw_hamming_init_ctx()
492 conf->step_size = nand->ecc.user_conf.step_size; in nand_ecc_sw_hamming_init_ctx()
515 nand->ecc.ctx.priv = engine_conf; in nand_ecc_sw_hamming_init_ctx()
516 nand->ecc.ctx.nsteps = mtd->writesize / conf->step_size; in nand_ecc_sw_hamming_init_ctx()
517 nand->ecc.ctx.total = nand->ecc.ctx.nsteps * engine_conf->code_size; in nand_ecc_sw_hamming_init_ctx()
534 struct nand_ecc_sw_hamming_conf *engine_conf = nand->ecc.ctx.priv; in nand_ecc_sw_hamming_cleanup_ctx()
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/linux/drivers/mtd/nand/raw/ingenic/
H A Dingenic_ecc.c28 int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
32 return ecc->ops->calculate(ecc, params, buf, ecc_code); in ingenic_ecc_calculate()
48 int ingenic_ecc_correct(struct ingenic_ecc *ecc, in ingenic_ecc_correct() argument
52 return ecc->ops->correct(ecc, params, buf, ecc_code); in ingenic_ecc_correct()
69 struct ingenic_ecc *ecc; in ingenic_ecc_get() local
80 ecc = platform_get_drvdata(pdev); in ingenic_ecc_get()
81 clk_prepare_enable(ecc->clk); in ingenic_ecc_get()
83 return ecc; in ingenic_ecc_get()
98 struct ingenic_ecc *ecc = NULL; in of_ingenic_ecc_get() local
111 ecc = ingenic_ecc_get(np); in of_ingenic_ecc_get()
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H A Dingenic_nand_drv.c44 struct ingenic_ecc *ecc; member
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
90 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_free() local
95 oobregion->length = mtd->oobsize - ecc->total - 12; in qi_lb60_ooblayout_free()
96 oobregion->offset = 12 + ecc->total; in qi_lb60_ooblayout_free()
102 .ecc = qi_lb60_ooblayout_ecc,
110 struct nand_ecc_ctrl *ecc = &chip->ecc; in jz4725b_ooblayout_ecc() local
112 if (section || !ecc->total) in jz4725b_ooblayout_ecc()
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H A Djz4740_ecc.c45 static void jz4740_ecc_reset(struct ingenic_ecc *ecc, bool calc_ecc) in jz4740_ecc_reset() argument
50 writel(0, ecc->base + JZ_REG_NAND_IRQ_STAT); in jz4740_ecc_reset()
53 reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
62 writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_reset()
65 static int jz4740_ecc_calculate(struct ingenic_ecc *ecc, in jz4740_ecc_calculate() argument
73 jz4740_ecc_reset(ecc, true); in jz4740_ecc_calculate()
76 status = readl(ecc->base + JZ_REG_NAND_IRQ_STAT); in jz4740_ecc_calculate()
82 reg = readl(ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_calculate()
84 writel(reg, ecc->base + JZ_REG_NAND_ECC_CTRL); in jz4740_ecc_calculate()
87 ecc_code[i] = readb(ecc->base + JZ_REG_NAND_PAR0 + i); in jz4740_ecc_calculate()
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H A Dingenic_ecc.h29 int ingenic_ecc_calculate(struct ingenic_ecc *ecc,
32 int ingenic_ecc_correct(struct ingenic_ecc *ecc,
36 void ingenic_ecc_release(struct ingenic_ecc *ecc);
39 static inline int ingenic_ecc_calculate(struct ingenic_ecc *ecc, in ingenic_ecc_calculate() argument
46 static inline int ingenic_ecc_correct(struct ingenic_ecc *ecc, in ingenic_ecc_correct() argument
53 static inline void ingenic_ecc_release(struct ingenic_ecc *ecc) in ingenic_ecc_release() argument
64 void (*disable)(struct ingenic_ecc *ecc);
65 int (*calculate)(struct ingenic_ecc *ecc,
68 int (*correct)(struct ingenic_ecc *ecc,
/linux/drivers/dma/ti/
H A Dedma.c219 struct edma_cc *ecc; member
300 static inline unsigned int edma_read(struct edma_cc *ecc, int offset) in edma_read() argument
302 return (unsigned int)__raw_readl(ecc->base + offset); in edma_read()
305 static inline void edma_write(struct edma_cc *ecc, int offset, int val) in edma_write() argument
307 __raw_writel(val, ecc->base + offset); in edma_write()
310 static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and, in edma_modify() argument
313 unsigned val = edma_read(ecc, offset); in edma_modify()
317 edma_write(ecc, offset, val); in edma_modify()
320 static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or) in edma_or() argument
322 unsigned val = edma_read(ecc, offset); in edma_or()
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/linux/drivers/mtd/nand/raw/
H A Dnand_base.c262 res = chip->ecc.read_oob(chip, first_page + page_offset); in nand_block_bad()
479 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask); in nand_do_write_oob()
481 status = chip->ecc.write_oob(chip, page & chip->pagemask); in nand_do_write_oob()
2885 int eccsize = chip->ecc.size; in nand_read_page_raw_syndrome()
2886 int eccbytes = chip->ecc.bytes; in nand_read_page_raw_syndrome()
2894 for (steps = chip->ecc.steps; steps > 0; steps--) { in nand_read_page_raw_syndrome()
2901 if (chip->ecc.prepad) { in nand_read_page_raw_syndrome()
2902 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, in nand_read_page_raw_syndrome()
2907 oob += chip->ecc.prepad; in nand_read_page_raw_syndrome()
2916 if (chip->ecc.postpad) { in nand_read_page_raw_syndrome()
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H A Dnand_micron.c66 struct micron_on_die_ecc ecc; member
127 .ecc = micron_nand_on_die_4_ooblayout_ecc,
140 oobregion->offset = mtd->oobsize - chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
141 oobregion->length = chip->ecc.total; in micron_nand_on_die_8_ooblayout_ecc()
156 oobregion->length = mtd->oobsize - chip->ecc.total - 2; in micron_nand_on_die_8_ooblayout_free()
162 .ecc = micron_nand_on_die_8_ooblayout_ecc,
172 if (micron->ecc.forced) in micron_nand_on_die_ecc_setup()
175 if (micron->ecc.enabled == enable) in micron_nand_on_die_ecc_setup()
183 micron->ecc.enabled = enable; in micron_nand_on_die_ecc_setup()
242 ret = nand_read_page_op(chip, page, 0, micron->ecc.rawbuf, in micron_nand_on_die_ecc_status_4()
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H A Dqcom_nandc.c147 static bool qcom_nandc_is_last_cw(struct nand_ecc_ctrl *ecc, int cw) in qcom_nandc_is_last_cw() argument
149 return cw == (ecc->steps - 1); in qcom_nandc_is_last_cw()
221 struct nand_ecc_ctrl *ecc = &chip->ecc; in nandc_set_read_loc() local
224 if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
229 if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
330 struct nand_ecc_ctrl *ecc = &chip->ecc; in config_nand_cw_read() local
334 if (nandc->props->qpic_version2 && qcom_nandc_is_last_cw(ecc, cw)) in config_nand_cw_read()
477 struct nand_ecc_ctrl *ecc = &chip->ecc; in qcom_nandc_read_cw_raw() local
489 raw_cw = ecc->steps - 1; in qcom_nandc_read_cw_raw()
496 data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); in qcom_nandc_read_cw_raw()
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H A Dmtk_nand.c146 struct mtk_ecc *ecc; member
185 return (u8 *)p + i * chip->ecc.size; in data_ptr()
211 return chip->ecc.size + mtk_nand->spare_per_sector; in mtk_data_len()
225 return nfc->buffer + i * mtk_data_len(chip) + chip->ecc.size; in mtk_oob_ptr()
335 if (chip->ecc.size == 512) in mtk_nfc_hw_runtime_config()
341 if (chip->ecc.size == 512) in mtk_nfc_hw_runtime_config()
347 if (chip->ecc.size == 512) in mtk_nfc_hw_runtime_config()
364 if (chip->ecc.size == 1024) in mtk_nfc_hw_runtime_config()
383 nfc->ecc_cfg.strength = chip->ecc.strength; in mtk_nfc_hw_runtime_config()
384 nfc->ecc_cfg.len = chip->ecc.size + mtk_nand->fdm.ecc_size; in mtk_nfc_hw_runtime_config()
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H A Dnuvoton-ma35d1-nand-controller.c121 oob_region->length = chip->ecc.total; in ma35_ooblayout_ecc()
135 oob_region->length = mtd->oobsize - chip->ecc.total - 2; in ma35_ooblayout_free()
143 .ecc = ma35_ooblayout_ecc,
253 if (chip->ecc.strength != 0) { in ma35_nand_hwecc_init()
254 chip->ecc.steps = mtd->writesize / chip->ecc.size; in ma35_nand_hwecc_init()
255 nvtnand->eccstatus = (chip->ecc.steps < 4) ? 1 : chip->ecc.steps / 4; in ma35_nand_hwecc_init()
258 switch (chip->ecc.strength) { in ma35_nand_hwecc_init()
260 chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH8; in ma35_nand_hwecc_init()
264 chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH12; in ma35_nand_hwecc_init()
268 chip->ecc.total = chip->ecc.steps * MA35_PARITY_BCH24; in ma35_nand_hwecc_init()
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H A Dstm32_fmc2_nand.c329 if (chip->ecc.strength == FMC2_ECC_BCH8) { in stm32_fmc2_nfc_setup()
332 } else if (chip->ecc.strength == FMC2_ECC_BCH4) { in stm32_fmc2_nfc_setup()
397 dma_cfg.src_addr += chip->ecc.strength == FMC2_ECC_HAM ? in stm32_fmc2_nfc_select_chip()
408 nfc->dma_ecc_len = chip->ecc.strength == FMC2_ECC_HAM ? in stm32_fmc2_nfc_select_chip()
486 if (chip->ecc.strength != FMC2_ECC_HAM) { in stm32_fmc2_nfc_hwctl()
503 static void stm32_fmc2_nfc_ham_set_ecc(const u32 ecc_sta, u8 *ecc) in stm32_fmc2_nfc_ham_set_ecc() argument
505 ecc[0] = ecc_sta; in stm32_fmc2_nfc_ham_set_ecc()
506 ecc[1] = ecc_sta >> 8; in stm32_fmc2_nfc_ham_set_ecc()
507 ecc[2] = ecc_sta >> 16; in stm32_fmc2_nfc_ham_set_ecc()
511 u8 *ecc) in stm32_fmc2_nfc_ham_calculate() argument
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H A Dtegra_nand.c185 struct mtd_oob_region ecc; member
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
214 oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_ooblayout_rs_ecc()
226 .ecc = tegra_nand_ooblayout_rs_ecc,
234 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_BCH * chip->ecc.strength, in tegra_nand_ooblayout_bch_ecc()
241 oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4); in tegra_nand_ooblayout_bch_ecc()
247 .ecc = tegra_nand_ooblayout_bch_ecc,
485 if (chip->ecc.algo == NAND_ECC_ALGO_BCH && enable) in tegra_nand_hw_ecc()
710 if (fail_sec_flag ^ GENMASK(chip->ecc.steps - 1, 0)) { in tegra_nand_read_page_hwecc()
726 for_each_set_bit(bit, &fail_sec_flag, chip->ecc.steps) { in tegra_nand_read_page_hwecc()
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H A Dnand_toshiba.c40 NAND_OP_8BIT_DATA_IN(chip->ecc.steps, ecc_status, 0), in toshiba_nand_benand_read_eccstatus_op()
62 for (i = 0; i < chip->ecc.steps; i++) { in toshiba_nand_benand_eccstatus()
132 chip->ecc.bytes = 0; in toshiba_nand_benand_init()
133 chip->ecc.size = 512; in toshiba_nand_benand_init()
134 chip->ecc.strength = 8; in toshiba_nand_benand_init()
135 chip->ecc.read_page = toshiba_nand_read_page_benand; in toshiba_nand_benand_init()
136 chip->ecc.read_subpage = toshiba_nand_read_subpage_benand; in toshiba_nand_benand_init()
137 chip->ecc.write_page = nand_write_page_raw; in toshiba_nand_benand_init()
138 chip->ecc.read_page_raw = nand_read_page_raw_notsupp; in toshiba_nand_benand_init()
139 chip->ecc.write_page_raw = nand_write_page_raw_notsupp; in toshiba_nand_benand_init()
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H A Ddenali.c210 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength), in denali_select_target()
212 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE); in denali_select_target()
213 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE); in denali_select_target()
214 iowrite32(chip->ecc.steps, denali->reg + CFG_NUM_DATA_BLOCKS); in denali_select_target()
246 struct nand_ecc_ctrl *ecc = &chip->ecc; in denali_payload_xfer() local
251 for (i = 0; i < ecc->steps; i++) { in denali_payload_xfer()
252 pos = i * (ecc->size + ecc->bytes); in denali_payload_xfer()
253 len = ecc->size; in denali_payload_xfer()
283 struct nand_ecc_ctrl *ecc = &chip->ecc; in denali_oob_xfer() local
296 for (i = 0; i < ecc->steps; i++) { in denali_oob_xfer()
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H A Dmeson_nand.c340 pagesize = nand->ecc.size >> 3; in meson_nfc_cmd_access()
341 pages = len / nand->ecc.size; in meson_nfc_cmd_access()
398 len = nand->ecc.size * (i + 1) + (nand->ecc.bytes + 2) * i; in meson_nfc_oob_ptr()
408 temp = nand->ecc.size + nand->ecc.bytes; in meson_nfc_data_ptr()
420 oob_len = nand->ecc.bytes + 2; in meson_nfc_get_data_oob()
421 for (i = 0; i < nand->ecc.steps; i++) { in meson_nfc_get_data_oob()
424 memcpy(buf, dsrc, nand->ecc.size); in meson_nfc_get_data_oob()
425 buf += nand->ecc.size; in meson_nfc_get_data_oob()
439 oob_len = nand->ecc.bytes + 2; in meson_nfc_set_data_oob()
440 for (i = 0; i < nand->ecc.steps; i++) { in meson_nfc_set_data_oob()
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H A Dndfc.c91 uint32_t ecc; in ndfc_calculate_ecc() local
92 uint8_t *p = (uint8_t *)&ecc; in ndfc_calculate_ecc()
95 ecc = in_be32(ndfc->ndfcbase + NDFC_ECC); in ndfc_calculate_ecc()
149 chip->ecc.correct = rawnand_sw_hamming_correct; in ndfc_chip_init()
150 chip->ecc.hwctl = ndfc_enable_hwecc; in ndfc_chip_init()
151 chip->ecc.calculate = ndfc_calculate_ecc; in ndfc_chip_init()
152 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in ndfc_chip_init()
153 chip->ecc.size = 256; in ndfc_chip_init()
154 chip->ecc.bytes = 3; in ndfc_chip_init()
155 chip->ecc.strength = 1; in ndfc_chip_init()
H A Domap_elm.c165 struct elm_errorvec *err_vec, u8 *ecc) in elm_load_syndrome() argument
180 val = (__force u32)cpu_to_be32(*(u32 *)&ecc[9]); in elm_load_syndrome()
185 val = (__force u32)cpu_to_be32(*(u32 *)&ecc[5]); in elm_load_syndrome()
190 val = (__force u32)cpu_to_be32(*(u32 *)&ecc[1]); in elm_load_syndrome()
195 val = ecc[0]; in elm_load_syndrome()
200 val = ((__force u32)cpu_to_be32(*(u32 *)&ecc[3]) >> 4) | in elm_load_syndrome()
201 ((ecc[2] & 0xf) << 28); in elm_load_syndrome()
206 val = (__force u32)cpu_to_be32(*(u32 *)&ecc[0]) >> 12; in elm_load_syndrome()
210 val = (__force u32)cpu_to_be32(*(u32 *)&ecc[22]); in elm_load_syndrome()
213 val = (__force u32)cpu_to_be32(*(u32 *)&ecc[18]); in elm_load_syndrome()
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/linux/Documentation/devicetree/bindings/mtd/
H A Dhisi504-nand.txt11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
H A Dnvidia-tegra20-nand.txt25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
31 - nand-ecc-strength: integer representing the number of bits to correct
36 - nand-ecc-maximize: See nand-controller.yaml
60 nand-ecc-algo = "bch";
61 nand-ecc-strength = <8>;
/linux/fs/ocfs2/
H A Dblockcheck.c353 u32 ecc; in ocfs2_block_check_compute() local
358 ecc = ocfs2_hamming_encode_block(data, blocksize); in ocfs2_block_check_compute()
364 BUG_ON(ecc > USHRT_MAX); in ocfs2_block_check_compute()
367 bc->bc_ecc = cpu_to_le16((u16)ecc); in ocfs2_block_check_compute()
385 u32 crc, ecc; in ocfs2_block_check_validate() local
405 ecc = ocfs2_hamming_encode_block(data, blocksize); in ocfs2_block_check_validate()
406 ocfs2_hamming_fix_block(data, blocksize, ecc ^ bc_ecc); in ocfs2_block_check_validate()
445 u32 crc, ecc; in ocfs2_block_check_compute_bhs() local
454 for (i = 0, crc = ~0, ecc = 0; i < nr; i++) { in ocfs2_block_check_compute_bhs()
461 ecc = (u16)ocfs2_hamming_encode(ecc, bhs[i]->b_data, in ocfs2_block_check_compute_bhs()
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/linux/arch/arm64/boot/dts/altera/
H A Dsocfpga_stratix10.dtsi351 clock-names = "nand", "nand_x", "ecc";
522 reset-names = "dwc2", "dwc2-ecc";
536 reset-names = "dwc2", "dwc2-ecc";
585 compatible = "altr,socfpga-s10-ecc-manager",
586 "altr,socfpga-a10-ecc-manager";
601 ocram-ecc@ff8cc000 {
602 compatible = "altr,socfpga-s10-ocram-ecc",
603 "altr,socfpga-a10-ocram-ecc";
605 altr,ecc-parent = <&ocram>;
609 usb0-ecc@ff8c4000 {
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/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex.dtsi350 clock-names = "nand", "nand_x", "ecc";
551 reset-names = "dwc2", "dwc2-ecc";
565 reset-names = "dwc2", "dwc2-ecc";
613 compatible = "altr,socfpga-s10-ecc-manager",
614 "altr,socfpga-a10-ecc-manager";
629 ocram-ecc@ff8cc000 {
630 compatible = "altr,socfpga-s10-ocram-ecc",
631 "altr,socfpga-a10-ocram-ecc";
633 altr,ecc-parent = <&ocram>;
637 usb0-ecc@ff8c4000 {
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