1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Microsemi Switchtec PCIe Driver
4 * Copyright (c) 2017, Microsemi Corporation
5 */
6
7 #ifndef _SWITCHTEC_H
8 #define _SWITCHTEC_H
9
10 #include <linux/pci.h>
11 #include <linux/cdev.h>
12
13 #define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
14 #define SWITCHTEC_MAX_PFF_CSR 255
15
16 #define SWITCHTEC_EVENT_OCCURRED BIT(0)
17 #define SWITCHTEC_EVENT_CLEAR BIT(0)
18 #define SWITCHTEC_EVENT_EN_LOG BIT(1)
19 #define SWITCHTEC_EVENT_EN_CLI BIT(2)
20 #define SWITCHTEC_EVENT_EN_IRQ BIT(3)
21 #define SWITCHTEC_EVENT_FATAL BIT(4)
22 #define SWITCHTEC_EVENT_NOT_SUPP BIT(31)
23
24 #define SWITCHTEC_DMA_MRPC_EN BIT(0)
25
26 #define MRPC_GAS_READ 0x29
27 #define MRPC_GAS_WRITE 0x87
28 #define MRPC_CMD_ID(x) ((x) & 0xffff)
29
30 enum {
31 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
32 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
33 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
34 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
35 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
36 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
37 SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
38 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
39 };
40
41 enum switchtec_gen {
42 SWITCHTEC_GEN3,
43 SWITCHTEC_GEN4,
44 SWITCHTEC_GEN5,
45 SWITCHTEC_GEN6,
46 };
47
48 struct mrpc_regs {
49 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
50 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
51 u32 cmd;
52 u32 status;
53 u32 ret_value;
54 u32 dma_en;
55 u64 dma_addr;
56 u32 dma_vector;
57 u32 dma_ver;
58 } __packed;
59
60 enum mrpc_status {
61 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
62 SWITCHTEC_MRPC_STATUS_DONE = 2,
63 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
64 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
65 };
66
67 struct sw_event_regs {
68 u64 event_report_ctrl;
69 u64 reserved1;
70 u64 part_event_bitmap;
71 u64 reserved2;
72 u32 global_summary;
73 u32 reserved3[3];
74 u32 stack_error_event_hdr;
75 u32 stack_error_event_data;
76 u32 reserved4[4];
77 u32 ppu_error_event_hdr;
78 u32 ppu_error_event_data;
79 u32 reserved5[4];
80 u32 isp_error_event_hdr;
81 u32 isp_error_event_data;
82 u32 reserved6[4];
83 u32 sys_reset_event_hdr;
84 u32 reserved7[5];
85 u32 fw_exception_hdr;
86 u32 reserved8[5];
87 u32 fw_nmi_hdr;
88 u32 reserved9[5];
89 u32 fw_non_fatal_hdr;
90 u32 reserved10[5];
91 u32 fw_fatal_hdr;
92 u32 reserved11[5];
93 u32 twi_mrpc_comp_hdr;
94 u32 twi_mrpc_comp_data;
95 u32 reserved12[4];
96 u32 twi_mrpc_comp_async_hdr;
97 u32 twi_mrpc_comp_async_data;
98 u32 reserved13[4];
99 u32 cli_mrpc_comp_hdr;
100 u32 cli_mrpc_comp_data;
101 u32 reserved14[4];
102 u32 cli_mrpc_comp_async_hdr;
103 u32 cli_mrpc_comp_async_data;
104 u32 reserved15[4];
105 u32 gpio_interrupt_hdr;
106 u32 gpio_interrupt_data;
107 u32 reserved16[4];
108 u32 gfms_event_hdr;
109 u32 gfms_event_data;
110 u32 reserved17[4];
111 } __packed;
112
113 enum {
114 SWITCHTEC_GEN3_CFG0_RUNNING = 0x04,
115 SWITCHTEC_GEN3_CFG1_RUNNING = 0x05,
116 SWITCHTEC_GEN3_IMG0_RUNNING = 0x03,
117 SWITCHTEC_GEN3_IMG1_RUNNING = 0x07,
118 };
119
120 enum {
121 SWITCHTEC_GEN4_MAP0_RUNNING = 0x00,
122 SWITCHTEC_GEN4_MAP1_RUNNING = 0x01,
123 SWITCHTEC_GEN4_KEY0_RUNNING = 0x02,
124 SWITCHTEC_GEN4_KEY1_RUNNING = 0x03,
125 SWITCHTEC_GEN4_BL2_0_RUNNING = 0x04,
126 SWITCHTEC_GEN4_BL2_1_RUNNING = 0x05,
127 SWITCHTEC_GEN4_CFG0_RUNNING = 0x06,
128 SWITCHTEC_GEN4_CFG1_RUNNING = 0x07,
129 SWITCHTEC_GEN4_IMG0_RUNNING = 0x08,
130 SWITCHTEC_GEN4_IMG1_RUNNING = 0x09,
131 };
132
133 enum {
134 SWITCHTEC_GEN4_KEY0_ACTIVE = 0,
135 SWITCHTEC_GEN4_KEY1_ACTIVE = 1,
136 SWITCHTEC_GEN4_BL2_0_ACTIVE = 0,
137 SWITCHTEC_GEN4_BL2_1_ACTIVE = 1,
138 SWITCHTEC_GEN4_CFG0_ACTIVE = 0,
139 SWITCHTEC_GEN4_CFG1_ACTIVE = 1,
140 SWITCHTEC_GEN4_IMG0_ACTIVE = 0,
141 SWITCHTEC_GEN4_IMG1_ACTIVE = 1,
142 };
143
144 struct sys_info_regs_gen3 {
145 u32 reserved1;
146 u32 vendor_table_revision;
147 u32 table_format_version;
148 u32 partition_id;
149 u32 cfg_file_fmt_version;
150 u16 cfg_running;
151 u16 img_running;
152 u32 reserved2[57];
153 char vendor_id[8];
154 char product_id[16];
155 char product_revision[4];
156 char component_vendor[8];
157 u16 component_id;
158 u8 component_revision;
159 } __packed;
160
161 struct sys_info_regs_gen4 {
162 u16 gas_layout_ver;
163 u8 evlist_ver;
164 u8 reserved1;
165 u16 mgmt_cmd_set_ver;
166 u16 fabric_cmd_set_ver;
167 u32 reserved2[2];
168 u8 mrpc_uart_ver;
169 u8 mrpc_twi_ver;
170 u8 mrpc_eth_ver;
171 u8 mrpc_inband_ver;
172 u32 reserved3[7];
173 u32 fw_update_tmo;
174 u32 xml_version_cfg;
175 u32 xml_version_img;
176 u32 partition_id;
177 u16 bl2_running;
178 u16 cfg_running;
179 u16 img_running;
180 u16 key_running;
181 u32 reserved4[43];
182 u32 vendor_seeprom_twi;
183 u32 vendor_table_revision;
184 u32 vendor_specific_info[2];
185 u16 p2p_vendor_id;
186 u16 p2p_device_id;
187 u8 p2p_revision_id;
188 u8 reserved5[3];
189 u32 p2p_class_id;
190 u16 subsystem_vendor_id;
191 u16 subsystem_id;
192 u32 p2p_serial_number[2];
193 u8 mac_addr[6];
194 u8 reserved6[2];
195 u32 reserved7[3];
196 char vendor_id[8];
197 char product_id[24];
198 char product_revision[2];
199 u16 reserved8;
200 } __packed;
201
202 struct sys_info_regs {
203 u32 device_id;
204 u32 device_version;
205 u32 firmware_version;
206 union {
207 struct sys_info_regs_gen3 gen3;
208 struct sys_info_regs_gen4 gen4;
209 };
210 } __packed;
211
212 struct partition_info {
213 u32 address;
214 u32 length;
215 };
216
217 struct flash_info_regs_gen3 {
218 u32 flash_part_map_upd_idx;
219
220 struct active_partition_info_gen3 {
221 u32 address;
222 u32 build_version;
223 u32 build_string;
224 } active_img;
225
226 struct active_partition_info_gen3 active_cfg;
227 struct active_partition_info_gen3 inactive_img;
228 struct active_partition_info_gen3 inactive_cfg;
229
230 u32 flash_length;
231
232 struct partition_info cfg0;
233 struct partition_info cfg1;
234 struct partition_info img0;
235 struct partition_info img1;
236 struct partition_info nvlog;
237 struct partition_info vendor[8];
238 };
239
240 struct flash_info_regs_gen4 {
241 u32 flash_address;
242 u32 flash_length;
243
244 struct active_partition_info_gen4 {
245 unsigned char bl2;
246 unsigned char cfg;
247 unsigned char img;
248 unsigned char key;
249 } active_flag;
250
251 u32 reserved[3];
252
253 struct partition_info map0;
254 struct partition_info map1;
255 struct partition_info key0;
256 struct partition_info key1;
257 struct partition_info bl2_0;
258 struct partition_info bl2_1;
259 struct partition_info cfg0;
260 struct partition_info cfg1;
261 struct partition_info img0;
262 struct partition_info img1;
263 struct partition_info nvlog;
264 struct partition_info vendor[8];
265 };
266
267 struct flash_info_regs {
268 union {
269 struct flash_info_regs_gen3 gen3;
270 struct flash_info_regs_gen4 gen4;
271 };
272 };
273
274 enum {
275 SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
276 SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
277 SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
278 };
279
280 struct ntb_info_regs {
281 u8 partition_count;
282 u8 partition_id;
283 u16 reserved1;
284 u64 ep_map;
285 u16 requester_id;
286 u16 reserved2;
287 u32 reserved3[4];
288 struct nt_partition_info {
289 u32 xlink_enabled;
290 u32 target_part_low;
291 u32 target_part_high;
292 u32 reserved;
293 } ntp_info[48];
294 } __packed;
295
296 struct part_cfg_regs {
297 u32 status;
298 u32 state;
299 u32 port_cnt;
300 u32 usp_port_mode;
301 u32 usp_pff_inst_id;
302 u32 vep_pff_inst_id;
303 u32 dsp_pff_inst_id[47];
304 u32 reserved1[11];
305 u16 vep_vector_number;
306 u16 usp_vector_number;
307 u32 port_event_bitmap;
308 u32 reserved2[3];
309 u32 part_event_summary;
310 u32 reserved3[3];
311 u32 part_reset_hdr;
312 u32 part_reset_data[5];
313 u32 mrpc_comp_hdr;
314 u32 mrpc_comp_data[5];
315 u32 mrpc_comp_async_hdr;
316 u32 mrpc_comp_async_data[5];
317 u32 dyn_binding_hdr;
318 u32 dyn_binding_data[5];
319 u32 intercomm_notify_hdr;
320 u32 intercomm_notify_data[5];
321 u32 reserved4[153];
322 } __packed;
323
324 enum {
325 NTB_CTRL_PART_OP_LOCK = 0x1,
326 NTB_CTRL_PART_OP_CFG = 0x2,
327 NTB_CTRL_PART_OP_RESET = 0x3,
328
329 NTB_CTRL_PART_STATUS_NORMAL = 0x1,
330 NTB_CTRL_PART_STATUS_LOCKED = 0x2,
331 NTB_CTRL_PART_STATUS_LOCKING = 0x3,
332 NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
333 NTB_CTRL_PART_STATUS_RESETTING = 0x5,
334
335 NTB_CTRL_BAR_VALID = 1 << 0,
336 NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
337 NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
338
339 NTB_CTRL_REQ_ID_EN = 1 << 0,
340
341 NTB_CTRL_LUT_EN = 1 << 0,
342 };
343
344 struct ntb_ctrl_regs {
345 u32 partition_status;
346 u32 partition_op;
347 u32 partition_ctrl;
348 u32 bar_setup;
349 u32 bar_error;
350 u16 lut_table_entries;
351 u16 lut_table_offset;
352 u32 lut_error;
353 u16 req_id_table_size;
354 u16 req_id_table_offset;
355 u32 req_id_error;
356 u32 reserved1[7];
357 struct {
358 u32 ctl;
359 u32 win_size;
360 u64 xlate_addr;
361 } bar_entry[6];
362 struct {
363 u32 win_size;
364 u32 reserved[3];
365 } bar_ext_entry[6];
366 u32 reserved2[192];
367 u32 req_id_table[512];
368 u32 reserved3[256];
369 u64 lut_entry[512];
370 } __packed;
371
372 #define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
373 #define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
374
375 struct ntb_dbmsg_regs {
376 u32 reserved1[1024];
377 u64 odb;
378 u64 odb_mask;
379 u64 idb;
380 u64 idb_mask;
381 u8 idb_vec_map[64];
382 u32 msg_map;
383 u32 reserved2;
384 struct {
385 u32 msg;
386 u32 status;
387 } omsg[4];
388
389 struct {
390 u32 msg;
391 u8 status;
392 u8 mask;
393 u8 src;
394 u8 reserved;
395 } imsg[4];
396
397 u8 reserved3[3928];
398 u8 msix_table[1024];
399 u8 reserved4[3072];
400 u8 pba[24];
401 u8 reserved5[4072];
402 } __packed;
403
404 enum {
405 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
406 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
407 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
408 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
409 };
410
411 struct pff_csr_regs {
412 u16 vendor_id;
413 u16 device_id;
414 u16 pcicmd;
415 u16 pcists;
416 u32 pci_class;
417 u32 pci_opts;
418 union {
419 u32 pci_bar[6];
420 u64 pci_bar64[3];
421 };
422 u32 pci_cardbus;
423 u32 pci_subsystem_id;
424 u32 pci_expansion_rom;
425 u32 pci_cap_ptr;
426 u32 reserved1;
427 u32 pci_irq;
428 u32 pci_cap_region[48];
429 u32 pcie_cap_region[448];
430 u32 indirect_gas_window[128];
431 u32 indirect_gas_window_off;
432 u32 reserved[127];
433 u32 pff_event_summary;
434 u32 reserved2[3];
435 u32 aer_in_p2p_hdr;
436 u32 aer_in_p2p_data[5];
437 u32 aer_in_vep_hdr;
438 u32 aer_in_vep_data[5];
439 u32 dpc_hdr;
440 u32 dpc_data[5];
441 u32 cts_hdr;
442 u32 cts_data[5];
443 u32 uec_hdr;
444 u32 uec_data[5];
445 u32 hotplug_hdr;
446 u32 hotplug_data[5];
447 u32 ier_hdr;
448 u32 ier_data[5];
449 u32 threshold_hdr;
450 u32 threshold_data[5];
451 u32 power_mgmt_hdr;
452 u32 power_mgmt_data[5];
453 u32 tlp_throttling_hdr;
454 u32 tlp_throttling_data[5];
455 u32 force_speed_hdr;
456 u32 force_speed_data[5];
457 u32 credit_timeout_hdr;
458 u32 credit_timeout_data[5];
459 u32 link_state_hdr;
460 u32 link_state_data[5];
461 u32 reserved4[174];
462 } __packed;
463
464 struct switchtec_ntb;
465
466 struct dma_mrpc_output {
467 u32 status;
468 u32 cmd_id;
469 u32 rtn_code;
470 u32 output_size;
471 u8 data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
472 };
473
474 struct switchtec_dev {
475 struct pci_dev *pdev;
476 struct device dev;
477 struct cdev cdev;
478
479 enum switchtec_gen gen;
480
481 int partition;
482 int partition_count;
483 int pff_csr_count;
484 char pff_local[SWITCHTEC_MAX_PFF_CSR];
485
486 void __iomem *mmio;
487 struct mrpc_regs __iomem *mmio_mrpc;
488 struct sw_event_regs __iomem *mmio_sw_event;
489 struct sys_info_regs __iomem *mmio_sys_info;
490 struct flash_info_regs __iomem *mmio_flash_info;
491 struct ntb_info_regs __iomem *mmio_ntb;
492 struct part_cfg_regs __iomem *mmio_part_cfg;
493 struct part_cfg_regs __iomem *mmio_part_cfg_all;
494 struct pff_csr_regs __iomem *mmio_pff_csr;
495
496 /*
497 * The mrpc mutex must be held when accessing the other
498 * mrpc_ fields, alive flag and stuser->state field
499 */
500 struct mutex mrpc_mutex;
501 struct list_head mrpc_queue;
502 int mrpc_busy;
503 struct work_struct mrpc_work;
504 struct delayed_work mrpc_timeout;
505 bool alive;
506
507 wait_queue_head_t event_wq;
508 atomic_t event_cnt;
509
510 struct work_struct link_event_work;
511 void (*link_notifier)(struct switchtec_dev *stdev);
512 u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
513
514 struct switchtec_ntb *sndev;
515
516 struct dma_mrpc_output *dma_mrpc;
517 dma_addr_t dma_mrpc_dma_addr;
518 };
519
to_stdev(struct device * dev)520 static inline struct switchtec_dev *to_stdev(struct device *dev)
521 {
522 return container_of(dev, struct switchtec_dev, dev);
523 }
524
525 extern const struct class switchtec_class;
526
527 #endif
528