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Searched refs:dwbc (Results 1 – 25 of 28) sorted by relevance

12

/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddwb.h156 struct dwbc { struct
177 struct dwbc *dwbc, argument
181 struct dwbc *dwbc,
184 bool (*disable)(struct dwbc *dwbc);
187 struct dwbc *dwbc,
191 struct dwbc *dwbc);
194 struct dwbc *dwbc,
198 struct dwbc *dwbc,
202 struct dwbc *dwbc,
206 struct dwbc *dwbc,
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/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb.c46 static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb3_get_caps() argument
66 void dwb3_config_fc(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb3_config_fc() argument
68 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_config_fc()
88 dwb3_set_stereo(dwbc, &params->stereo_params); in dwb3_config_fc()
91 bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb3_enable() argument
93 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_enable()
94 DC_LOG_DWB("%s dwb3_enabled at inst = %d", __func__, dwbc->inst); in dwb3_enable()
100 dwb3_config_fc(dwbc, params); in dwb3_enable()
103 dwb3_program_hdr_mult(dwbc, params); in dwb3_enable()
104 dwb3_set_gamut_remap(dwbc, params); in dwb3_enable()
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H A Ddcn30_dwb_cm.c273 struct dwbc *dwbc, in dwb3_ogam_set_input_transfer_func() argument
276 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_ogam_set_input_transfer_func()
286 cm_helper_translate_curve_to_hw_format(dwbc->ctx, in dwb3_ogam_set_input_transfer_func()
301 struct dwbc *dwbc, in dwb3_program_gamut_remap() argument
306 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_program_gamut_remap()
356 struct dwbc *dwbc, in dwb3_set_gamut_remap() argument
359 struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc); in dwb3_set_gamut_remap()
365 dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS); in dwb3_set_gamut_remap()
379 dwb3_program_gamut_remap(dwbc, arr_reg_val, in dwb3_set_gamut_remap()
382 dwb3_program_gamut_remap(dwbc, arr_reg_val, in dwb3_set_gamut_remap()
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H A Ddcn30_dwb.h871 struct dwbc base;
884 bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);
886 bool dwb3_disable(struct dwbc *dwbc);
888 bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);
890 bool dwb3_is_enabled(struct dwbc *dwbc);
892 void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable);
894 void dwb3_set_stereo(struct dwbc *dwbc,
897 void dwb3_set_new_content(struct dwbc *dwbc,
900 void dwb3_config_fc(struct dwbc *dwbc,
903 void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params);
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/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c50 static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb2_get_caps() argument
52 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_get_caps()
72 void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_config_dwb_cnv() argument
74 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_config_dwb_cnv()
99 static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_enable() argument
101 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_enable()
121 dwb2_config_dwb_cnv(dwbc, params); in dwb2_enable()
124 dwb2_set_scaler(dwbc, params); in dwb2_enable()
135 bool dwb2_disable(struct dwbc *dwbc) in dwb2_disable() argument
137 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_disable()
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H A Ddcn20_dwb.h389 struct dwbc base;
402 bool dwb2_disable(struct dwbc *dwbc);
404 bool dwb2_is_enabled(struct dwbc *dwbc);
406 void dwb2_set_stereo(struct dwbc *dwbc,
409 void dwb2_set_new_content(struct dwbc *dwbc,
412 void dwb2_config_dwb_cnv(struct dwbc *dwbc,
415 void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.c45 static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb1_get_caps() argument
64 static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb1_enable() argument
66 struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); in dwb1_enable()
69 dwbc->funcs->disable(dwbc); in dwb1_enable()
81 static bool dwb1_disable(struct dwbc *dwbc) in dwb1_disable() argument
83 struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); in dwb1_disable()
H A Ddcn10_dwb.h254 struct dwbc base;
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_stream.c457 struct dwbc *dwb; in dc_stream_add_writeback()
478 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
499 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
511 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
529 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_fc_disable_writeback()
601 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_remove_writeback()
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h248 struct dwbc *dwbc[MAX_DWB_PIPES]; member
471 struct dwbc *dwbc; member
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c444 struct dwbc *dwb; in dcn30_update_writeback()
445 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
461 struct dwbc *dwb; in dcn30_mmhubbub_warmup()
467 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
518 struct dwbc *dwb; in dcn30_enable_writeback()
521 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_enable_writeback()
544 struct dwbc *dwb; in dcn30_disable_writeback()
548 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dcn30_disable_writeback()
567 struct dwbc *dwb; in dcn30_program_all_writeback_pipes_in_tree()
612 dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst]; in dcn30_program_all_writeback_pipes_in_tree()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c722 pool->dwbc[i] = &dwbc30->base; in dcn302_dwbc_create()
1062 if (pool->dwbc[i] != NULL) { in dcn302_resource_destruct()
1063 kfree(TO_DCN30_DWBC(pool->dwbc[i])); in dcn302_resource_destruct()
1064 pool->dwbc[i] = NULL; in dcn302_resource_destruct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c684 pool->dwbc[i] = &dwbc30->base; in dcn303_dwbc_create()
1007 if (pool->dwbc[i] != NULL) { in dcn303_resource_destruct()
1008 kfree(TO_DCN30_DWBC(pool->dwbc[i])); in dcn303_resource_destruct()
1009 pool->dwbc[i] = NULL; in dcn303_resource_destruct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c1111 if (pool->base.dwbc[i] != NULL) { in dcn301_destruct()
1112 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn301_destruct()
1113 pool->base.dwbc[i] = NULL; in dcn301_destruct()
1195 pool->dwbc[i] = &dwbc30->base; in dcn301_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c1437 if (pool->base.dwbc[i] != NULL) { in dcn316_resource_destruct()
1438 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn316_resource_destruct()
1439 pool->base.dwbc[i] = NULL; in dcn316_resource_destruct()
1526 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1497 if (pool->base.dwbc[i] != NULL) { in dcn314_resource_destruct()
1498 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn314_resource_destruct()
1499 pool->base.dwbc[i] = NULL; in dcn314_resource_destruct()
1589 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c719 if (pool->base.dwbc[i] != NULL) { in dcn21_resource_destruct()
720 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); in dcn21_resource_destruct()
721 pool->base.dwbc[i] = NULL; in dcn21_resource_destruct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c1441 if (pool->base.dwbc[i] != NULL) { in dcn31_resource_destruct()
1442 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn31_resource_destruct()
1443 pool->base.dwbc[i] = NULL; in dcn31_resource_destruct()
1533 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c1427 if (pool->base.dwbc[i] != NULL) { in dcn321_resource_destruct()
1428 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn321_resource_destruct()
1429 pool->base.dwbc[i] = NULL; in dcn321_resource_destruct()
1508 pool->dwbc[i] = &dwbc30->base; in dcn321_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c1510 if (pool->base.dwbc[i] != NULL) { in dcn35_resource_destruct()
1511 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn35_resource_destruct()
1512 pool->base.dwbc[i] = NULL; in dcn35_resource_destruct()
1622 pool->dwbc[i] = &dwbc30->base; in dcn35_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c1490 if (pool->base.dwbc[i] != NULL) { in dcn351_resource_destruct()
1491 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn351_resource_destruct()
1492 pool->base.dwbc[i] = NULL; in dcn351_resource_destruct()
1602 pool->dwbc[i] = &dwbc30->base; in dcn35_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c1441 if (pool->base.dwbc[i] != NULL) { in dcn315_resource_destruct()
1442 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn315_resource_destruct()
1443 pool->base.dwbc[i] = NULL; in dcn315_resource_destruct()
1533 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c1453 if (pool->base.dwbc[i] != NULL) { in dcn401_resource_destruct()
1454 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn401_resource_destruct()
1455 pool->base.dwbc[i] = NULL; in dcn401_resource_destruct()
1535 pool->dwbc[i] = &dwbc401->base; in dcn401_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1140 if (pool->base.dwbc[i] != NULL) { in dcn30_resource_destruct()
1141 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn30_resource_destruct()
1142 pool->base.dwbc[i] = NULL; in dcn30_resource_destruct()
1235 pool->dwbc[i] = &dwbc30->base; in dcn30_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1149 if (pool->base.dwbc[i] != NULL) { in dcn20_resource_destruct()
1150 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); in dcn20_resource_destruct()
1151 pool->base.dwbc[i] = NULL; in dcn20_resource_destruct()
2254 pool->dwbc[i] = &dwbc20->base; in dcn20_dwbc_create()

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