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Searched refs:dwbc (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddwb.h156 struct dwbc { struct
177 struct dwbc *dwbc, argument
181 struct dwbc *dwbc,
184 bool (*disable)(struct dwbc *dwbc);
187 struct dwbc *dwbc,
191 struct dwbc *dwbc);
194 struct dwbc *dwbc,
198 struct dwbc *dwbc,
202 struct dwbc *dwbc,
206 struct dwbc *dwbc,
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/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c50 static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps) in dwb2_get_caps() argument
52 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_get_caps()
72 void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_config_dwb_cnv() argument
74 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_config_dwb_cnv()
99 static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params) in dwb2_enable() argument
101 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_enable()
121 dwb2_config_dwb_cnv(dwbc, params); in dwb2_enable()
124 dwb2_set_scaler(dwbc, params); in dwb2_enable()
135 bool dwb2_disable(struct dwbc *dwbc) in dwb2_disable() argument
137 struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc); in dwb2_disable()
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H A Ddcn20_dwb.h389 struct dwbc base;
402 bool dwb2_disable(struct dwbc *dwbc);
404 bool dwb2_is_enabled(struct dwbc *dwbc);
406 void dwb2_set_stereo(struct dwbc *dwbc,
409 void dwb2_set_new_content(struct dwbc *dwbc,
412 void dwb2_config_dwb_cnv(struct dwbc *dwbc,
415 void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb.h871 struct dwbc base;
884 bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);
886 bool dwb3_disable(struct dwbc *dwbc);
888 bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);
890 bool dwb3_is_enabled(struct dwbc *dwbc);
892 void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable);
894 void dwb3_set_stereo(struct dwbc *dwbc,
897 void dwb3_set_new_content(struct dwbc *dwbc,
900 void dwb3_config_fc(struct dwbc *dwbc,
903 void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params);
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c465 struct dwbc *dwb; in dcn30_update_writeback()
466 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
482 struct dwbc *dwb; in dcn30_mmhubbub_warmup()
488 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
539 struct dwbc *dwb; in dcn30_enable_writeback()
542 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_enable_writeback()
565 struct dwbc *dwb; in dcn30_disable_writeback()
569 dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dcn30_disable_writeback()
588 struct dwbc *dwb; in dcn30_program_all_writeback_pipes_in_tree()
635 dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst]; in dcn30_program_all_writeback_pipes_in_tree()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c805 pool->dwbc[i] = &dwbc30->base; in dcn303_dwbc_create()
1152 if (pool->dwbc[i] != NULL) { in dcn303_resource_destruct()
1153 kfree(TO_DCN30_DWBC(pool->dwbc[i])); in dcn303_resource_destruct()
1154 pool->dwbc[i] = NULL; in dcn303_resource_destruct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c844 pool->dwbc[i] = &dwbc30->base; in dcn302_dwbc_create()
1208 if (pool->dwbc[i] != NULL) { in dcn302_resource_destruct()
1209 kfree(TO_DCN30_DWBC(pool->dwbc[i])); in dcn302_resource_destruct()
1210 pool->dwbc[i] = NULL; in dcn302_resource_destruct()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h254 struct dwbc base;
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c1598 if (pool->base.dwbc[i] != NULL) { in dcn316_resource_destruct()
1599 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn316_resource_destruct()
1600 pool->base.dwbc[i] = NULL; in dcn316_resource_destruct()
1686 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c1662 if (pool->base.dwbc[i] != NULL) { in dcn314_resource_destruct()
1663 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn314_resource_destruct()
1664 pool->base.dwbc[i] = NULL; in dcn314_resource_destruct()
1753 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c1650 if (pool->base.dwbc[i] != NULL) { in dcn36_resource_destruct()
1651 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn36_resource_destruct()
1652 pool->base.dwbc[i] = NULL; in dcn36_resource_destruct()
1766 pool->dwbc[i] = &dwbc30->base; in dcn35_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c1603 if (pool->base.dwbc[i] != NULL) { in dcn31_resource_destruct()
1604 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn31_resource_destruct()
1605 pool->base.dwbc[i] = NULL; in dcn31_resource_destruct()
1694 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c1663 if (pool->base.dwbc[i] != NULL) { in dcn35_resource_destruct()
1664 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn35_resource_destruct()
1665 pool->base.dwbc[i] = NULL; in dcn35_resource_destruct()
1779 pool->dwbc[i] = &dwbc30->base; in dcn35_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c1605 if (pool->base.dwbc[i] != NULL) { in dcn315_resource_destruct()
1606 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn315_resource_destruct()
1607 pool->base.dwbc[i] = NULL; in dcn315_resource_destruct()
1696 pool->dwbc[i] = &dwbc30->base; in dcn31_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c1587 if (pool->base.dwbc[i] != NULL) { in dcn321_resource_destruct()
1588 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn321_resource_destruct()
1589 pool->base.dwbc[i] = NULL; in dcn321_resource_destruct()
1672 pool->dwbc[i] = &dwbc30->base; in dcn321_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c1643 if (pool->base.dwbc[i] != NULL) { in dcn351_resource_destruct()
1644 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn351_resource_destruct()
1645 pool->base.dwbc[i] = NULL; in dcn351_resource_destruct()
1759 pool->dwbc[i] = &dwbc30->base; in dcn35_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c1618 if (pool->base.dwbc[i] != NULL) { in dcn401_resource_destruct()
1619 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn401_resource_destruct()
1620 pool->base.dwbc[i] = NULL; in dcn401_resource_destruct()
1704 pool->dwbc[i] = &dwbc401->base; in dcn401_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn42/
H A Ddcn42_resource.c1597 if (pool->base.dwbc[i] != NULL) { in dcn42_resource_destruct()
1598 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn42_resource_destruct()
1599 pool->base.dwbc[i] = NULL; in dcn42_resource_destruct()
1745 pool->dwbc[i] = &dwbc42->base; in dcn42_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/
H A Ddcn42b_resource.c1588 if (pool->base.dwbc[i] != NULL) { in dcn42b_resource_destruct()
1589 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn42b_resource_destruct()
1590 pool->base.dwbc[i] = NULL; in dcn42b_resource_destruct()
1734 pool->dwbc[i] = &dwbc42->base; in dcn42b_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1301 if (pool->base.dwbc[i] != NULL) { in dcn30_resource_destruct()
1302 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn30_resource_destruct()
1303 pool->base.dwbc[i] = NULL; in dcn30_resource_destruct()
1395 pool->dwbc[i] = &dwbc30->base; in dcn30_dwbc_create()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c1613 if (pool->base.dwbc[i] != NULL) { in dcn32_resource_destruct()
1614 kfree(TO_DCN30_DWBC(pool->base.dwbc[i])); in dcn32_resource_destruct()
1615 pool->base.dwbc[i] = NULL; in dcn32_resource_destruct()
1698 pool->dwbc[i] = &dwbc30->base; in dcn32_dwbc_create()