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Searched refs:dw0 (Results 1 – 23 of 23) sorted by relevance

/linux/tools/perf/util/hisi-ptt-decoder/
H A Dhisi-ptt-pkt-decoder.c125 union hisi_ptt_4dw dw0; in hisi_ptt_4dw_print_dw0() local
128 dw0.value = *(uint32_t *)(buf + pos); in hisi_ptt_4dw_print_dw0()
138 "Format", dw0.format, "Type", dw0.type, "T9", dw0.t9, in hisi_ptt_4dw_print_dw0()
139 "T8", dw0.t8, "TH", dw0.th, "SO", dw0.so, "Length", in hisi_ptt_4dw_print_dw0()
140 dw0.len, "Time", dw0.time); in hisi_ptt_4dw_print_dw0()
/linux/drivers/iommu/intel/
H A Dtrace.h60 u64 dw0, u64 dw1, u64 dw2, u64 dw3,
63 TP_ARGS(iommu, dev, dw0, dw1, dw2, dw3, seq),
66 __field(u64, dw0)
77 __entry->dw0 = dw0;
88 decode_prq_descriptor(__get_str(buff), MSG_MAX, __entry->dw0,
/linux/drivers/crypto/hisilicon/
H A Dqm_common.h19 __le32 dw0; member
23 __le32 dw0; member
H A Dqm.c70 #define QM_EQE_PHASE(dw0) (((dw0) >> 16) & 0x1) argument
73 #define QM_AEQE_PHASE(dw0) (((dw0) >> 16) & 0x1) argument
1047 u32 dw0 = le32_to_cpu(eqe->dw0); in qm_get_complete_eqe_num() local
1051 if (QM_EQE_PHASE(dw0) != qm->status.eqc_phase) { in qm_get_complete_eqe_num()
1057 cqn = dw0 & QM_EQE_CQN_MASK; in qm_get_complete_eqe_num()
1063 poll_data->qp_finish_id[eqe_num] = dw0 & QM_EQE_CQN_MASK; in qm_get_complete_eqe_num()
1075 dw0 = le32_to_cpu(eqe->dw0); in qm_get_complete_eqe_num()
1076 if (QM_EQE_PHASE(dw0) != qm->status.eqc_phase) in qm_get_complete_eqe_num()
1170 u32 dw0 = le32_to_cpu(aeqe->dw0); in qm_aeq_thread() local
1176 while (QM_AEQE_PHASE(dw0) == qm->status.aeqc_phase) { in qm_aeq_thread()
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/linux/arch/powerpc/include/asm/
H A Dultravisor.h29 static inline int uv_register_pate(u64 lpid, u64 dw0, u64 dw1) in uv_register_pate() argument
31 return ucall_norets(UV_WRITE_PATE, lpid, dw0, dw1); in uv_register_pate()
H A Dmmu.h303 extern void mmu_partition_table_set_entry(unsigned int lpid, unsigned long dw0,
/linux/drivers/scsi/hisi_sas/
H A Dhisi_sas_v3_hw.c476 u32 dw0; member
486 __le32 dw0; member
1259 prot->dw0 |= T10_INSRT_EN_MSK; in fill_prot_v3_hw()
1263 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); in fill_prot_v3_hw()
1268 prot->dw0 |= T10_CHK_EN_MSK; in fill_prot_v3_hw()
1273 prot->dw0 |= T10_INSRT_EN_MSK; in fill_prot_v3_hw()
1277 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); in fill_prot_v3_hw()
1281 prot->dw0 |= T10_CHK_EN_MSK; in fill_prot_v3_hw()
1294 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF); in fill_prot_v3_hw()
1297 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF); in fill_prot_v3_hw()
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H A Dhisi_sas.h507 __le32 dw0; member
H A Dhisi_sas_v1_hw.c932 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | in prep_smp_v1_hw()
967 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | in prep_ssp_v1_hw()
/linux/drivers/usb/isp1760/
H A Disp1760-hcd.c59 __dw dw0; member
70 __le32 dw0; member
514 ptd->dw0 = le32_to_dw(le32_ptd.dw0); in isp1763_ptd_read()
541 ptd.dw0 = dw_to_le32(cpu_ptd->dw0); in isp1763_ptd_write()
550 isp1763_mem_write(hcd, dst_offset, (u16 *)&ptd.dw0, in isp1763_ptd_write()
551 8 * sizeof(ptd.dw0)); in isp1763_ptd_write()
563 isp1760_mem_write(base, dst_offset + sizeof(ptd->dw0), in isp1760_ptd_write()
566 isp1760_mem_write(base, dst_offset, (__force u32 *)&ptd->dw0, in isp1760_ptd_write()
567 sizeof(ptd->dw0)); in isp1760_ptd_write()
833 ptd->dw0 = DW0_VALID_BIT; in create_ptd_atl()
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/linux/drivers/dma/amd/ptdma/
H A Dptdma-dmaengine.c116 bool soc = FIELD_GET(DWORD0_SOC, desc->dwouv.dw0); in ae4_core_execute_cmd()
120 desc->dwouv.dw0 |= FIELD_PREP(DWORD0_IOC, desc->dwouv.dw0); in ae4_core_execute_cmd()
121 desc->dwouv.dw0 &= ~DWORD0_SOC; in ae4_core_execute_cmd()
H A Dptdma.h300 u32 dw0; member
/linux/drivers/net/ethernet/huawei/hinic/
H A Dhinic_debugfs.c115 ret = funcfg_table_elem->dw0.bs.valid; in hinic_dbg_get_func_table()
118 ret = funcfg_table_elem->dw0.bs.nic_rx_mode; in hinic_dbg_get_func_table()
H A Dhinic_debugfs.h41 } dw0; member
/linux/arch/powerpc/kvm/
H A Dbook3s_hv_nested.c536 void kvmhv_set_ptbl_entry(u64 lpid, u64 dw0, u64 dw1) in kvmhv_set_ptbl_entry() argument
539 mmu_partition_table_set_entry(lpid, dw0, dw1, true); in kvmhv_set_ptbl_entry()
544 pseries_partition_tb[lpid].patb0 = cpu_to_be64(dw0); in kvmhv_set_ptbl_entry()
551 kvmhv_nestedv2_set_ptbl_entry(lpid, dw0, dw1); in kvmhv_set_ptbl_entry()
556 unsigned long dw0; in kvmhv_set_nested_ptbl() local
558 dw0 = PATB_HR | radix__get_tree_size() | in kvmhv_set_nested_ptbl()
560 kvmhv_set_ptbl_entry(gp->shadow_lpid, dw0, gp->process_table); in kvmhv_set_nested_ptbl()
H A Dbook3s_hv.c5447 unsigned long dw0, dw1; in kvmppc_setup_partition_table() local
5451 dw0 = ((kvm->arch.vrma_slb_v & SLB_VSID_L) >> 1) | in kvmppc_setup_partition_table()
5454 dw0 |= kvm->arch.sdr1; in kvmppc_setup_partition_table()
5459 dw0 = PATB_HR | radix__get_tree_size() | in kvmppc_setup_partition_table()
5463 kvmhv_set_ptbl_entry(kvm->arch.lpid, dw0, dw1); in kvmppc_setup_partition_table()
/linux/drivers/dma/
H A Dhisi_dma.c113 __le32 dw0; member
525 sqe->dw0 = cpu_to_le32(FIELD_PREP(OPCODE_MASK, OPCODE_M2M)); in hisi_dma_start_transfer()
526 sqe->dw0 |= cpu_to_le32(LOCAL_IRQ_EN); in hisi_dma_start_transfer()
/linux/drivers/crypto/ccp/
H A Dccp-dev.h621 struct dword0 dw0; member
H A Dccp-dev-v5.c156 #define CCP5_CMD_DW0(p) ((p)->dw0)
/linux/drivers/pci/
H A Dpci.c3254 u32 dw0, bei, base, max_offset; in pci_ea_read() local
3258 pci_read_config_dword(dev, ent_offset, &dw0); in pci_ea_read()
3262 ent_size = (FIELD_GET(PCI_EA_ES, dw0) + 1) << 2; in pci_ea_read()
3264 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */ in pci_ea_read()
3267 bei = FIELD_GET(PCI_EA_BEI, dw0); in pci_ea_read()
3268 prop = FIELD_GET(PCI_EA_PP, dw0); in pci_ea_read()
3275 prop = FIELD_GET(PCI_EA_SP, dw0); in pci_ea_read()
/linux/Documentation/arch/powerpc/
H A Dultravisor.rst458 uint64_t dw0 /* the first double word to write */
470 * U_P2 if ``dw0`` is invalid.
/linux/drivers/net/ethernet/intel/igc/
H A Digc_main.c3665 u32 dw0 = in igc_write_flex_filter_ll() local
3678 wr32(fhft + row_idx, dw0); in igc_write_flex_filter_ll()
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_main.c12152 u32 dw0, dw1, dw2, dw3; in ixgbe_io_error_detected() local
12171 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG); in ixgbe_io_error_detected()
12191 dw0, dw1, dw2, dw3); in ixgbe_io_error_detected()