| /linux/drivers/iommu/amd/ |
| H A D | nested.c | 27 u32 gpt_level = FIELD_GET(DTE_GPT_LEVEL_MASK, gdte->dte[2]); in validate_gdte_nested()
30 if (FIELD_GET(DTE_MODE_MASK, gdte->dte[0]) != 0 || in validate_gdte_nested()
31 FIELD_GET(DTE_HOST_TRP, gdte->dte[0]) != 0) in validate_gdte_nested()
35 if (FIELD_GET(DTE_FLAG_V, gdte->dte[0]) == 1 && in validate_gdte_nested()
36 FIELD_GET(DTE_FLAG_GV, gdte->dte[0]) == 1 && in validate_gdte_nested()
37 FIELD_GET(DTE_GCR3_14_12, gdte->dte[0]) == 0 && in validate_gdte_nested()
38 FIELD_GET(DTE_GCR3_30_15, gdte->dte[1]) == 0 && in validate_gdte_nested()
39 FIELD_GET(DTE_GCR3_51_31, gdte->dte[1]) == 0) in validate_gdte_nested()
48 if (FIELD_GET(DTE_GLX, gdte->dte[0]) == 3) in validate_gdte_nested()
111 dte); in amd_iommu_alloc_domain_nested()
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| H A D | init.c | 1133 static void set_dte_bit(struct dev_table_entry *dte, u8 bit) in set_dte_bit() argument
1138 dte->data[i] |= (1UL << _bit); in set_dte_bit()
1234 struct dev_table_entry *dte = NULL; in amd_iommu_get_ivhd_dte_flags() local
1246 dte = &(e->dte); in amd_iommu_get_ivhd_dte_flags()
1251 return dte; in amd_iommu_get_ivhd_dte_flags()
1276 struct dev_table_entry dte = {}; in set_dev_entry_from_acpi_range() local
1292 set_dte_bit(&dte, DEV_ENTRY_INIT_PASS); in set_dev_entry_from_acpi_range()
1294 set_dte_bit(&dte, DEV_ENTRY_EINT_PASS); in set_dev_entry_from_acpi_range()
1296 set_dte_bit(&dte, DEV_ENTRY_NMI_PASS); in set_dev_entry_from_acpi_range()
1298 set_dte_bit(&dte, DEV_ENTRY_SYSMGT1); in set_dev_entry_from_acpi_range()
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| H A D | iommu.c | 223 struct dev_table_entry *dte) in get_dte256() argument
232 dte->data128[0] = ptr->data128[0]; in get_dte256()
233 dte->data128[1] = ptr->data128[1]; in get_dte256()
763 struct dev_table_entry dte; in dump_dte_entry() local
766 get_dte256(iommu, dev_data, &dte); in dump_dte_entry()
769 pr_err("DTE[%d]: %016llx\n", i, dte.data[i]); in dump_dte_entry()
2162 struct dev_table_entry *dte = &get_dev_table(iommu)[dev_data->devid]; in set_dte_entry() local
2166 old_domid = READ_ONCE(dte->data[1]) & DTE_DOMID_MASK; in set_dte_entry()
3012 struct dev_table_entry *dte; in amd_iommu_set_dirty_tracking() local
3028 dte = &get_dev_table(iommu)[dev_data->devid]; in amd_iommu_set_dirty_tracking()
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| /linux/Documentation/devicetree/bindings/ptp/ |
| H A D | brcm,ptp-dte.txt | 9 "brcm,ptp-dte"
11 "brcm,iproc-ptp-dte" - for iproc based SoC's
16 ptp: ptp-dte@180af650 {
17 compatible = "brcm,iproc-ptp-dte", "brcm,ptp-dte";
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| /linux/drivers/iommu/ |
| H A D | rockchip-iommu.c | 102 phys_addr_t (*pt_address)(u32 dte);
187 static inline phys_addr_t rk_dte_pt_address(u32 dte) in rk_dte_pt_address() argument
189 return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK; in rk_dte_pt_address()
208 static inline phys_addr_t rk_dte_pt_address_v2(u32 dte) in rk_dte_pt_address_v2() argument
210 u64 dte_v2 = dte; in rk_dte_pt_address_v2()
219 static inline bool rk_dte_is_pt_valid(u32 dte) in rk_dte_is_pt_valid() argument
221 return dte & RK_DTE_PT_VALID; in rk_dte_is_pt_valid()
542 u32 dte; in log_iova() local
558 dte = *dte_addr; in log_iova()
560 if (!rk_dte_is_pt_valid(dte)) in log_iova()
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| H A D | sun50i-iommu.c | 197 static phys_addr_t sun50i_dte_get_pt_address(u32 dte) in sun50i_dte_get_pt_address() argument
199 return (phys_addr_t)dte & SUN50I_DTE_PT_ADDRESS_MASK; in sun50i_dte_get_pt_address()
202 static bool sun50i_dte_is_pt_valid(u32 dte) in sun50i_dte_is_pt_valid() argument
204 return (dte & SUN50I_DTE_PT_ATTRS) == SUN50I_DTE_PT_VALID; in sun50i_dte_is_pt_valid()
563 u32 dte; in sun50i_dte_get_page_table() local
566 dte = *dte_addr; in sun50i_dte_get_page_table()
567 if (sun50i_dte_is_pt_valid(dte)) { in sun50i_dte_get_page_table()
568 phys_addr_t pt_phys = sun50i_dte_get_pt_address(dte); in sun50i_dte_get_page_table()
576 dte = sun50i_mk_dte(virt_to_phys(page_table)); in sun50i_dte_get_page_table()
577 old_dte = cmpxchg(dte_addr, 0, dte); in sun50i_dte_get_page_table()
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| /linux/net/x25/ |
| H A D | x25_facilities.c | 266 struct x25_facilities *new, struct x25_dte_facilities *dte) in x25_negotiate_facilities() argument
275 memset(dte, 0, sizeof(*dte)); in x25_negotiate_facilities()
277 len = x25_parse_facilities(skb, &theirs, dte, &x25->vc_facil_mask); in x25_negotiate_facilities()
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| /linux/drivers/irqchip/ |
| H A D | irq-gic-v5-its.c | 466 __le64 *dte; in gicv5_its_device_register() local
478 dte = gicv5_its_devtab_get_dte_ref(its, its_dev->device_id, true); in gicv5_its_device_register()
479 if (!dte) in gicv5_its_device_register()
482 if (FIELD_GET(GICV5_DTL2E_VALID, le64_to_cpu(*dte))) in gicv5_its_device_register()
531 its_write_table_entry(its, dte, val); in gicv5_its_device_register()
535 its_write_table_entry(its, dte, 0); in gicv5_its_device_register()
550 __le64 *dte; in gicv5_its_device_unregister() local
552 dte = gicv5_its_devtab_get_dte_ref(its, its_dev->device_id, false); in gicv5_its_device_unregister()
554 if (!FIELD_GET(GICV5_DTL2E_VALID, le64_to_cpu(*dte))) { in gicv5_its_device_unregister()
561 its_write_table_entry(its, dte, 0); in gicv5_its_device_unregister()
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| /linux/drivers/net/wan/ |
| H A D | wanxl.c | 112 const char *cable, *pm, *dte = "", *dsr = "", *dcd = ""; in wanxl_cable_intr() local
163 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE"; in wanxl_cable_intr()
166 pm, dte, cable, dsr, dcd); in wanxl_cable_intr()
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| /linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra20-trimslice.dts | 98 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
213 "dte", "gma", "gmc", "gmd", "gpu",
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| H A D | tegra20-tamonten.dtsi | 92 nvidia,pins = "dtb", "dtc", "dte";
206 "dtc", "dte", "gpu", "sdio1",
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| H A D | tegra20-ventana.dts | 104 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
241 nvidia,pins = "dte", "spif";
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| H A D | tegra20-paz00.dts | 101 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
217 "dtc", "dte", "slxa", "slxc", "slxd",
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| H A D | tegra20-harmony.dts | 110 nvidia,pins = "dtb", "dtc", "dte";
223 "dtc", "dte", "dtf", "gpu", "sdio1",
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| H A D | tegra20-colibri.dtsi | 381 gpio-dte {
382 nvidia,pins = "dte";
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| H A D | tegra20-seaboard.dts | 102 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
240 nvidia,pins = "dte", "spif";
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| H A D | tegra20-acer-a500-picasso.dts | 145 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
251 "dap4", "dte", "dtf", "gma", "gmc",
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx53-cx9020.dts | 170 fsl,dte-mode;
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| H A D | imx6qdl-colibri.dtsi | 669 fsl,dte-mode;
678 fsl,dte-mode;
687 fsl,dte-mode;
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| H A D | imx7d-meerkat96.dts | 171 fsl,dte-mode;
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| H A D | imx7s-warp.dts | 299 fsl,dte-mode;
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| H A D | imx6ull-tarragon-common.dtsi | 781 fsl,dte-mode;
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| H A D | imx6q-pistachio.dts | 590 fsl,dte-mode;
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mp-phycore-fpsc.dtsi | 739 fsl,dte-mode;
745 fsl,dte-mode;
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| H A D | imx8mm-phyboard-polis-rdk.dts | 250 fsl,dte-mode;
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