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Searched refs:drr_timing (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_mall_phantom.c431 …_schedulable(struct dml2_context *ctx, struct dc_state *context, struct dc_crtc_timing *drr_timing) in dml2_svp_drr_schedulable() argument
469 drr_frame_us = drr_timing->v_total * drr_timing->h_total / in dml2_svp_drr_schedulable()
470 (double)(drr_timing->pix_clk_100hz * 100) * 1000000; in dml2_svp_drr_schedulable()
475 drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / in dml2_svp_drr_schedulable()
476 (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); in dml2_svp_drr_schedulable()
484 if (stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 && in dml2_svp_drr_schedulable()
H A Ddml2_mall_phantom.h50 …schedulable(struct dml2_context *ctx, struct dc_state *context, struct dc_crtc_timing *drr_timing);
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dmub_srv.c569 struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing; in populate_subvp_cmd_drr_info() local
591 drr_frame_us = div64_u64(((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000), in populate_subvp_cmd_drr_info()
592 (((uint64_t)drr_timing->pix_clk_100hz * 100))); in populate_subvp_cmd_drr_info()
597 …min_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us… in populate_subvp_cmd_drr_info()
598 (((uint64_t)drr_timing->h_total * 1000000))); in populate_subvp_cmd_drr_info()
604 drr_active_us = div64_u64(((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000), in populate_subvp_cmd_drr_info()
605 (((uint64_t)drr_timing->pix_clk_100hz * 100))); in populate_subvp_cmd_drr_info()
610 …max_vtotal_supported = div64_u64(((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us… in populate_subvp_cmd_drr_info()
611 (((uint64_t)drr_timing->h_total * 1000000))); in populate_subvp_cmd_drr_info()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c803 struct dc_crtc_timing *drr_timing = NULL; in subvp_drr_schedulable() local
852 drr_timing = &drr_pipe->stream->timing; in subvp_drr_schedulable()
858 drr_frame_us = drr_timing->v_total * drr_timing->h_total / in subvp_drr_schedulable()
859 (double)(drr_timing->pix_clk_100hz * 100) * 1000000; in subvp_drr_schedulable()
864 …drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total / in subvp_drr_schedulable()
865 (double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us); in subvp_drr_schedulable()
874 if (drr_timing && in subvp_drr_schedulable()
875 stretched_drr_us < (1 / (double)drr_timing->min_refresh_in_uhz) * 1000000 * 1000000 && in subvp_drr_schedulable()