1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Pinctrl data for the NVIDIA Tegra264 pinmux
4 *
5 * Copyright (c) 2024-2026, NVIDIA CORPORATION. All rights reserved.
6 */
7
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/property.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/pinctrl/pinmux.h>
13
14 #include "pinctrl-tegra.h"
15
16 /* Define unique ID for each pins */
17 enum {
18 TEGRA_PIN_PEX_L4_CLKREQ_N_PD0,
19 TEGRA_PIN_PEX_L4_RST_N_PD1,
20 TEGRA_PIN_PEX_L5_CLKREQ_N_PD2,
21 TEGRA_PIN_PEX_L5_RST_N_PD3,
22 TEGRA_PIN_ETH0_MDIO_PD4,
23 TEGRA_PIN_ETH0_MDC_PD5,
24 TEGRA_PIN_ETH3_MDIO_PD6,
25 TEGRA_PIN_ETH3_MDC_PD7,
26 TEGRA_PIN_ETH1_MDIO_PE0,
27 TEGRA_PIN_ETH1_MDC_PE1,
28 TEGRA_PIN_ETH2_MDIO_PE2,
29 TEGRA_PIN_ETH2_MDC_PE3,
30 TEGRA_PIN_PEX_L1_CLKREQ_N_PB0,
31 TEGRA_PIN_PEX_L1_RST_N_PB1,
32 TEGRA_PIN_PEX_L2_CLKREQ_N_PB2,
33 TEGRA_PIN_PEX_L2_RST_N_PB3,
34 TEGRA_PIN_PEX_L3_CLKREQ_N_PB4,
35 TEGRA_PIN_PEX_L3_RST_N_PB5,
36 TEGRA_PIN_SOC_GPIO113_PB6,
37 TEGRA_PIN_SOC_GPIO114_PB7,
38 TEGRA_PIN_SGMII0_SMA_MDIO_PC0,
39 TEGRA_PIN_SGMII0_SMA_MDC_PC1,
40 TEGRA_PIN_PEX_WAKE_N_PC2,
41 TEGRA_PIN_PWM1_PA0,
42 TEGRA_PIN_PWM6_PA1,
43 TEGRA_PIN_PWM7_PA2,
44 TEGRA_PIN_PWM8_PA3,
45 TEGRA_PIN_UFS0_REF_CLK_PA4,
46 TEGRA_PIN_UFS0_RST_N_PA5,
47 };
48
49 enum {
50 TEGRA_PIN_SOC_GPIO250_PF0,
51 TEGRA_PIN_SOC_GPIO251_PF1,
52 TEGRA_PIN_SOC_GPIO252_PF2,
53 TEGRA_PIN_DP_AUX_CH0_HPD_PF3,
54 TEGRA_PIN_DP_AUX_CH1_HPD_PF4,
55 TEGRA_PIN_DP_AUX_CH2_HPD_PF5,
56 TEGRA_PIN_DP_AUX_CH3_HPD_PF6,
57 TEGRA_PIN_PWM2_PF7,
58 TEGRA_PIN_PWM3_PG0,
59 TEGRA_PIN_GEN7_I2C_SCL_PG1,
60 TEGRA_PIN_GEN7_I2C_SDA_PG2,
61 TEGRA_PIN_GEN9_I2C_SCL_PG3,
62 TEGRA_PIN_GEN9_I2C_SDA_PG4,
63 TEGRA_PIN_SDMMC1_CLK_PX0,
64 TEGRA_PIN_SDMMC1_CMD_PX1,
65 TEGRA_PIN_SDMMC1_DAT0_PX2,
66 TEGRA_PIN_SDMMC1_DAT1_PX3,
67 TEGRA_PIN_SDMMC1_DAT2_PX4,
68 TEGRA_PIN_SDMMC1_DAT3_PX5,
69 TEGRA_PIN_SDMMC1_COMP,
70 TEGRA_PIN_SOC_GPIO124_PL0,
71 TEGRA_PIN_SOC_GPIO125_PL1,
72 TEGRA_PIN_FAN_TACH0_PL2,
73 TEGRA_PIN_SOC_GPIO127_PL3,
74 TEGRA_PIN_SOC_GPIO128_PL4,
75 TEGRA_PIN_SOC_GPIO129_PL5,
76 TEGRA_PIN_SOC_GPIO130_PL6,
77 TEGRA_PIN_SOC_GPIO131_PL7,
78 TEGRA_PIN_GP_PWM9_PM0,
79 TEGRA_PIN_SOC_GPIO133_PM1,
80 TEGRA_PIN_UART9_TX_PM2,
81 TEGRA_PIN_UART9_RX_PM3,
82 TEGRA_PIN_UART9_RTS_N_PM4,
83 TEGRA_PIN_UART9_CTS_N_PM5,
84 TEGRA_PIN_SOC_GPIO170_PU0,
85 TEGRA_PIN_SOC_GPIO171_PU1,
86 TEGRA_PIN_SOC_GPIO172_PU2,
87 TEGRA_PIN_SOC_GPIO173_PU3,
88 TEGRA_PIN_SOC_GPIO174_PU4,
89 TEGRA_PIN_SOC_GPIO175_PU5,
90 TEGRA_PIN_SOC_GPIO176_PU6,
91 TEGRA_PIN_SOC_GPIO177_PU7,
92 TEGRA_PIN_SOC_GPIO178_PV0,
93 TEGRA_PIN_PWM10_PV1,
94 TEGRA_PIN_UART4_TX_PV2,
95 TEGRA_PIN_UART4_RX_PV3,
96 TEGRA_PIN_UART4_RTS_N_PV4,
97 TEGRA_PIN_UART4_CTS_N_PV5,
98 TEGRA_PIN_DAP2_CLK_PV6,
99 TEGRA_PIN_DAP2_DIN_PV7,
100 TEGRA_PIN_DAP2_DOUT_PW0,
101 TEGRA_PIN_DAP2_FS_PW1,
102 TEGRA_PIN_GEN1_I2C_SCL_PW2,
103 TEGRA_PIN_GEN1_I2C_SDA_PW3,
104 TEGRA_PIN_GEN0_I2C_SCL_PW4,
105 TEGRA_PIN_GEN0_I2C_SDA_PW5,
106 TEGRA_PIN_PWR_I2C_SCL_PW6,
107 TEGRA_PIN_PWR_I2C_SDA_PW7,
108 TEGRA_PIN_SOC_GPIO138_PP0,
109 TEGRA_PIN_SOC_GPIO139_PP1,
110 TEGRA_PIN_DAP6_SCLK_PP2,
111 TEGRA_PIN_DAP6_DOUT_PP3,
112 TEGRA_PIN_DAP6_DIN_PP4,
113 TEGRA_PIN_DAP6_FS_PP5,
114 TEGRA_PIN_DAP4_SCLK_PP6,
115 TEGRA_PIN_DAP4_DOUT_PP7,
116 TEGRA_PIN_DAP4_DIN_PQ0,
117 TEGRA_PIN_DAP4_FS_PQ1,
118 TEGRA_PIN_SPI5_SCK_PQ2,
119 TEGRA_PIN_SPI5_MISO_PQ3,
120 TEGRA_PIN_SPI5_MOSI_PQ4,
121 TEGRA_PIN_SPI5_CS0_PQ5,
122 TEGRA_PIN_SOC_GPIO152_PQ6,
123 TEGRA_PIN_SOC_GPIO153_PQ7,
124 TEGRA_PIN_AUD_MCLK_PR0,
125 TEGRA_PIN_SOC_GPIO155_PR1,
126 TEGRA_PIN_DAP1_SCLK_PR2,
127 TEGRA_PIN_DAP1_OUT_PR3,
128 TEGRA_PIN_DAP1_IN_PR4,
129 TEGRA_PIN_DAP1_FS_PR5,
130 TEGRA_PIN_GEN11_I2C_SCL_PR6,
131 TEGRA_PIN_GEN11_I2C_SDA_PR7,
132 TEGRA_PIN_SOC_GPIO350_PS0,
133 TEGRA_PIN_SOC_GPIO351_PS1,
134 TEGRA_PIN_QSPI0_SCK_PT0,
135 TEGRA_PIN_QSPI0_CS_N_PT1,
136 TEGRA_PIN_QSPI0_IO0_PT2,
137 TEGRA_PIN_QSPI0_IO1_PT3,
138 TEGRA_PIN_QSPI0_IO2_PT4,
139 TEGRA_PIN_QSPI0_IO3_PT5,
140 TEGRA_PIN_SOC_GPIO192_PT6,
141 TEGRA_PIN_SOC_GPIO270_PY0,
142 TEGRA_PIN_SOC_GPIO271_PY1,
143 TEGRA_PIN_SOC_GPIO272_PY2,
144 TEGRA_PIN_SOC_GPIO273_PY3,
145 TEGRA_PIN_SOC_GPIO274_PY4,
146 TEGRA_PIN_SOC_GPIO275_PY5,
147 TEGRA_PIN_SOC_GPIO276_PY6,
148 TEGRA_PIN_SOC_GPIO277_PY7,
149 TEGRA_PIN_SOC_GPIO278_PZ0,
150 TEGRA_PIN_SOC_GPIO279_PZ1,
151 TEGRA_PIN_XHALT_TRIG_PZ2,
152 TEGRA_PIN_SOC_GPIO281_PZ3,
153 TEGRA_PIN_SOC_GPIO282_PZ4,
154 TEGRA_PIN_SOC_GPIO283_PZ5,
155 TEGRA_PIN_SOC_GPIO284_PZ6,
156 TEGRA_PIN_SOC_GPIO285_PZ7,
157 TEGRA_PIN_SOC_GPIO286_PAL0,
158 TEGRA_PIN_SOC_GPIO287_PAL1,
159 TEGRA_PIN_SOC_GPIO288_PAL2,
160 TEGRA_PIN_CPU_PWR_REQ_PH0,
161 TEGRA_PIN_GPU_PWR_REQ_PH1,
162 TEGRA_PIN_UART10_TX_PH2,
163 TEGRA_PIN_UART10_RX_PH3,
164 TEGRA_PIN_UART10_RTS_N_PH4,
165 TEGRA_PIN_UART10_CTS_N_PH5,
166 TEGRA_PIN_SPI3_SCK_PH6,
167 TEGRA_PIN_SPI3_MISO_PH7,
168 TEGRA_PIN_SPI3_MOSI_PJ0,
169 TEGRA_PIN_SPI3_CS0_PJ1,
170 TEGRA_PIN_SPI3_CS3_PJ2,
171 TEGRA_PIN_UART5_TX_PJ3,
172 TEGRA_PIN_UART5_RX_PJ4,
173 TEGRA_PIN_UART5_RTS_N_PJ5,
174 TEGRA_PIN_UART5_CTS_N_PJ6,
175 TEGRA_PIN_SPI1_SCK_PJ7,
176 TEGRA_PIN_SPI1_MISO_PK0,
177 TEGRA_PIN_SPI1_MOSI_PK1,
178 TEGRA_PIN_SPI1_CS0_PK2,
179 TEGRA_PIN_SPI1_CS1_PK3,
180 TEGRA_PIN_EXTPERIPH1_CLK_PK4,
181 TEGRA_PIN_EXTPERIPH2_CLK_PK5,
182 TEGRA_PIN_GEN12_I2C_SCL_PK6,
183 TEGRA_PIN_GEN12_I2C_SDA_PK7,
184 };
185
186 enum {
187 TEGRA_PIN_SOC_GPIO00_PAA0,
188 TEGRA_PIN_VCOMP_ALERT_PAA1,
189 TEGRA_PIN_AO_RETENTION_N_PAA2,
190 TEGRA_PIN_BATT_OC_PAA3,
191 TEGRA_PIN_BOOTV_CTL_N_PAA4,
192 TEGRA_PIN_POWER_ON_PAA5,
193 TEGRA_PIN_HDMI_CEC_PAA6,
194 TEGRA_PIN_SOC_GPIO07_PAA7,
195 TEGRA_PIN_SOC_GPIO08_PBB0,
196 TEGRA_PIN_SOC_GPIO09_PBB1,
197 TEGRA_PIN_GEN2_I2C_SCL_PCC0,
198 TEGRA_PIN_GEN2_I2C_SDA_PCC1,
199 TEGRA_PIN_GEN3_I2C_SCL_PCC2,
200 TEGRA_PIN_GEN3_I2C_SDA_PCC3,
201 TEGRA_PIN_GP_PWM4_PCC4,
202 TEGRA_PIN_UART0_TX_PCC5,
203 TEGRA_PIN_UART0_RX_PCC6,
204 TEGRA_PIN_SPI2_SCK_PCC7,
205 TEGRA_PIN_SPI2_MISO_PDD0,
206 TEGRA_PIN_SPI2_MOSI_PDD1,
207 TEGRA_PIN_SPI2_CS0_N_PDD2,
208 TEGRA_PIN_SOC_GPIO21_PDD3,
209 TEGRA_PIN_SOC_GPIO22_PDD4,
210 TEGRA_PIN_SOC_GPIO23_PDD5,
211 TEGRA_PIN_SOC_GPIO24_PDD6,
212 TEGRA_PIN_SOC_GPIO25_PDD7,
213 TEGRA_PIN_SOC_GPIO26_PEE0,
214 TEGRA_PIN_SOC_GPIO27_PEE1,
215 TEGRA_PIN_SOC_GPIO28_PEE2,
216 TEGRA_PIN_SOC_GPIO29_PEE3,
217 };
218
219 static const struct pinctrl_pin_desc tegra264_uphy_pins[] = {
220 PINCTRL_PIN(TEGRA_PIN_PEX_L4_CLKREQ_N_PD0, "PEX_L4_CLKREQ_N_PD0"),
221 PINCTRL_PIN(TEGRA_PIN_PEX_L4_RST_N_PD1, "PEX_L4_RST_N_PD1"),
222 PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PD2, "PEX_L5_CLKREQ_N_PD2"),
223 PINCTRL_PIN(TEGRA_PIN_PEX_L5_RST_N_PD3, "PEX_L5_RST_N_PD3"),
224 PINCTRL_PIN(TEGRA_PIN_ETH0_MDIO_PD4, "ETH0_MDIO_PD4"),
225 PINCTRL_PIN(TEGRA_PIN_ETH0_MDC_PD5, "ETH0_MDC_PD5"),
226 PINCTRL_PIN(TEGRA_PIN_ETH3_MDIO_PD6, "ETH3_MDIO_PD6"),
227 PINCTRL_PIN(TEGRA_PIN_ETH3_MDC_PD7, "ETH3_MDC_PD7"),
228 PINCTRL_PIN(TEGRA_PIN_ETH1_MDIO_PE0, "ETH1_MDIO_PE0"),
229 PINCTRL_PIN(TEGRA_PIN_ETH1_MDC_PE1, "ETH1_MDC_PE1"),
230 PINCTRL_PIN(TEGRA_PIN_ETH2_MDIO_PE2, "ETH2_MDIO_PE2"),
231 PINCTRL_PIN(TEGRA_PIN_ETH2_MDC_PE3, "ETH2_MDC_PE3"),
232 PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PB0, "PEX_L1_CLKREQ_N_PB0"),
233 PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PB1, "PEX_L1_RST_N_PB1"),
234 PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PB2, "PEX_L2_CLKREQ_N_PB2"),
235 PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PB3, "PEX_L2_RST_N_PB3"),
236 PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PB4, "PEX_L3_CLKREQ_N_PB4"),
237 PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PB5, "PEX_L3_RST_N_PB5"),
238 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO113_PB6, "SOC_GPIO113_PB6"),
239 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO114_PB7, "SOC_GPIO114_PB7"),
240 PINCTRL_PIN(TEGRA_PIN_SGMII0_SMA_MDIO_PC0, "SGMII0_SMA_MDIO_PC0"),
241 PINCTRL_PIN(TEGRA_PIN_SGMII0_SMA_MDC_PC1, "SGMII0_SMA_MDC_PC1"),
242 PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PC2, "PEX_WAKE_N_PC2"),
243 PINCTRL_PIN(TEGRA_PIN_PWM1_PA0, "PWM1_PA0"),
244 PINCTRL_PIN(TEGRA_PIN_PWM6_PA1, "PWM6_PA1"),
245 PINCTRL_PIN(TEGRA_PIN_PWM7_PA2, "PWM7_PA2"),
246 PINCTRL_PIN(TEGRA_PIN_PWM8_PA3, "PWM8_PA3"),
247 PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PA4, "UFS0_REF_CLK_PA4"),
248 PINCTRL_PIN(TEGRA_PIN_UFS0_RST_N_PA5, "UFS0_RST_N_PA5"),
249 };
250
251 static const struct pinctrl_pin_desc tegra264_main_pins[] = {
252 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO250_PF0, "SOC_GPIO250_PF0"),
253 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO251_PF1, "SOC_GPIO251_PF1"),
254 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO252_PF2, "SOC_GPIO252_PF2"),
255 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PF3, "DP_AUX_CH0_HPD_PF3"),
256 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PF4, "DP_AUX_CH1_HPD_PF4"),
257 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH2_HPD_PF5, "DP_AUX_CH2_HPD_PF5"),
258 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH3_HPD_PF6, "DP_AUX_CH3_HPD_PF6"),
259 PINCTRL_PIN(TEGRA_PIN_PWM2_PF7, "PWM2_PF7"),
260 PINCTRL_PIN(TEGRA_PIN_PWM3_PG0, "PWM3_PG0"),
261 PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PG1, "GEN7_I2C_SCL_PG1"),
262 PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PG2, "GEN7_I2C_SDA_PG2"),
263 PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PG3, "GEN9_I2C_SCL_PG3"),
264 PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PG4, "GEN9_I2C_SDA_PG4"),
265 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PX0, "SDMMC1_CLK_PX0"),
266 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PX1, "SDMMC1_CMD_PX1"),
267 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PX2, "SDMMC1_DAT0_PX2"),
268 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PX3, "SDMMC1_DAT1_PX3"),
269 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PX4, "SDMMC1_DAT2_PX4"),
270 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PX5, "SDMMC1_DAT3_PX5"),
271 PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),
272 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_PH0, "CPU_PWR_REQ_PH0"),
273 PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PH1, "GPU_PWR_REQ_PH1"),
274 PINCTRL_PIN(TEGRA_PIN_UART10_TX_PH2, "UART10_TX_PH2"),
275 PINCTRL_PIN(TEGRA_PIN_UART10_RX_PH3, "UART10_RX_PH3"),
276 PINCTRL_PIN(TEGRA_PIN_UART10_RTS_N_PH4, "UART10_RTS_N_PH4"),
277 PINCTRL_PIN(TEGRA_PIN_UART10_CTS_N_PH5, "UART10_CTS_N_PH5"),
278 PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PH6, "SPI3_SCK_PH6"),
279 PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PH7, "SPI3_MISO_PH7"),
280 PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PJ0, "SPI3_MOSI_PJ0"),
281 PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PJ1, "SPI3_CS0_PJ1"),
282 PINCTRL_PIN(TEGRA_PIN_SPI3_CS3_PJ2, "SPI3_CS3_PJ2"),
283 PINCTRL_PIN(TEGRA_PIN_UART5_TX_PJ3, "UART5_TX_PJ3"),
284 PINCTRL_PIN(TEGRA_PIN_UART5_RX_PJ4, "UART5_RX_PJ4"),
285 PINCTRL_PIN(TEGRA_PIN_UART5_RTS_N_PJ5, "UART5_RTS_N_PJ5"),
286 PINCTRL_PIN(TEGRA_PIN_UART5_CTS_N_PJ6, "UART5_CTS_N_PJ6"),
287 PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PJ7, "SPI1_SCK_PJ7"),
288 PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PK0, "SPI1_MISO_PK0"),
289 PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PK1, "SPI1_MOSI_PK1"),
290 PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PK2, "SPI1_CS0_PK2"),
291 PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PK3, "SPI1_CS1_PK3"),
292 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PK4, "EXTPERIPH1_CLK_PK4"),
293 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PK5, "EXTPERIPH2_CLK_PK5"),
294 PINCTRL_PIN(TEGRA_PIN_GEN12_I2C_SCL_PK6, "GEN12_I2C_SCL_PK6"),
295 PINCTRL_PIN(TEGRA_PIN_GEN12_I2C_SDA_PK7, "GEN12_I2C_SDA_PK7"),
296 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO124_PL0, "SOC_GPIO124_PL0"),
297 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO125_PL1, "SOC_GPIO125_PL1"),
298 PINCTRL_PIN(TEGRA_PIN_FAN_TACH0_PL2, "FAN_TACH0_PL2"),
299 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO127_PL3, "SOC_GPIO127_PL3"),
300 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO128_PL4, "SOC_GPIO128_PL4"),
301 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO129_PL5, "SOC_GPIO129_PL5"),
302 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO130_PL6, "SOC_GPIO130_PL6"),
303 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO131_PL7, "SOC_GPIO131_PL7"),
304 PINCTRL_PIN(TEGRA_PIN_GP_PWM9_PM0, "GP_PWM9_PM0"),
305 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO133_PM1, "SOC_GPIO133_PM1"),
306 PINCTRL_PIN(TEGRA_PIN_UART9_TX_PM2, "UART9_TX_PM2"),
307 PINCTRL_PIN(TEGRA_PIN_UART9_RX_PM3, "UART9_RX_PM3"),
308 PINCTRL_PIN(TEGRA_PIN_UART9_RTS_N_PM4, "UART9_RTS_N_PM4"),
309 PINCTRL_PIN(TEGRA_PIN_UART9_CTS_N_PM5, "UART9_CTS_N_PM5"),
310 PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PT0, "QSPI0_SCK_PT0"),
311 PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PT1, "QSPI0_CS_N_PT1"),
312 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PT2, "QSPI0_IO0_PT2"),
313 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PT3, "QSPI0_IO1_PT3"),
314 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO2_PT4, "QSPI0_IO2_PT4"),
315 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO3_PT5, "QSPI0_IO3_PT5"),
316 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO192_PT6, "SOC_GPIO192_PT6"),
317 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO170_PU0, "SOC_GPIO170_PU0"),
318 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO171_PU1, "SOC_GPIO171_PU1"),
319 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO172_PU2, "SOC_GPIO172_PU2"),
320 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO173_PU3, "SOC_GPIO173_PU3"),
321 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO174_PU4, "SOC_GPIO174_PU4"),
322 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO175_PU5, "SOC_GPIO175_PU5"),
323 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO176_PU6, "SOC_GPIO176_PU6"),
324 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO177_PU7, "SOC_GPIO177_PU7"),
325 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO178_PV0, "SOC_GPIO178_PV0"),
326 PINCTRL_PIN(TEGRA_PIN_PWM10_PV1, "PWM10_PV1"),
327 PINCTRL_PIN(TEGRA_PIN_UART4_TX_PV2, "UART4_TX_PV2"),
328 PINCTRL_PIN(TEGRA_PIN_UART4_RX_PV3, "UART4_RX_PV3"),
329 PINCTRL_PIN(TEGRA_PIN_UART4_RTS_N_PV4, "UART4_RTS_N_PV4"),
330 PINCTRL_PIN(TEGRA_PIN_UART4_CTS_N_PV5, "UART4_CTS_N_PV5"),
331 PINCTRL_PIN(TEGRA_PIN_DAP2_CLK_PV6, "DAP2_CLK_PV6"),
332 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PV7, "DAP2_DIN_PV7"),
333 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PW0, "DAP2_DOUT_PW0"),
334 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PW1, "DAP2_FS_PW1"),
335 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PW2, "GEN1_I2C_SCL_PW2"),
336 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PW3, "GEN1_I2C_SDA_PW3"),
337 PINCTRL_PIN(TEGRA_PIN_GEN0_I2C_SCL_PW4, "GEN0_I2C_SCL_PW4"),
338 PINCTRL_PIN(TEGRA_PIN_GEN0_I2C_SDA_PW5, "GEN0_I2C_SDA_PW5"),
339 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PW6, "PWR_I2C_SCL_PW6"),
340 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PW7, "PWR_I2C_SDA_PW7"),
341 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO270_PY0, "SOC_GPIO270_PY0"),
342 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO271_PY1, "SOC_GPIO271_PY1"),
343 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO272_PY2, "SOC_GPIO272_PY2"),
344 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO273_PY3, "SOC_GPIO273_PY3"),
345 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO274_PY4, "SOC_GPIO274_PY4"),
346 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO275_PY5, "SOC_GPIO275_PY5"),
347 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO276_PY6, "SOC_GPIO276_PY6"),
348 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO277_PY7, "SOC_GPIO277_PY7"),
349 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO278_PZ0, "SOC_GPIO278_PZ0"),
350 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO279_PZ1, "SOC_GPIO279_PZ1"),
351 PINCTRL_PIN(TEGRA_PIN_XHALT_TRIG_PZ2, "XHALT_TRIG_PZ2"),
352 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO281_PZ3, "SOC_GPIO281_PZ3"),
353 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO282_PZ4, "SOC_GPIO282_PZ4"),
354 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO283_PZ5, "SOC_GPIO283_PZ5"),
355 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO284_PZ6, "SOC_GPIO284_PZ6"),
356 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO285_PZ7, "SOC_GPIO285_PZ7"),
357 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO286_PAL0, "SOC_GPIO286_PAL0"),
358 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO287_PAL1, "SOC_GPIO287_PAL1"),
359 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO288_PAL2, "SOC_GPIO288_PAL2"),
360 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO138_PP0, "SOC_GPIO138_PP0"),
361 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO139_PP1, "SOC_GPIO139_PP1"),
362 PINCTRL_PIN(TEGRA_PIN_DAP6_SCLK_PP2, "DAP6_SCLK_PP2"),
363 PINCTRL_PIN(TEGRA_PIN_DAP6_DOUT_PP3, "DAP6_DOUT_PP3"),
364 PINCTRL_PIN(TEGRA_PIN_DAP6_DIN_PP4, "DAP6_DIN_PP4"),
365 PINCTRL_PIN(TEGRA_PIN_DAP6_FS_PP5, "DAP6_FS_PP5"),
366 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP6, "DAP4_SCLK_PP6"),
367 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP7, "DAP4_DOUT_PP7"),
368 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PQ0, "DAP4_DIN_PQ0"),
369 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PQ1, "DAP4_FS_PQ1"),
370 PINCTRL_PIN(TEGRA_PIN_SPI5_SCK_PQ2, "SPI5_SCK_PQ2"),
371 PINCTRL_PIN(TEGRA_PIN_SPI5_MISO_PQ3, "SPI5_MISO_PQ3"),
372 PINCTRL_PIN(TEGRA_PIN_SPI5_MOSI_PQ4, "SPI5_MOSI_PQ4"),
373 PINCTRL_PIN(TEGRA_PIN_SPI5_CS0_PQ5, "SPI5_CS0_PQ5"),
374 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO152_PQ6, "SOC_GPIO152_PQ6"),
375 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO153_PQ7, "SOC_GPIO153_PQ7"),
376 PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PR0, "AUD_MCLK_PR0"),
377 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO155_PR1, "SOC_GPIO155_PR1"),
378 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PR2, "DAP1_SCLK_PR2"),
379 PINCTRL_PIN(TEGRA_PIN_DAP1_OUT_PR3, "DAP1_OUT_PR3"),
380 PINCTRL_PIN(TEGRA_PIN_DAP1_IN_PR4, "DAP1_IN_PR4"),
381 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PR5, "DAP1_FS_PR5"),
382 PINCTRL_PIN(TEGRA_PIN_GEN11_I2C_SCL_PR6, "GEN11_I2C_SCL_PR6"),
383 PINCTRL_PIN(TEGRA_PIN_GEN11_I2C_SDA_PR7, "GEN11_I2C_SDA_PR7"),
384 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO350_PS0, "SOC_GPIO350_PS0"),
385 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO351_PS1, "SOC_GPIO351_PS1"),
386
387 };
388
389 static const struct pinctrl_pin_desc tegra264_aon_pins[] = {
390 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PAA0, "SOC_GPIO00_PAA0"),
391 PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PAA1, "VCOMP_ALERT_PAA1"),
392 PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PAA2, "AO_RETENTION_N_PAA2"),
393 PINCTRL_PIN(TEGRA_PIN_BATT_OC_PAA3, "BATT_OC_PAA3"),
394 PINCTRL_PIN(TEGRA_PIN_BOOTV_CTL_N_PAA4, "BOOTV_CTL_N_PAA4"),
395 PINCTRL_PIN(TEGRA_PIN_POWER_ON_PAA5, "POWER_ON_PAA5"),
396 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PAA6, "HDMI_CEC_PAA6"),
397 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PAA7, "SOC_GPIO07_PAA7"),
398 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO08_PBB0, "SOC_GPIO08_PBB0"),
399 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO09_PBB1, "SOC_GPIO09_PBB1"),
400 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC0, "GEN2_I2C_SCL_PCC0"),
401 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PCC1, "GEN2_I2C_SDA_PCC1"),
402 PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PCC2, "GEN3_I2C_SCL_PCC2"),
403 PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PCC3, "GEN3_I2C_SDA_PCC3"),
404 PINCTRL_PIN(TEGRA_PIN_GP_PWM4_PCC4, "GP_PWM4_PCC4"),
405 PINCTRL_PIN(TEGRA_PIN_UART0_TX_PCC5, "UART0_TX_PCC5"),
406 PINCTRL_PIN(TEGRA_PIN_UART0_RX_PCC6, "UART0_RX_PCC6"),
407 PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC7, "SPI2_SCK_PCC7"),
408 PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PDD0, "SPI2_MISO_PDD0"),
409 PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PDD1, "SPI2_MOSI_PDD1"),
410 PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_N_PDD2, "SPI2_CS0_N_PDD2"),
411 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PDD3, "SOC_GPIO21_PDD3"),
412 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PDD4, "SOC_GPIO22_PDD4"),
413 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PDD5, "SOC_GPIO23_PDD5"),
414 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO24_PDD6, "SOC_GPIO24_PDD6"),
415 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO25_PDD7, "SOC_GPIO25_PDD7"),
416 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO26_PEE0, "SOC_GPIO26_PEE0"),
417 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO27_PEE1, "SOC_GPIO27_PEE1"),
418 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO28_PEE2, "SOC_GPIO28_PEE2"),
419 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO29_PEE3, "SOC_GPIO29_PEE3"),
420 };
421
422 static const unsigned int soc_gpio250_pf0_pins[] = {
423 TEGRA_PIN_SOC_GPIO250_PF0,
424 };
425
426 static const unsigned int soc_gpio251_pf1_pins[] = {
427 TEGRA_PIN_SOC_GPIO251_PF1,
428 };
429
430 static const unsigned int soc_gpio252_pf2_pins[] = {
431 TEGRA_PIN_SOC_GPIO252_PF2,
432 };
433
434 static const unsigned int dp_aux_ch0_hpd_pf3_pins[] = {
435 TEGRA_PIN_DP_AUX_CH0_HPD_PF3,
436 };
437
438 static const unsigned int dp_aux_ch1_hpd_pf4_pins[] = {
439 TEGRA_PIN_DP_AUX_CH1_HPD_PF4,
440 };
441
442 static const unsigned int dp_aux_ch2_hpd_pf5_pins[] = {
443 TEGRA_PIN_DP_AUX_CH2_HPD_PF5,
444 };
445
446 static const unsigned int dp_aux_ch3_hpd_pf6_pins[] = {
447 TEGRA_PIN_DP_AUX_CH3_HPD_PF6,
448 };
449
450 static const unsigned int pwm2_pf7_pins[] = {
451 TEGRA_PIN_PWM2_PF7,
452 };
453
454 static const unsigned int pwm3_pg0_pins[] = {
455 TEGRA_PIN_PWM3_PG0,
456 };
457
458 static const unsigned int gen7_i2c_scl_pg1_pins[] = {
459 TEGRA_PIN_GEN7_I2C_SCL_PG1,
460 };
461
462 static const unsigned int gen7_i2c_sda_pg2_pins[] = {
463 TEGRA_PIN_GEN7_I2C_SDA_PG2,
464 };
465
466 static const unsigned int gen9_i2c_scl_pg3_pins[] = {
467 TEGRA_PIN_GEN9_I2C_SCL_PG3,
468 };
469
470 static const unsigned int gen9_i2c_sda_pg4_pins[] = {
471 TEGRA_PIN_GEN9_I2C_SDA_PG4,
472 };
473
474 static const unsigned int pwm1_pa0_pins[] = {
475 TEGRA_PIN_PWM1_PA0,
476 };
477
478 static const unsigned int pwm6_pa1_pins[] = {
479 TEGRA_PIN_PWM6_PA1,
480 };
481
482 static const unsigned int pwm7_pa2_pins[] = {
483 TEGRA_PIN_PWM7_PA2,
484 };
485
486 static const unsigned int pwm8_pa3_pins[] = {
487 TEGRA_PIN_PWM8_PA3,
488 };
489
490 static const unsigned int ufs0_ref_clk_pa4_pins[] = {
491 TEGRA_PIN_UFS0_REF_CLK_PA4,
492 };
493
494 static const unsigned int ufs0_rst_n_pa5_pins[] = {
495 TEGRA_PIN_UFS0_RST_N_PA5,
496 };
497
498 static const unsigned int pex_l1_clkreq_n_pb0_pins[] = {
499 TEGRA_PIN_PEX_L1_CLKREQ_N_PB0,
500 };
501
502 static const unsigned int pex_l1_rst_n_pb1_pins[] = {
503 TEGRA_PIN_PEX_L1_RST_N_PB1,
504 };
505
506 static const unsigned int pex_l2_clkreq_n_pb2_pins[] = {
507 TEGRA_PIN_PEX_L2_CLKREQ_N_PB2,
508 };
509
510 static const unsigned int pex_l2_rst_n_pb3_pins[] = {
511 TEGRA_PIN_PEX_L2_RST_N_PB3,
512 };
513
514 static const unsigned int pex_l3_clkreq_n_pb4_pins[] = {
515 TEGRA_PIN_PEX_L3_CLKREQ_N_PB4,
516 };
517
518 static const unsigned int pex_l3_rst_n_pb5_pins[] = {
519 TEGRA_PIN_PEX_L3_RST_N_PB5,
520 };
521
522 static const unsigned int soc_gpio113_pb6_pins[] = {
523 TEGRA_PIN_SOC_GPIO113_PB6,
524 };
525
526 static const unsigned int soc_gpio114_pb7_pins[] = {
527 TEGRA_PIN_SOC_GPIO114_PB7,
528 };
529
530 static const unsigned int sgmii0_sma_mdio_pc0_pins[] = {
531 TEGRA_PIN_SGMII0_SMA_MDIO_PC0,
532 };
533
534 static const unsigned int sgmii0_sma_mdc_pc1_pins[] = {
535 TEGRA_PIN_SGMII0_SMA_MDC_PC1,
536 };
537
538 static const unsigned int pex_wake_n_pc2_pins[] = {
539 TEGRA_PIN_PEX_WAKE_N_PC2,
540 };
541
542 static const unsigned int pex_l4_clkreq_n_pd0_pins[] = {
543 TEGRA_PIN_PEX_L4_CLKREQ_N_PD0,
544 };
545
546 static const unsigned int pex_l4_rst_n_pd1_pins[] = {
547 TEGRA_PIN_PEX_L4_RST_N_PD1,
548 };
549
550 static const unsigned int pex_l5_clkreq_n_pd2_pins[] = {
551 TEGRA_PIN_PEX_L5_CLKREQ_N_PD2,
552 };
553
554 static const unsigned int pex_l5_rst_n_pd3_pins[] = {
555 TEGRA_PIN_PEX_L5_RST_N_PD3,
556 };
557
558 static const unsigned int eth0_mdio_pd4_pins[] = {
559 TEGRA_PIN_ETH0_MDIO_PD4,
560 };
561
562 static const unsigned int eth0_mdc_pd5_pins[] = {
563 TEGRA_PIN_ETH0_MDC_PD5,
564 };
565
566 static const unsigned int eth3_mdio_pd6_pins[] = {
567 TEGRA_PIN_ETH3_MDIO_PD6,
568 };
569
570 static const unsigned int eth3_mdc_pd7_pins[] = {
571 TEGRA_PIN_ETH3_MDC_PD7,
572 };
573
574 static const unsigned int eth1_mdio_pe0_pins[] = {
575 TEGRA_PIN_ETH1_MDIO_PE0,
576 };
577
578 static const unsigned int eth1_mdc_pe1_pins[] = {
579 TEGRA_PIN_ETH1_MDC_PE1,
580 };
581
582 static const unsigned int eth2_mdio_pe2_pins[] = {
583 TEGRA_PIN_ETH2_MDIO_PE2,
584 };
585
586 static const unsigned int eth2_mdc_pe3_pins[] = {
587 TEGRA_PIN_ETH2_MDC_PE3,
588 };
589
590 static const unsigned int sdmmc1_clk_px0_pins[] = {
591 TEGRA_PIN_SDMMC1_CLK_PX0,
592 };
593
594 static const unsigned int sdmmc1_cmd_px1_pins[] = {
595 TEGRA_PIN_SDMMC1_CMD_PX1,
596 };
597
598 static const unsigned int sdmmc1_dat0_px2_pins[] = {
599 TEGRA_PIN_SDMMC1_DAT0_PX2,
600 };
601
602 static const unsigned int sdmmc1_dat1_px3_pins[] = {
603 TEGRA_PIN_SDMMC1_DAT1_PX3,
604 };
605
606 static const unsigned int sdmmc1_dat2_px4_pins[] = {
607 TEGRA_PIN_SDMMC1_DAT2_PX4,
608 };
609
610 static const unsigned int sdmmc1_dat3_px5_pins[] = {
611 TEGRA_PIN_SDMMC1_DAT3_PX5,
612 };
613
614 static const unsigned int sdmmc1_comp_pins[] = {
615 TEGRA_PIN_SDMMC1_COMP,
616 };
617
618 static const unsigned int cpu_pwr_req_ph0_pins[] = {
619 TEGRA_PIN_CPU_PWR_REQ_PH0,
620 };
621
622 static const unsigned int gpu_pwr_req_ph1_pins[] = {
623 TEGRA_PIN_GPU_PWR_REQ_PH1,
624 };
625
626 static const unsigned int uart10_tx_ph2_pins[] = {
627 TEGRA_PIN_UART10_TX_PH2,
628 };
629
630 static const unsigned int uart10_rx_ph3_pins[] = {
631 TEGRA_PIN_UART10_RX_PH3,
632 };
633
634 static const unsigned int uart10_rts_n_ph4_pins[] = {
635 TEGRA_PIN_UART10_RTS_N_PH4,
636 };
637
638 static const unsigned int uart10_cts_n_ph5_pins[] = {
639 TEGRA_PIN_UART10_CTS_N_PH5,
640 };
641
642 static const unsigned int spi3_sck_ph6_pins[] = {
643 TEGRA_PIN_SPI3_SCK_PH6,
644 };
645
646 static const unsigned int spi3_miso_ph7_pins[] = {
647 TEGRA_PIN_SPI3_MISO_PH7,
648 };
649
650 static const unsigned int spi3_mosi_pj0_pins[] = {
651 TEGRA_PIN_SPI3_MOSI_PJ0,
652 };
653
654 static const unsigned int spi3_cs0_pj1_pins[] = {
655 TEGRA_PIN_SPI3_CS0_PJ1,
656 };
657
658 static const unsigned int spi3_cs3_pj2_pins[] = {
659 TEGRA_PIN_SPI3_CS3_PJ2,
660 };
661
662 static const unsigned int uart5_tx_pj3_pins[] = {
663 TEGRA_PIN_UART5_TX_PJ3,
664 };
665
666 static const unsigned int uart5_rx_pj4_pins[] = {
667 TEGRA_PIN_UART5_RX_PJ4,
668 };
669
670 static const unsigned int uart5_rts_n_pj5_pins[] = {
671 TEGRA_PIN_UART5_RTS_N_PJ5,
672 };
673
674 static const unsigned int uart5_cts_n_pj6_pins[] = {
675 TEGRA_PIN_UART5_CTS_N_PJ6,
676 };
677
678 static const unsigned int spi1_sck_pj7_pins[] = {
679 TEGRA_PIN_SPI1_SCK_PJ7,
680 };
681
682 static const unsigned int spi1_miso_pk0_pins[] = {
683 TEGRA_PIN_SPI1_MISO_PK0,
684 };
685
686 static const unsigned int spi1_mosi_pk1_pins[] = {
687 TEGRA_PIN_SPI1_MOSI_PK1,
688 };
689
690 static const unsigned int spi1_cs0_pk2_pins[] = {
691 TEGRA_PIN_SPI1_CS0_PK2,
692 };
693
694 static const unsigned int spi1_cs1_pk3_pins[] = {
695 TEGRA_PIN_SPI1_CS1_PK3,
696 };
697
698 static const unsigned int extperiph1_clk_pk4_pins[] = {
699 TEGRA_PIN_EXTPERIPH1_CLK_PK4,
700 };
701
702 static const unsigned int extperiph2_clk_pk5_pins[] = {
703 TEGRA_PIN_EXTPERIPH2_CLK_PK5,
704 };
705
706 static const unsigned int gen12_i2c_scl_pk6_pins[] = {
707 TEGRA_PIN_GEN12_I2C_SCL_PK6,
708 };
709
710 static const unsigned int gen12_i2c_sda_pk7_pins[] = {
711 TEGRA_PIN_GEN12_I2C_SDA_PK7,
712 };
713
714 static const unsigned int soc_gpio124_pl0_pins[] = {
715 TEGRA_PIN_SOC_GPIO124_PL0,
716 };
717
718 static const unsigned int soc_gpio125_pl1_pins[] = {
719 TEGRA_PIN_SOC_GPIO125_PL1,
720 };
721
722 static const unsigned int fan_tach0_pl2_pins[] = {
723 TEGRA_PIN_FAN_TACH0_PL2,
724 };
725
726 static const unsigned int soc_gpio127_pl3_pins[] = {
727 TEGRA_PIN_SOC_GPIO127_PL3,
728 };
729
730 static const unsigned int soc_gpio128_pl4_pins[] = {
731 TEGRA_PIN_SOC_GPIO128_PL4,
732 };
733
734 static const unsigned int soc_gpio129_pl5_pins[] = {
735 TEGRA_PIN_SOC_GPIO129_PL5,
736 };
737
738 static const unsigned int soc_gpio130_pl6_pins[] = {
739 TEGRA_PIN_SOC_GPIO130_PL6,
740 };
741
742 static const unsigned int soc_gpio131_pl7_pins[] = {
743 TEGRA_PIN_SOC_GPIO131_PL7,
744 };
745
746 static const unsigned int gp_pwm9_pm0_pins[] = {
747 TEGRA_PIN_GP_PWM9_PM0,
748 };
749
750 static const unsigned int soc_gpio133_pm1_pins[] = {
751 TEGRA_PIN_SOC_GPIO133_PM1,
752 };
753
754 static const unsigned int uart9_tx_pm2_pins[] = {
755 TEGRA_PIN_UART9_TX_PM2,
756 };
757
758 static const unsigned int uart9_rx_pm3_pins[] = {
759 TEGRA_PIN_UART9_RX_PM3,
760 };
761
762 static const unsigned int uart9_rts_n_pm4_pins[] = {
763 TEGRA_PIN_UART9_RTS_N_PM4,
764 };
765
766 static const unsigned int uart9_cts_n_pm5_pins[] = {
767 TEGRA_PIN_UART9_CTS_N_PM5,
768 };
769
770 static const unsigned int soc_gpio170_pu0_pins[] = {
771 TEGRA_PIN_SOC_GPIO170_PU0,
772 };
773
774 static const unsigned int soc_gpio171_pu1_pins[] = {
775 TEGRA_PIN_SOC_GPIO171_PU1,
776 };
777
778 static const unsigned int soc_gpio172_pu2_pins[] = {
779 TEGRA_PIN_SOC_GPIO172_PU2,
780 };
781
782 static const unsigned int soc_gpio173_pu3_pins[] = {
783 TEGRA_PIN_SOC_GPIO173_PU3,
784 };
785
786 static const unsigned int soc_gpio174_pu4_pins[] = {
787 TEGRA_PIN_SOC_GPIO174_PU4,
788 };
789
790 static const unsigned int soc_gpio175_pu5_pins[] = {
791 TEGRA_PIN_SOC_GPIO175_PU5,
792 };
793
794 static const unsigned int soc_gpio176_pu6_pins[] = {
795 TEGRA_PIN_SOC_GPIO176_PU6,
796 };
797
798 static const unsigned int soc_gpio177_pu7_pins[] = {
799 TEGRA_PIN_SOC_GPIO177_PU7,
800 };
801
802 static const unsigned int soc_gpio178_pv0_pins[] = {
803 TEGRA_PIN_SOC_GPIO178_PV0,
804 };
805
806 static const unsigned int pwm10_pv1_pins[] = {
807 TEGRA_PIN_PWM10_PV1,
808 };
809
810 static const unsigned int uart4_tx_pv2_pins[] = {
811 TEGRA_PIN_UART4_TX_PV2,
812 };
813
814 static const unsigned int uart4_rx_pv3_pins[] = {
815 TEGRA_PIN_UART4_RX_PV3,
816 };
817
818 static const unsigned int uart4_rts_n_pv4_pins[] = {
819 TEGRA_PIN_UART4_RTS_N_PV4,
820 };
821
822 static const unsigned int uart4_cts_n_pv5_pins[] = {
823 TEGRA_PIN_UART4_CTS_N_PV5,
824 };
825
826 static const unsigned int dap2_clk_pv6_pins[] = {
827 TEGRA_PIN_DAP2_CLK_PV6,
828 };
829
830 static const unsigned int dap2_din_pv7_pins[] = {
831 TEGRA_PIN_DAP2_DIN_PV7,
832 };
833
834 static const unsigned int dap2_dout_pw0_pins[] = {
835 TEGRA_PIN_DAP2_DOUT_PW0,
836 };
837
838 static const unsigned int dap2_fs_pw1_pins[] = {
839 TEGRA_PIN_DAP2_FS_PW1,
840 };
841
842 static const unsigned int gen1_i2c_scl_pw2_pins[] = {
843 TEGRA_PIN_GEN1_I2C_SCL_PW2,
844 };
845
846 static const unsigned int gen1_i2c_sda_pw3_pins[] = {
847 TEGRA_PIN_GEN1_I2C_SDA_PW3,
848 };
849
850 static const unsigned int gen0_i2c_scl_pw4_pins[] = {
851 TEGRA_PIN_GEN0_I2C_SCL_PW4,
852 };
853
854 static const unsigned int gen0_i2c_sda_pw5_pins[] = {
855 TEGRA_PIN_GEN0_I2C_SDA_PW5,
856 };
857
858 static const unsigned int pwr_i2c_scl_pw6_pins[] = {
859 TEGRA_PIN_PWR_I2C_SCL_PW6,
860 };
861
862 static const unsigned int pwr_i2c_sda_pw7_pins[] = {
863 TEGRA_PIN_PWR_I2C_SDA_PW7,
864 };
865
866 static const unsigned int qspi0_sck_pt0_pins[] = {
867 TEGRA_PIN_QSPI0_SCK_PT0,
868 };
869
870 static const unsigned int qspi0_cs_n_pt1_pins[] = {
871 TEGRA_PIN_QSPI0_CS_N_PT1,
872 };
873
874 static const unsigned int qspi0_io0_pt2_pins[] = {
875 TEGRA_PIN_QSPI0_IO0_PT2,
876 };
877
878 static const unsigned int qspi0_io1_pt3_pins[] = {
879 TEGRA_PIN_QSPI0_IO1_PT3,
880 };
881
882 static const unsigned int qspi0_io2_pt4_pins[] = {
883 TEGRA_PIN_QSPI0_IO2_PT4,
884 };
885
886 static const unsigned int qspi0_io3_pt5_pins[] = {
887 TEGRA_PIN_QSPI0_IO3_PT5,
888 };
889
890 static const unsigned int soc_gpio192_pt6_pins[] = {
891 TEGRA_PIN_SOC_GPIO192_PT6,
892 };
893
894 static const unsigned int soc_gpio138_pp0_pins[] = {
895 TEGRA_PIN_SOC_GPIO138_PP0,
896 };
897
898 static const unsigned int soc_gpio139_pp1_pins[] = {
899 TEGRA_PIN_SOC_GPIO139_PP1,
900 };
901
902 static const unsigned int dap6_sclk_pp2_pins[] = {
903 TEGRA_PIN_DAP6_SCLK_PP2,
904 };
905
906 static const unsigned int dap6_dout_pp3_pins[] = {
907 TEGRA_PIN_DAP6_DOUT_PP3,
908 };
909
910 static const unsigned int dap6_din_pp4_pins[] = {
911 TEGRA_PIN_DAP6_DIN_PP4,
912 };
913
914 static const unsigned int dap6_fs_pp5_pins[] = {
915 TEGRA_PIN_DAP6_FS_PP5,
916 };
917
918 static const unsigned int dap4_sclk_pp6_pins[] = {
919 TEGRA_PIN_DAP4_SCLK_PP6,
920 };
921
922 static const unsigned int dap4_dout_pp7_pins[] = {
923 TEGRA_PIN_DAP4_DOUT_PP7,
924 };
925
926 static const unsigned int dap4_din_pq0_pins[] = {
927 TEGRA_PIN_DAP4_DIN_PQ0,
928 };
929
930 static const unsigned int dap4_fs_pq1_pins[] = {
931 TEGRA_PIN_DAP4_FS_PQ1,
932 };
933
934 static const unsigned int spi5_sck_pq2_pins[] = {
935 TEGRA_PIN_SPI5_SCK_PQ2,
936 };
937
938 static const unsigned int spi5_miso_pq3_pins[] = {
939 TEGRA_PIN_SPI5_MISO_PQ3,
940 };
941
942 static const unsigned int spi5_mosi_pq4_pins[] = {
943 TEGRA_PIN_SPI5_MOSI_PQ4,
944 };
945
946 static const unsigned int spi5_cs0_pq5_pins[] = {
947 TEGRA_PIN_SPI5_CS0_PQ5,
948 };
949
950 static const unsigned int soc_gpio152_pq6_pins[] = {
951 TEGRA_PIN_SOC_GPIO152_PQ6,
952 };
953
954 static const unsigned int soc_gpio153_pq7_pins[] = {
955 TEGRA_PIN_SOC_GPIO153_PQ7,
956 };
957
958 static const unsigned int aud_mclk_pr0_pins[] = {
959 TEGRA_PIN_AUD_MCLK_PR0,
960 };
961
962 static const unsigned int soc_gpio155_pr1_pins[] = {
963 TEGRA_PIN_SOC_GPIO155_PR1,
964 };
965
966 static const unsigned int dap1_sclk_pr2_pins[] = {
967 TEGRA_PIN_DAP1_SCLK_PR2,
968 };
969
970 static const unsigned int dap1_out_pr3_pins[] = {
971 TEGRA_PIN_DAP1_OUT_PR3,
972 };
973
974 static const unsigned int dap1_in_pr4_pins[] = {
975 TEGRA_PIN_DAP1_IN_PR4,
976 };
977
978 static const unsigned int dap1_fs_pr5_pins[] = {
979 TEGRA_PIN_DAP1_FS_PR5,
980 };
981
982 static const unsigned int gen11_i2c_scl_pr6_pins[] = {
983 TEGRA_PIN_GEN11_I2C_SCL_PR6,
984 };
985
986 static const unsigned int gen11_i2c_sda_pr7_pins[] = {
987 TEGRA_PIN_GEN11_I2C_SDA_PR7,
988 };
989
990 static const unsigned int soc_gpio350_ps0_pins[] = {
991 TEGRA_PIN_SOC_GPIO350_PS0,
992 };
993
994 static const unsigned int soc_gpio351_ps1_pins[] = {
995 TEGRA_PIN_SOC_GPIO351_PS1,
996 };
997
998 static const unsigned int soc_gpio270_py0_pins[] = {
999 TEGRA_PIN_SOC_GPIO270_PY0,
1000 };
1001
1002 static const unsigned int soc_gpio271_py1_pins[] = {
1003 TEGRA_PIN_SOC_GPIO271_PY1,
1004 };
1005
1006 static const unsigned int soc_gpio272_py2_pins[] = {
1007 TEGRA_PIN_SOC_GPIO272_PY2,
1008 };
1009
1010 static const unsigned int soc_gpio273_py3_pins[] = {
1011 TEGRA_PIN_SOC_GPIO273_PY3,
1012 };
1013
1014 static const unsigned int soc_gpio274_py4_pins[] = {
1015 TEGRA_PIN_SOC_GPIO274_PY4,
1016 };
1017
1018 static const unsigned int soc_gpio275_py5_pins[] = {
1019 TEGRA_PIN_SOC_GPIO275_PY5,
1020 };
1021
1022 static const unsigned int soc_gpio276_py6_pins[] = {
1023 TEGRA_PIN_SOC_GPIO276_PY6,
1024 };
1025
1026 static const unsigned int soc_gpio277_py7_pins[] = {
1027 TEGRA_PIN_SOC_GPIO277_PY7,
1028 };
1029
1030 static const unsigned int soc_gpio278_pz0_pins[] = {
1031 TEGRA_PIN_SOC_GPIO278_PZ0,
1032 };
1033
1034 static const unsigned int soc_gpio279_pz1_pins[] = {
1035 TEGRA_PIN_SOC_GPIO279_PZ1,
1036 };
1037
1038 static const unsigned int xhalt_trig_pz2_pins[] = {
1039 TEGRA_PIN_XHALT_TRIG_PZ2,
1040 };
1041
1042 static const unsigned int soc_gpio281_pz3_pins[] = {
1043 TEGRA_PIN_SOC_GPIO281_PZ3,
1044 };
1045
1046 static const unsigned int soc_gpio282_pz4_pins[] = {
1047 TEGRA_PIN_SOC_GPIO282_PZ4,
1048 };
1049
1050 static const unsigned int soc_gpio283_pz5_pins[] = {
1051 TEGRA_PIN_SOC_GPIO283_PZ5,
1052 };
1053
1054 static const unsigned int soc_gpio284_pz6_pins[] = {
1055 TEGRA_PIN_SOC_GPIO284_PZ6,
1056 };
1057
1058 static const unsigned int soc_gpio285_pz7_pins[] = {
1059 TEGRA_PIN_SOC_GPIO285_PZ7,
1060 };
1061
1062 static const unsigned int soc_gpio286_pal0_pins[] = {
1063 TEGRA_PIN_SOC_GPIO286_PAL0,
1064 };
1065
1066 static const unsigned int soc_gpio287_pal1_pins[] = {
1067 TEGRA_PIN_SOC_GPIO287_PAL1,
1068 };
1069
1070 static const unsigned int soc_gpio288_pal2_pins[] = {
1071 TEGRA_PIN_SOC_GPIO288_PAL2,
1072 };
1073
1074 static const unsigned int soc_gpio00_paa0_pins[] = {
1075 TEGRA_PIN_SOC_GPIO00_PAA0,
1076 };
1077
1078 static const unsigned int vcomp_alert_paa1_pins[] = {
1079 TEGRA_PIN_VCOMP_ALERT_PAA1,
1080 };
1081
1082 static const unsigned int ao_retention_n_paa2_pins[] = {
1083 TEGRA_PIN_AO_RETENTION_N_PAA2,
1084 };
1085
1086 static const unsigned int batt_oc_paa3_pins[] = {
1087 TEGRA_PIN_BATT_OC_PAA3,
1088 };
1089
1090 static const unsigned int bootv_ctl_n_paa4_pins[] = {
1091 TEGRA_PIN_BOOTV_CTL_N_PAA4,
1092 };
1093
1094 static const unsigned int power_on_paa5_pins[] = {
1095 TEGRA_PIN_POWER_ON_PAA5,
1096 };
1097
1098 static const unsigned int hdmi_cec_paa6_pins[] = {
1099 TEGRA_PIN_HDMI_CEC_PAA6,
1100 };
1101
1102 static const unsigned int soc_gpio07_paa7_pins[] = {
1103 TEGRA_PIN_SOC_GPIO07_PAA7,
1104 };
1105
1106 static const unsigned int soc_gpio08_pbb0_pins[] = {
1107 TEGRA_PIN_SOC_GPIO08_PBB0,
1108 };
1109
1110 static const unsigned int soc_gpio09_pbb1_pins[] = {
1111 TEGRA_PIN_SOC_GPIO09_PBB1,
1112 };
1113
1114 static const unsigned int gen2_i2c_scl_pcc0_pins[] = {
1115 TEGRA_PIN_GEN2_I2C_SCL_PCC0,
1116 };
1117
1118 static const unsigned int gen2_i2c_sda_pcc1_pins[] = {
1119 TEGRA_PIN_GEN2_I2C_SDA_PCC1,
1120 };
1121
1122 static const unsigned int gen3_i2c_scl_pcc2_pins[] = {
1123 TEGRA_PIN_GEN3_I2C_SCL_PCC2,
1124 };
1125
1126 static const unsigned int gen3_i2c_sda_pcc3_pins[] = {
1127 TEGRA_PIN_GEN3_I2C_SDA_PCC3,
1128 };
1129
1130 static const unsigned int gp_pwm4_pcc4_pins[] = {
1131 TEGRA_PIN_GP_PWM4_PCC4,
1132 };
1133
1134 static const unsigned int uart0_tx_pcc5_pins[] = {
1135 TEGRA_PIN_UART0_TX_PCC5,
1136 };
1137
1138 static const unsigned int uart0_rx_pcc6_pins[] = {
1139 TEGRA_PIN_UART0_RX_PCC6,
1140 };
1141
1142 static const unsigned int spi2_sck_pcc7_pins[] = {
1143 TEGRA_PIN_SPI2_SCK_PCC7,
1144 };
1145
1146 static const unsigned int spi2_miso_pdd0_pins[] = {
1147 TEGRA_PIN_SPI2_MISO_PDD0,
1148 };
1149
1150 static const unsigned int spi2_mosi_pdd1_pins[] = {
1151 TEGRA_PIN_SPI2_MOSI_PDD1,
1152 };
1153
1154 static const unsigned int spi2_cs0_n_pdd2_pins[] = {
1155 TEGRA_PIN_SPI2_CS0_N_PDD2,
1156 };
1157
1158 static const unsigned int soc_gpio21_pdd3_pins[] = {
1159 TEGRA_PIN_SOC_GPIO21_PDD3,
1160 };
1161
1162 static const unsigned int soc_gpio22_pdd4_pins[] = {
1163 TEGRA_PIN_SOC_GPIO22_PDD4,
1164 };
1165
1166 static const unsigned int soc_gpio23_pdd5_pins[] = {
1167 TEGRA_PIN_SOC_GPIO23_PDD5,
1168 };
1169
1170 static const unsigned int soc_gpio24_pdd6_pins[] = {
1171 TEGRA_PIN_SOC_GPIO24_PDD6,
1172 };
1173
1174 static const unsigned int soc_gpio25_pdd7_pins[] = {
1175 TEGRA_PIN_SOC_GPIO25_PDD7,
1176 };
1177
1178 static const unsigned int soc_gpio26_pee0_pins[] = {
1179 TEGRA_PIN_SOC_GPIO26_PEE0,
1180 };
1181
1182 static const unsigned int soc_gpio27_pee1_pins[] = {
1183 TEGRA_PIN_SOC_GPIO27_PEE1,
1184 };
1185
1186 static const unsigned int soc_gpio28_pee2_pins[] = {
1187 TEGRA_PIN_SOC_GPIO28_PEE2,
1188 };
1189
1190 static const unsigned int soc_gpio29_pee3_pins[] = {
1191 TEGRA_PIN_SOC_GPIO29_PEE3,
1192 };
1193
1194 enum tegra_mux_dt {
1195 TEGRA_MUX_DCA_VSYNC,
1196 TEGRA_MUX_DCA_HSYNC,
1197 TEGRA_MUX_RSVD0,
1198 TEGRA_MUX_DP_AUX_CH0_HPD,
1199 TEGRA_MUX_DP_AUX_CH1_HPD,
1200 TEGRA_MUX_DP_AUX_CH2_HPD,
1201 TEGRA_MUX_DP_AUX_CH3_HPD,
1202 TEGRA_MUX_GP_PWM2,
1203 TEGRA_MUX_GP_PWM3,
1204 TEGRA_MUX_I2C7_CLK,
1205 TEGRA_MUX_I2C7_DAT,
1206 TEGRA_MUX_I2C9_CLK,
1207 TEGRA_MUX_I2C9_DAT,
1208 TEGRA_MUX_UARTK_CTS,
1209 TEGRA_MUX_UARTK_RTS,
1210 TEGRA_MUX_UARTK_RXD,
1211 TEGRA_MUX_UARTK_TXD,
1212 TEGRA_MUX_SPI3_CS0,
1213 TEGRA_MUX_SPI3_CS3,
1214 TEGRA_MUX_SPI3_DIN,
1215 TEGRA_MUX_SPI3_DOUT,
1216 TEGRA_MUX_SPI3_SCK,
1217 TEGRA_MUX_UARTF_CTS,
1218 TEGRA_MUX_UARTF_RTS,
1219 TEGRA_MUX_UARTF_RXD,
1220 TEGRA_MUX_UARTF_TXD,
1221 TEGRA_MUX_SPI1_CS0,
1222 TEGRA_MUX_SPI1_CS1,
1223 TEGRA_MUX_SPI1_DIN,
1224 TEGRA_MUX_SPI1_DOUT,
1225 TEGRA_MUX_SPI1_SCK,
1226 TEGRA_MUX_EXTPERIPH2_CLK,
1227 TEGRA_MUX_EXTPERIPH1_CLK,
1228 TEGRA_MUX_I2C12_CLK,
1229 TEGRA_MUX_I2C12_DAT,
1230 TEGRA_MUX_NV_THERM_FAN_TACH0,
1231 TEGRA_MUX_GP_PWM9,
1232 TEGRA_MUX_UARTJ_CTS,
1233 TEGRA_MUX_UARTJ_RTS,
1234 TEGRA_MUX_UARTJ_RXD,
1235 TEGRA_MUX_UARTJ_TXD,
1236 TEGRA_MUX_I2C0_CLK,
1237 TEGRA_MUX_I2C0_DAT,
1238 TEGRA_MUX_I2C1_CLK,
1239 TEGRA_MUX_I2C1_DAT,
1240 TEGRA_MUX_I2S2_LRCK,
1241 TEGRA_MUX_I2S2_SCLK,
1242 TEGRA_MUX_I2S2_SDATA_OUT,
1243 TEGRA_MUX_I2S2_SDATA_IN,
1244 TEGRA_MUX_GP_PWM10,
1245 TEGRA_MUX_UARTE_CTS,
1246 TEGRA_MUX_UARTE_RTS,
1247 TEGRA_MUX_UARTE_RXD,
1248 TEGRA_MUX_UARTE_TXD,
1249 TEGRA_MUX_I2C5_DAT,
1250 TEGRA_MUX_I2C5_CLK,
1251 TEGRA_MUX_I2S6_SDATA_IN,
1252 TEGRA_MUX_I2S6_SDATA_OUT,
1253 TEGRA_MUX_I2S6_LRCK,
1254 TEGRA_MUX_I2S6_SCLK,
1255 TEGRA_MUX_I2S4_SDATA_OUT,
1256 TEGRA_MUX_I2S4_SCLK,
1257 TEGRA_MUX_I2S4_SDATA_IN,
1258 TEGRA_MUX_I2S4_LRCK,
1259 TEGRA_MUX_SPI5_CS0,
1260 TEGRA_MUX_SPI5_DIN,
1261 TEGRA_MUX_SPI5_DOUT,
1262 TEGRA_MUX_SPI5_SCK,
1263 TEGRA_MUX_AUD_MCLK,
1264 TEGRA_MUX_I2S1_SCLK,
1265 TEGRA_MUX_I2S1_SDATA_IN,
1266 TEGRA_MUX_I2S1_SDATA_OUT,
1267 TEGRA_MUX_I2S1_LRCK,
1268 TEGRA_MUX_I2C11_CLK,
1269 TEGRA_MUX_I2C11_DAT,
1270 TEGRA_MUX_XHALT_TRIG,
1271 TEGRA_MUX_GP_PWM1,
1272 TEGRA_MUX_GP_PWM6,
1273 TEGRA_MUX_GP_PWM7,
1274 TEGRA_MUX_GP_PWM8,
1275 TEGRA_MUX_UFS0,
1276 TEGRA_MUX_PE1_CLKREQ_L,
1277 TEGRA_MUX_PE1_RST_L,
1278 TEGRA_MUX_PE2_RST_L,
1279 TEGRA_MUX_PE2_CLKREQ_L,
1280 TEGRA_MUX_PE3_CLKREQ_L,
1281 TEGRA_MUX_PE3_RST_L,
1282 TEGRA_MUX_SGMII0_SMA_MDIO,
1283 TEGRA_MUX_SGMII0_SMA_MDC,
1284 TEGRA_MUX_USB_VBUS_EN0,
1285 TEGRA_MUX_USB_VBUS_EN1,
1286 TEGRA_MUX_ETH1_MDIO,
1287 TEGRA_MUX_PE4_CLKREQ_L,
1288 TEGRA_MUX_PE4_RST_L,
1289 TEGRA_MUX_PE5_CLKREQ_L,
1290 TEGRA_MUX_PE5_RST_L,
1291 TEGRA_MUX_ETH0_MDIO,
1292 TEGRA_MUX_ETH0_MDC,
1293 TEGRA_MUX_ETH1_MDC,
1294 TEGRA_MUX_ETH2_MDIO,
1295 TEGRA_MUX_ETH2_MDC,
1296 TEGRA_MUX_ETH3_MDIO,
1297 TEGRA_MUX_ETH3_MDC,
1298 TEGRA_MUX_QSPI0_CS_N,
1299 TEGRA_MUX_QSPI0_IO0,
1300 TEGRA_MUX_QSPI0_IO1,
1301 TEGRA_MUX_QSPI0_IO2,
1302 TEGRA_MUX_QSPI0_IO3,
1303 TEGRA_MUX_QSPI0_SCK,
1304 TEGRA_MUX_SDMMC1_CLK,
1305 TEGRA_MUX_SDMMC1_CMD,
1306 TEGRA_MUX_SDMMC1_COMP,
1307 TEGRA_MUX_SDMMC1_DAT3,
1308 TEGRA_MUX_SDMMC1_DAT2,
1309 TEGRA_MUX_SDMMC1_DAT1,
1310 TEGRA_MUX_SDMMC1_DAT0,
1311 TEGRA_MUX_QSPI3_SCK,
1312 TEGRA_MUX_QSPI3_CS0,
1313 TEGRA_MUX_QSPI3_IO0,
1314 TEGRA_MUX_QSPI3_IO1,
1315 TEGRA_MUX_DCB_VSYNC,
1316 TEGRA_MUX_DCB_HSYNC,
1317 TEGRA_MUX_DSA_LSPII,
1318 TEGRA_MUX_DCE_VSYNC,
1319 TEGRA_MUX_DCE_HSYNC,
1320 TEGRA_MUX_DCH_VSYNC,
1321 TEGRA_MUX_DCH_HSYNC,
1322 TEGRA_MUX_BL_EN,
1323 TEGRA_MUX_BL_PWM_DIM0,
1324 TEGRA_MUX_RSVD1,
1325 TEGRA_MUX_SOC_THERM_OC3,
1326 TEGRA_MUX_I2S5_SCLK,
1327 TEGRA_MUX_I2S5_SDATA_IN,
1328 TEGRA_MUX_EXTPERIPH3_CLK,
1329 TEGRA_MUX_EXTPERIPH4_CLK,
1330 TEGRA_MUX_I2S5_SDATA_OUT,
1331 TEGRA_MUX_I2S5_LRCK,
1332 TEGRA_MUX_SDMMC1_CD,
1333 TEGRA_MUX_I2S7_SDATA_IN,
1334 TEGRA_MUX_SPI4_SCK,
1335 TEGRA_MUX_SPI4_DIN,
1336 TEGRA_MUX_SPI4_DOUT,
1337 TEGRA_MUX_SPI4_CS0,
1338 TEGRA_MUX_SPI4_CS1,
1339 TEGRA_MUX_GP_PWM5,
1340 TEGRA_MUX_I2C14_CLK,
1341 TEGRA_MUX_I2C14_DAT,
1342 TEGRA_MUX_I2S8_SCLK,
1343 TEGRA_MUX_I2S8_SDATA_OUT,
1344 TEGRA_MUX_I2S8_LRCK,
1345 TEGRA_MUX_I2S8_SDATA_IN,
1346 TEGRA_MUX_I2C16_CLK,
1347 TEGRA_MUX_I2C16_DAT,
1348 TEGRA_MUX_I2S3_SCLK,
1349 TEGRA_MUX_I2S3_SDATA_OUT,
1350 TEGRA_MUX_I2S3_SDATA_IN,
1351 TEGRA_MUX_I2S3_LRCK,
1352 TEGRA_MUX_PM_TRIG1,
1353 TEGRA_MUX_PM_TRIG0,
1354 TEGRA_MUX_QSPI2_SCK,
1355 TEGRA_MUX_QSPI2_CS0,
1356 TEGRA_MUX_QSPI2_IO0,
1357 TEGRA_MUX_QSPI2_IO1,
1358 TEGRA_MUX_DCC_VSYNC,
1359 TEGRA_MUX_DCC_HSYNC,
1360 TEGRA_MUX_RSVD2,
1361 TEGRA_MUX_DCF_VSYNC,
1362 TEGRA_MUX_DCF_HSYNC,
1363 TEGRA_MUX_SOUNDWIRE1_CLK,
1364 TEGRA_MUX_SOUNDWIRE1_DAT0,
1365 TEGRA_MUX_SOUNDWIRE1_DAT1,
1366 TEGRA_MUX_SOUNDWIRE1_DAT2,
1367 TEGRA_MUX_DMIC2_CLK,
1368 TEGRA_MUX_DMIC2_DAT,
1369 TEGRA_MUX_NV_THERM_FAN_TACH1,
1370 TEGRA_MUX_I2C15_CLK,
1371 TEGRA_MUX_I2C15_DAT,
1372 TEGRA_MUX_I2S7_LRCK,
1373 TEGRA_MUX_CCLA_LA_TRIGGER_MUX,
1374 TEGRA_MUX_I2S7_SCLK,
1375 TEGRA_MUX_I2S7_SDATA_OUT,
1376 TEGRA_MUX_DMIC1_DAT,
1377 TEGRA_MUX_DMIC1_CLK,
1378 TEGRA_MUX_DCD_VSYNC,
1379 TEGRA_MUX_DCD_HSYNC,
1380 TEGRA_MUX_RSVD3,
1381 TEGRA_MUX_DCG_VSYNC,
1382 TEGRA_MUX_DCG_HSYNC,
1383 TEGRA_MUX_DSPK1_CLK,
1384 TEGRA_MUX_DSPK1_DAT,
1385 TEGRA_MUX_SOC_THERM_OC2,
1386 TEGRA_MUX_ISTCTRL_IST_DONE_N,
1387 TEGRA_MUX_SOC_THERM_OC1,
1388 TEGRA_MUX_TSC_EDGE_OUT0C,
1389 TEGRA_MUX_TSC_EDGE_OUT0D,
1390 TEGRA_MUX_TSC_EDGE_OUT0A,
1391 TEGRA_MUX_TSC_EDGE_OUT0B,
1392 TEGRA_MUX_TOUCH_CLK,
1393 TEGRA_MUX_HDMI_CEC,
1394 TEGRA_MUX_I2C2_CLK,
1395 TEGRA_MUX_I2C2_DAT,
1396 TEGRA_MUX_I2C3_CLK,
1397 TEGRA_MUX_I2C3_DAT,
1398 TEGRA_MUX_GP_PWM4,
1399 TEGRA_MUX_UARTA_TXD,
1400 TEGRA_MUX_UARTA_RXD,
1401 TEGRA_MUX_SPI2_SCK,
1402 TEGRA_MUX_SPI2_DIN,
1403 TEGRA_MUX_SPI2_DOUT,
1404 TEGRA_MUX_SPI2_CS0,
1405 TEGRA_MUX_TSC_SYNC1,
1406 TEGRA_MUX_TSC_EDGE_OUT3,
1407 TEGRA_MUX_TSC_EDGE_OUT0,
1408 TEGRA_MUX_TSC_EDGE_OUT1,
1409 TEGRA_MUX_TSC_SYNC0,
1410 TEGRA_MUX_SOUNDWIRE0_CLK,
1411 TEGRA_MUX_SOUNDWIRE0_DAT0,
1412 TEGRA_MUX_L0L1_RST_OUT_N,
1413 TEGRA_MUX_L2_RST_OUT_N,
1414 TEGRA_MUX_UARTL_TXD,
1415 TEGRA_MUX_UARTL_RXD,
1416 TEGRA_MUX_I2S9_SCLK,
1417 TEGRA_MUX_I2S9_SDATA_OUT,
1418 TEGRA_MUX_I2S9_SDATA_IN,
1419 TEGRA_MUX_I2S9_LRCK,
1420 TEGRA_MUX_DMIC5_DAT,
1421 TEGRA_MUX_DMIC5_CLK,
1422 TEGRA_MUX_TSC_EDGE_OUT2,
1423 };
1424
1425 /* Make list of each function name */
1426 #define TEGRA_PIN_FUNCTION(lid) #lid
1427
1428 static const char * const tegra264_functions[] = {
1429 TEGRA_PIN_FUNCTION(dca_vsync),
1430 TEGRA_PIN_FUNCTION(dca_hsync),
1431 TEGRA_PIN_FUNCTION(rsvd0),
1432 TEGRA_PIN_FUNCTION(dp_aux_ch0_hpd),
1433 TEGRA_PIN_FUNCTION(dp_aux_ch1_hpd),
1434 TEGRA_PIN_FUNCTION(dp_aux_ch2_hpd),
1435 TEGRA_PIN_FUNCTION(dp_aux_ch3_hpd),
1436 TEGRA_PIN_FUNCTION(gp_pwm2),
1437 TEGRA_PIN_FUNCTION(gp_pwm3),
1438 TEGRA_PIN_FUNCTION(i2c7_clk),
1439 TEGRA_PIN_FUNCTION(i2c7_dat),
1440 TEGRA_PIN_FUNCTION(i2c9_clk),
1441 TEGRA_PIN_FUNCTION(i2c9_dat),
1442 TEGRA_PIN_FUNCTION(uartk_cts),
1443 TEGRA_PIN_FUNCTION(uartk_rts),
1444 TEGRA_PIN_FUNCTION(uartk_rxd),
1445 TEGRA_PIN_FUNCTION(uartk_txd),
1446 TEGRA_PIN_FUNCTION(spi3_cs0),
1447 TEGRA_PIN_FUNCTION(spi3_cs3),
1448 TEGRA_PIN_FUNCTION(spi3_din),
1449 TEGRA_PIN_FUNCTION(spi3_dout),
1450 TEGRA_PIN_FUNCTION(spi3_sck),
1451 TEGRA_PIN_FUNCTION(uartf_cts),
1452 TEGRA_PIN_FUNCTION(uartf_rts),
1453 TEGRA_PIN_FUNCTION(uartf_rxd),
1454 TEGRA_PIN_FUNCTION(uartf_txd),
1455 TEGRA_PIN_FUNCTION(spi1_cs0),
1456 TEGRA_PIN_FUNCTION(spi1_cs1),
1457 TEGRA_PIN_FUNCTION(spi1_din),
1458 TEGRA_PIN_FUNCTION(spi1_dout),
1459 TEGRA_PIN_FUNCTION(spi1_sck),
1460 TEGRA_PIN_FUNCTION(extperiph2_clk),
1461 TEGRA_PIN_FUNCTION(extperiph1_clk),
1462 TEGRA_PIN_FUNCTION(i2c12_clk),
1463 TEGRA_PIN_FUNCTION(i2c12_dat),
1464 TEGRA_PIN_FUNCTION(nv_therm_fan_tach0),
1465 TEGRA_PIN_FUNCTION(gp_pwm9),
1466 TEGRA_PIN_FUNCTION(uartj_cts),
1467 TEGRA_PIN_FUNCTION(uartj_rts),
1468 TEGRA_PIN_FUNCTION(uartj_rxd),
1469 TEGRA_PIN_FUNCTION(uartj_txd),
1470 TEGRA_PIN_FUNCTION(i2c0_clk),
1471 TEGRA_PIN_FUNCTION(i2c0_dat),
1472 TEGRA_PIN_FUNCTION(i2c1_clk),
1473 TEGRA_PIN_FUNCTION(i2c1_dat),
1474 TEGRA_PIN_FUNCTION(i2s2_lrck),
1475 TEGRA_PIN_FUNCTION(i2s2_sclk),
1476 TEGRA_PIN_FUNCTION(i2s2_sdata_out),
1477 TEGRA_PIN_FUNCTION(i2s2_sdata_in),
1478 TEGRA_PIN_FUNCTION(gp_pwm10),
1479 TEGRA_PIN_FUNCTION(uarte_cts),
1480 TEGRA_PIN_FUNCTION(uarte_rts),
1481 TEGRA_PIN_FUNCTION(uarte_rxd),
1482 TEGRA_PIN_FUNCTION(uarte_txd),
1483 TEGRA_PIN_FUNCTION(i2c5_dat),
1484 TEGRA_PIN_FUNCTION(i2c5_clk),
1485 TEGRA_PIN_FUNCTION(i2s6_sdata_in),
1486 TEGRA_PIN_FUNCTION(i2s6_sdata_out),
1487 TEGRA_PIN_FUNCTION(i2s6_lrck),
1488 TEGRA_PIN_FUNCTION(i2s6_sclk),
1489 TEGRA_PIN_FUNCTION(i2s4_sdata_out),
1490 TEGRA_PIN_FUNCTION(i2s4_sclk),
1491 TEGRA_PIN_FUNCTION(i2s4_sdata_in),
1492 TEGRA_PIN_FUNCTION(i2s4_lrck),
1493 TEGRA_PIN_FUNCTION(spi5_cs0),
1494 TEGRA_PIN_FUNCTION(spi5_din),
1495 TEGRA_PIN_FUNCTION(spi5_dout),
1496 TEGRA_PIN_FUNCTION(spi5_sck),
1497 TEGRA_PIN_FUNCTION(aud_mclk),
1498 TEGRA_PIN_FUNCTION(i2s1_sclk),
1499 TEGRA_PIN_FUNCTION(i2s1_sdata_in),
1500 TEGRA_PIN_FUNCTION(i2s1_sdata_out),
1501 TEGRA_PIN_FUNCTION(i2s1_lrck),
1502 TEGRA_PIN_FUNCTION(i2c11_clk),
1503 TEGRA_PIN_FUNCTION(i2c11_dat),
1504 TEGRA_PIN_FUNCTION(xhalt_trig),
1505 TEGRA_PIN_FUNCTION(gp_pwm1),
1506 TEGRA_PIN_FUNCTION(gp_pwm6),
1507 TEGRA_PIN_FUNCTION(gp_pwm7),
1508 TEGRA_PIN_FUNCTION(gp_pwm8),
1509 TEGRA_PIN_FUNCTION(ufs0),
1510 TEGRA_PIN_FUNCTION(pe1_clkreq_l),
1511 TEGRA_PIN_FUNCTION(pe1_rst_l),
1512 TEGRA_PIN_FUNCTION(pe2_rst_l),
1513 TEGRA_PIN_FUNCTION(pe2_clkreq_l),
1514 TEGRA_PIN_FUNCTION(pe3_clkreq_l),
1515 TEGRA_PIN_FUNCTION(pe3_rst_l),
1516 TEGRA_PIN_FUNCTION(sgmii0_sma_mdio),
1517 TEGRA_PIN_FUNCTION(sgmii0_sma_mdc),
1518 TEGRA_PIN_FUNCTION(usb_vbus_en0),
1519 TEGRA_PIN_FUNCTION(usb_vbus_en1),
1520 TEGRA_PIN_FUNCTION(eth1_mdio),
1521 TEGRA_PIN_FUNCTION(pe4_clkreq_l),
1522 TEGRA_PIN_FUNCTION(pe4_rst_l),
1523 TEGRA_PIN_FUNCTION(pe5_clkreq_l),
1524 TEGRA_PIN_FUNCTION(pe5_rst_l),
1525 TEGRA_PIN_FUNCTION(eth0_mdio),
1526 TEGRA_PIN_FUNCTION(eth0_mdc),
1527 TEGRA_PIN_FUNCTION(eth1_mdc),
1528 TEGRA_PIN_FUNCTION(eth2_mdio),
1529 TEGRA_PIN_FUNCTION(eth2_mdc),
1530 TEGRA_PIN_FUNCTION(eth3_mdio),
1531 TEGRA_PIN_FUNCTION(eth3_mdc),
1532 TEGRA_PIN_FUNCTION(qspi0_cs_n),
1533 TEGRA_PIN_FUNCTION(qspi0_io0),
1534 TEGRA_PIN_FUNCTION(qspi0_io1),
1535 TEGRA_PIN_FUNCTION(qspi0_io2),
1536 TEGRA_PIN_FUNCTION(qspi0_io3),
1537 TEGRA_PIN_FUNCTION(qspi0_sck),
1538 TEGRA_PIN_FUNCTION(sdmmc1_clk),
1539 TEGRA_PIN_FUNCTION(sdmmc1_cmd),
1540 TEGRA_PIN_FUNCTION(sdmmc1_comp),
1541 TEGRA_PIN_FUNCTION(sdmmc1_dat3),
1542 TEGRA_PIN_FUNCTION(sdmmc1_dat2),
1543 TEGRA_PIN_FUNCTION(sdmmc1_dat1),
1544 TEGRA_PIN_FUNCTION(sdmmc1_dat0),
1545 TEGRA_PIN_FUNCTION(qspi3_sck),
1546 TEGRA_PIN_FUNCTION(qspi3_cs0),
1547 TEGRA_PIN_FUNCTION(qspi3_io0),
1548 TEGRA_PIN_FUNCTION(qspi3_io1),
1549 TEGRA_PIN_FUNCTION(dcb_vsync),
1550 TEGRA_PIN_FUNCTION(dcb_hsync),
1551 TEGRA_PIN_FUNCTION(dsa_lspii),
1552 TEGRA_PIN_FUNCTION(dce_vsync),
1553 TEGRA_PIN_FUNCTION(dce_hsync),
1554 TEGRA_PIN_FUNCTION(dch_vsync),
1555 TEGRA_PIN_FUNCTION(dch_hsync),
1556 TEGRA_PIN_FUNCTION(bl_en),
1557 TEGRA_PIN_FUNCTION(bl_pwm_dim0),
1558 TEGRA_PIN_FUNCTION(rsvd1),
1559 TEGRA_PIN_FUNCTION(soc_therm_oc3),
1560 TEGRA_PIN_FUNCTION(i2s5_sclk),
1561 TEGRA_PIN_FUNCTION(i2s5_sdata_in),
1562 TEGRA_PIN_FUNCTION(extperiph3_clk),
1563 TEGRA_PIN_FUNCTION(extperiph4_clk),
1564 TEGRA_PIN_FUNCTION(i2s5_sdata_out),
1565 TEGRA_PIN_FUNCTION(i2s5_lrck),
1566 TEGRA_PIN_FUNCTION(sdmmc1_cd),
1567 TEGRA_PIN_FUNCTION(i2s7_sdata_in),
1568 TEGRA_PIN_FUNCTION(spi4_sck),
1569 TEGRA_PIN_FUNCTION(spi4_din),
1570 TEGRA_PIN_FUNCTION(spi4_dout),
1571 TEGRA_PIN_FUNCTION(spi4_cs0),
1572 TEGRA_PIN_FUNCTION(spi4_cs1),
1573 TEGRA_PIN_FUNCTION(gp_pwm5),
1574 TEGRA_PIN_FUNCTION(i2c14_clk),
1575 TEGRA_PIN_FUNCTION(i2c14_dat),
1576 TEGRA_PIN_FUNCTION(i2s8_sclk),
1577 TEGRA_PIN_FUNCTION(i2s8_sdata_out),
1578 TEGRA_PIN_FUNCTION(i2s8_lrck),
1579 TEGRA_PIN_FUNCTION(i2s8_sdata_in),
1580 TEGRA_PIN_FUNCTION(i2c16_clk),
1581 TEGRA_PIN_FUNCTION(i2c16_dat),
1582 TEGRA_PIN_FUNCTION(i2s3_sclk),
1583 TEGRA_PIN_FUNCTION(i2s3_sdata_out),
1584 TEGRA_PIN_FUNCTION(i2s3_sdata_in),
1585 TEGRA_PIN_FUNCTION(i2s3_lrck),
1586 TEGRA_PIN_FUNCTION(pm_trig1),
1587 TEGRA_PIN_FUNCTION(pm_trig0),
1588 TEGRA_PIN_FUNCTION(qspi2_sck),
1589 TEGRA_PIN_FUNCTION(qspi2_cs0),
1590 TEGRA_PIN_FUNCTION(qspi2_io0),
1591 TEGRA_PIN_FUNCTION(qspi2_io1),
1592 TEGRA_PIN_FUNCTION(dcc_vsync),
1593 TEGRA_PIN_FUNCTION(dcc_hsync),
1594 TEGRA_PIN_FUNCTION(rsvd2),
1595 TEGRA_PIN_FUNCTION(dcf_vsync),
1596 TEGRA_PIN_FUNCTION(dcf_hsync),
1597 TEGRA_PIN_FUNCTION(soundwire1_clk),
1598 TEGRA_PIN_FUNCTION(soundwire1_dat0),
1599 TEGRA_PIN_FUNCTION(soundwire1_dat1),
1600 TEGRA_PIN_FUNCTION(soundwire1_dat2),
1601 TEGRA_PIN_FUNCTION(dmic2_clk),
1602 TEGRA_PIN_FUNCTION(dmic2_dat),
1603 TEGRA_PIN_FUNCTION(nv_therm_fan_tach1),
1604 TEGRA_PIN_FUNCTION(i2c15_clk),
1605 TEGRA_PIN_FUNCTION(i2c15_dat),
1606 TEGRA_PIN_FUNCTION(i2s7_lrck),
1607 TEGRA_PIN_FUNCTION(ccla_la_trigger_mux),
1608 TEGRA_PIN_FUNCTION(i2s7_sclk),
1609 TEGRA_PIN_FUNCTION(i2s7_sdata_out),
1610 TEGRA_PIN_FUNCTION(dmic1_dat),
1611 TEGRA_PIN_FUNCTION(dmic1_clk),
1612 TEGRA_PIN_FUNCTION(dcd_vsync),
1613 TEGRA_PIN_FUNCTION(dcd_hsync),
1614 TEGRA_PIN_FUNCTION(rsvd3),
1615 TEGRA_PIN_FUNCTION(dcg_vsync),
1616 TEGRA_PIN_FUNCTION(dcg_hsync),
1617 TEGRA_PIN_FUNCTION(dspk1_clk),
1618 TEGRA_PIN_FUNCTION(dspk1_dat),
1619 TEGRA_PIN_FUNCTION(soc_therm_oc2),
1620 TEGRA_PIN_FUNCTION(istctrl_ist_done_n),
1621 TEGRA_PIN_FUNCTION(soc_therm_oc1),
1622 TEGRA_PIN_FUNCTION(tsc_edge_out0c),
1623 TEGRA_PIN_FUNCTION(tsc_edge_out0d),
1624 TEGRA_PIN_FUNCTION(tsc_edge_out0a),
1625 TEGRA_PIN_FUNCTION(tsc_edge_out0b),
1626 TEGRA_PIN_FUNCTION(touch_clk),
1627 TEGRA_PIN_FUNCTION(hdmi_cec),
1628 TEGRA_PIN_FUNCTION(i2c2_clk),
1629 TEGRA_PIN_FUNCTION(i2c2_dat),
1630 TEGRA_PIN_FUNCTION(i2c3_clk),
1631 TEGRA_PIN_FUNCTION(i2c3_dat),
1632 TEGRA_PIN_FUNCTION(gp_pwm4),
1633 TEGRA_PIN_FUNCTION(uarta_txd),
1634 TEGRA_PIN_FUNCTION(uarta_rxd),
1635 TEGRA_PIN_FUNCTION(spi2_sck),
1636 TEGRA_PIN_FUNCTION(spi2_din),
1637 TEGRA_PIN_FUNCTION(spi2_dout),
1638 TEGRA_PIN_FUNCTION(spi2_cs0),
1639 TEGRA_PIN_FUNCTION(tsc_sync1),
1640 TEGRA_PIN_FUNCTION(tsc_edge_out3),
1641 TEGRA_PIN_FUNCTION(tsc_edge_out0),
1642 TEGRA_PIN_FUNCTION(tsc_edge_out1),
1643 TEGRA_PIN_FUNCTION(tsc_sync0),
1644 TEGRA_PIN_FUNCTION(soundwire0_clk),
1645 TEGRA_PIN_FUNCTION(soundwire0_dat0),
1646 TEGRA_PIN_FUNCTION(l0l1_rst_out_n),
1647 TEGRA_PIN_FUNCTION(l2_rst_out_n),
1648 TEGRA_PIN_FUNCTION(uartl_txd),
1649 TEGRA_PIN_FUNCTION(uartl_rxd),
1650 TEGRA_PIN_FUNCTION(i2s9_sclk),
1651 TEGRA_PIN_FUNCTION(i2s9_sdata_out),
1652 TEGRA_PIN_FUNCTION(i2s9_sdata_in),
1653 TEGRA_PIN_FUNCTION(i2s9_lrck),
1654 TEGRA_PIN_FUNCTION(dmic5_dat),
1655 TEGRA_PIN_FUNCTION(dmic5_clk),
1656 TEGRA_PIN_FUNCTION(tsc_edge_out2),
1657 };
1658
1659 #define PINGROUP_REG_Y(r) ((r))
1660 #define PINGROUP_REG_N(r) -1
1661
1662 #define DRV_PINGROUP_Y(r) ((r))
1663
1664 #define DRV_PINGROUP_ENTRY_N \
1665 .drv_reg = -1, \
1666 .drv_bank = -1, \
1667 .drvdn_bit = -1, \
1668 .drvup_bit = -1, \
1669 .slwr_bit = -1, \
1670 .slwf_bit = -1
1671
1672 #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
1673 drvup_w, slwr_b, slwr_w, slwf_b, \
1674 slwf_w, bank) \
1675 .drv_reg = DRV_PINGROUP_Y(r), \
1676 .drv_bank = bank, \
1677 .drvdn_bit = drvdn_b, \
1678 .drvdn_width = drvdn_w, \
1679 .drvup_bit = drvup_b, \
1680 .drvup_width = drvup_w, \
1681 .slwr_bit = slwr_b, \
1682 .slwr_width = slwr_w, \
1683 .slwf_bit = slwf_b, \
1684 .slwf_width = slwf_w
1685
1686 #define PIN_PINGROUP_ENTRY_N \
1687 .mux_reg = -1, \
1688 .pupd_reg = -1, \
1689 .tri_reg = -1, \
1690 .einput_bit = -1, \
1691 .e_io_hv_bit = -1, \
1692 .odrain_bit = -1, \
1693 .lock_bit = -1, \
1694 .parked_bit = -1, \
1695 .lpmd_bit = -1, \
1696 .drvtype_bit = -1, \
1697 .lpdr_bit = -1, \
1698 .pbias_buf_bit = -1, \
1699 .preemp_bit = -1, \
1700 .rfu_in_bit = -1
1701
1702 #define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \
1703 e_lpdr, e_pbias_buf, gpio_sfio_sel, \
1704 schmitt_b) \
1705 .mux_reg = PINGROUP_REG_Y(r), \
1706 .lpmd_bit = -1, \
1707 .lock_bit = -1, \
1708 .hsm_bit = -1, \
1709 .mux_bank = bank, \
1710 .mux_bit = 0, \
1711 .pupd_reg = PINGROUP_REG_##pupd(r), \
1712 .pupd_bank = bank, \
1713 .pupd_bit = 2, \
1714 .tri_reg = PINGROUP_REG_Y(r), \
1715 .tri_bank = bank, \
1716 .tri_bit = 4, \
1717 .einput_bit = e_input, \
1718 .sfsel_bit = gpio_sfio_sel, \
1719 .schmitt_bit = schmitt_b, \
1720 .drvtype_bit = 13, \
1721 .lpdr_bit = e_lpdr,
1722
1723 #define drive_eth1_mdio_pe0 DRV_PINGROUP_ENTRY_Y(0x4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1724 #define drive_pex_l4_clkreq_n_pd0 DRV_PINGROUP_ENTRY_Y(0xc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1725 #define drive_pex_l4_rst_n_pd1 DRV_PINGROUP_ENTRY_Y(0x14, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1726 #define drive_pex_l5_clkreq_n_pd2 DRV_PINGROUP_ENTRY_Y(0x1c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1727 #define drive_pex_l5_rst_n_pd3 DRV_PINGROUP_ENTRY_Y(0x24, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1728 #define drive_eth0_mdio_pd4 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1729 #define drive_eth0_mdc_pd5 DRV_PINGROUP_ENTRY_Y(0x34, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1730 #define drive_eth1_mdc_pe1 DRV_PINGROUP_ENTRY_Y(0x3c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1731 #define drive_eth2_mdio_pe2 DRV_PINGROUP_ENTRY_Y(0x44, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1732 #define drive_eth2_mdc_pe3 DRV_PINGROUP_ENTRY_Y(0x4c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1733 #define drive_eth3_mdio_pd6 DRV_PINGROUP_ENTRY_Y(0x54, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1734 #define drive_eth3_mdc_pd7 DRV_PINGROUP_ENTRY_Y(0x5c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1735 #define drive_pex_l1_clkreq_n_pb0 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1736 #define drive_pex_l1_rst_n_pb1 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1737 #define drive_pex_wake_n_pc2 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1738 #define drive_pex_l2_rst_n_pb3 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1739 #define drive_pex_l2_clkreq_n_pb2 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1740 #define drive_pex_l3_clkreq_n_pb4 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1741 #define drive_pex_l3_rst_n_pb5 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1742 #define drive_sgmii0_sma_mdio_pc0 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1743 #define drive_sgmii0_sma_mdc_pc1 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1744 #define drive_soc_gpio113_pb6 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1745 #define drive_soc_gpio114_pb7 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1746 #define drive_pwm1_pa0 DRV_PINGROUP_ENTRY_Y(0x3004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1747 #define drive_pwm6_pa1 DRV_PINGROUP_ENTRY_Y(0x300c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1748 #define drive_pwm7_pa2 DRV_PINGROUP_ENTRY_Y(0x3014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1749 #define drive_pwm8_pa3 DRV_PINGROUP_ENTRY_Y(0x301c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1750 #define drive_ufs0_ref_clk_pa4 DRV_PINGROUP_ENTRY_Y(0x3024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1751 #define drive_ufs0_rst_n_pa5 DRV_PINGROUP_ENTRY_Y(0x302c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1752
1753 #define drive_cpu_pwr_req_ph0 DRV_PINGROUP_ENTRY_Y(0x4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1754 #define drive_gpu_pwr_req_ph1 DRV_PINGROUP_ENTRY_Y(0xc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1755 #define drive_uart10_cts_n_ph5 DRV_PINGROUP_ENTRY_Y(0x14, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1756 #define drive_uart10_rts_n_ph4 DRV_PINGROUP_ENTRY_Y(0x1c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1757 #define drive_uart10_rx_ph3 DRV_PINGROUP_ENTRY_Y(0x24, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1758 #define drive_uart10_tx_ph2 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1759 #define drive_spi3_cs0_pj1 DRV_PINGROUP_ENTRY_Y(0x34, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1760 #define drive_spi3_cs3_pj2 DRV_PINGROUP_ENTRY_Y(0x3c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1761 #define drive_spi3_miso_ph7 DRV_PINGROUP_ENTRY_Y(0x44, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1762 #define drive_spi3_mosi_pj0 DRV_PINGROUP_ENTRY_Y(0x4c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1763 #define drive_spi3_sck_ph6 DRV_PINGROUP_ENTRY_Y(0x54, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1764 #define drive_uart5_cts_n_pj6 DRV_PINGROUP_ENTRY_Y(0x5c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1765 #define drive_uart5_rts_n_pj5 DRV_PINGROUP_ENTRY_Y(0x64, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1766 #define drive_uart5_rx_pj4 DRV_PINGROUP_ENTRY_Y(0x6c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1767 #define drive_uart5_tx_pj3 DRV_PINGROUP_ENTRY_Y(0x74, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1768 #define drive_spi1_cs0_pk2 DRV_PINGROUP_ENTRY_Y(0x7c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1769 #define drive_spi1_cs1_pk3 DRV_PINGROUP_ENTRY_Y(0x84, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1770 #define drive_spi1_miso_pk0 DRV_PINGROUP_ENTRY_Y(0x8c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1771 #define drive_spi1_mosi_pk1 DRV_PINGROUP_ENTRY_Y(0x94, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1772 #define drive_spi1_sck_pj7 DRV_PINGROUP_ENTRY_Y(0x9c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1773 #define drive_extperiph2_clk_pk5 DRV_PINGROUP_ENTRY_Y(0xa4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1774 #define drive_extperiph1_clk_pk4 DRV_PINGROUP_ENTRY_Y(0xac, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1775 #define drive_gen12_i2c_scl_pk6 DRV_PINGROUP_ENTRY_Y(0xb4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1776 #define drive_gen12_i2c_sda_pk7 DRV_PINGROUP_ENTRY_Y(0xbc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1777 #define drive_soc_gpio124_pl0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1778 #define drive_soc_gpio125_pl1 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1779 #define drive_fan_tach0_pl2 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1780 #define drive_soc_gpio127_pl3 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1781 #define drive_soc_gpio128_pl4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1782 #define drive_soc_gpio129_pl5 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1783 #define drive_soc_gpio130_pl6 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1784 #define drive_soc_gpio131_pl7 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1785 #define drive_gp_pwm9_pm0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1786 #define drive_soc_gpio133_pm1 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1787 #define drive_uart9_cts_n_pm5 DRV_PINGROUP_ENTRY_Y(0x1054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1788 #define drive_uart9_rts_n_pm4 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1789 #define drive_uart9_rx_pm3 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1790 #define drive_uart9_tx_pm2 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1791 #define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N
1792 #define drive_sdmmc1_clk_px0 DRV_PINGROUP_ENTRY_Y(0x2004, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1793 #define drive_sdmmc1_cmd_px1 DRV_PINGROUP_ENTRY_Y(0x200c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1794 #define drive_sdmmc1_dat3_px5 DRV_PINGROUP_ENTRY_Y(0x201c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1795 #define drive_sdmmc1_dat2_px4 DRV_PINGROUP_ENTRY_Y(0x2024, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1796 #define drive_sdmmc1_dat1_px3 DRV_PINGROUP_ENTRY_Y(0x202c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1797 #define drive_sdmmc1_dat0_px2 DRV_PINGROUP_ENTRY_Y(0x2034, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1798 #define drive_qspi0_cs_n_pt1 DRV_PINGROUP_ENTRY_Y(0x3004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1799 #define drive_qspi0_io0_pt2 DRV_PINGROUP_ENTRY_Y(0x300c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1800 #define drive_qspi0_io1_pt3 DRV_PINGROUP_ENTRY_Y(0x3014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1801 #define drive_qspi0_io2_pt4 DRV_PINGROUP_ENTRY_Y(0x301c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1802 #define drive_qspi0_io3_pt5 DRV_PINGROUP_ENTRY_Y(0x3024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1803 #define drive_qspi0_sck_pt0 DRV_PINGROUP_ENTRY_Y(0x302c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1804 #define drive_soc_gpio192_pt6 DRV_PINGROUP_ENTRY_Y(0x3034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1805 #define drive_soc_gpio138_pp0 DRV_PINGROUP_ENTRY_Y(0x5004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1806 #define drive_soc_gpio139_pp1 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1807 #define drive_dap6_din_pp4 DRV_PINGROUP_ENTRY_Y(0x5014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1808 #define drive_dap6_dout_pp3 DRV_PINGROUP_ENTRY_Y(0x501c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1809 #define drive_dap6_fs_pp5 DRV_PINGROUP_ENTRY_Y(0x5024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1810 #define drive_dap6_sclk_pp2 DRV_PINGROUP_ENTRY_Y(0x502c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1811 #define drive_dap4_dout_pp7 DRV_PINGROUP_ENTRY_Y(0x5034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1812 #define drive_dap4_sclk_pp6 DRV_PINGROUP_ENTRY_Y(0x503c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1813 #define drive_dap4_din_pq0 DRV_PINGROUP_ENTRY_Y(0x5044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1814 #define drive_dap4_fs_pq1 DRV_PINGROUP_ENTRY_Y(0x504c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1815 #define drive_spi5_cs0_pq5 DRV_PINGROUP_ENTRY_Y(0x5054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1816 #define drive_spi5_miso_pq3 DRV_PINGROUP_ENTRY_Y(0x505c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1817 #define drive_spi5_mosi_pq4 DRV_PINGROUP_ENTRY_Y(0x5064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1818 #define drive_spi5_sck_pq2 DRV_PINGROUP_ENTRY_Y(0x506c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1819 #define drive_soc_gpio152_pq6 DRV_PINGROUP_ENTRY_Y(0x5074, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1820 #define drive_soc_gpio153_pq7 DRV_PINGROUP_ENTRY_Y(0x507c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1821 #define drive_soc_gpio155_pr1 DRV_PINGROUP_ENTRY_Y(0x5084, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1822 #define drive_aud_mclk_pr0 DRV_PINGROUP_ENTRY_Y(0x508c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1823 #define drive_dap1_sclk_pr2 DRV_PINGROUP_ENTRY_Y(0x5094, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1824 #define drive_dap1_in_pr4 DRV_PINGROUP_ENTRY_Y(0x509c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1825 #define drive_dap1_out_pr3 DRV_PINGROUP_ENTRY_Y(0x50a4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1826 #define drive_dap1_fs_pr5 DRV_PINGROUP_ENTRY_Y(0x50ac, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1827 #define drive_gen11_i2c_scl_pr6 DRV_PINGROUP_ENTRY_Y(0x50b4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1828 #define drive_gen11_i2c_sda_pr7 DRV_PINGROUP_ENTRY_Y(0x50bc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1829 #define drive_soc_gpio350_ps0 DRV_PINGROUP_ENTRY_Y(0x50c4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1830 #define drive_soc_gpio351_ps1 DRV_PINGROUP_ENTRY_Y(0x50cc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1831 #define drive_gen0_i2c_scl_pw4 DRV_PINGROUP_ENTRY_Y(0x6004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1832 #define drive_gen0_i2c_sda_pw5 DRV_PINGROUP_ENTRY_Y(0x600c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1833 #define drive_gen1_i2c_scl_pw2 DRV_PINGROUP_ENTRY_Y(0x6014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1834 #define drive_gen1_i2c_sda_pw3 DRV_PINGROUP_ENTRY_Y(0x601c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1835 #define drive_dap2_fs_pw1 DRV_PINGROUP_ENTRY_Y(0x6044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1836 #define drive_dap2_clk_pv6 DRV_PINGROUP_ENTRY_Y(0x604c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1837 #define drive_dap2_din_pv7 DRV_PINGROUP_ENTRY_Y(0x6054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1838 #define drive_dap2_dout_pw0 DRV_PINGROUP_ENTRY_Y(0x605c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1839 #define drive_pwm10_pv1 DRV_PINGROUP_ENTRY_Y(0x6064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1840 #define drive_soc_gpio170_pu0 DRV_PINGROUP_ENTRY_Y(0x606c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1841 #define drive_soc_gpio171_pu1 DRV_PINGROUP_ENTRY_Y(0x6074, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1842 #define drive_soc_gpio172_pu2 DRV_PINGROUP_ENTRY_Y(0x607c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1843 #define drive_soc_gpio173_pu3 DRV_PINGROUP_ENTRY_Y(0x6084, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1844 #define drive_soc_gpio174_pu4 DRV_PINGROUP_ENTRY_Y(0x608c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1845 #define drive_soc_gpio175_pu5 DRV_PINGROUP_ENTRY_Y(0x6094, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1846 #define drive_soc_gpio176_pu6 DRV_PINGROUP_ENTRY_Y(0x609c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1847 #define drive_soc_gpio177_pu7 DRV_PINGROUP_ENTRY_Y(0x60a4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1848 #define drive_soc_gpio178_pv0 DRV_PINGROUP_ENTRY_Y(0x60ac, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1849 #define drive_uart4_cts_n_pv5 DRV_PINGROUP_ENTRY_Y(0x60b4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1850 #define drive_uart4_rts_n_pv4 DRV_PINGROUP_ENTRY_Y(0x60bc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1851 #define drive_uart4_rx_pv3 DRV_PINGROUP_ENTRY_Y(0x60c4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1852 #define drive_uart4_tx_pv2 DRV_PINGROUP_ENTRY_Y(0x60cc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1853 #define drive_pwr_i2c_sda_pw7 DRV_PINGROUP_ENTRY_Y(0x60d4, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1854 #define drive_pwr_i2c_scl_pw6 DRV_PINGROUP_ENTRY_Y(0x60dc, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1855 #define drive_soc_gpio250_pf0 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1856 #define drive_soc_gpio251_pf1 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1857 #define drive_soc_gpio252_pf2 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1858 #define drive_dp_aux_ch0_hpd_pf3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1859 #define drive_dp_aux_ch1_hpd_pf4 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1860 #define drive_dp_aux_ch2_hpd_pf5 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1861 #define drive_dp_aux_ch3_hpd_pf6 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1862 #define drive_pwm2_pf7 DRV_PINGROUP_ENTRY_Y(0x703c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1863 #define drive_pwm3_pg0 DRV_PINGROUP_ENTRY_Y(0x7044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1864 #define drive_gen7_i2c_scl_pg1 DRV_PINGROUP_ENTRY_Y(0x704c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1865 #define drive_gen7_i2c_sda_pg2 DRV_PINGROUP_ENTRY_Y(0x7054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1866 #define drive_gen9_i2c_scl_pg3 DRV_PINGROUP_ENTRY_Y(0x705c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1867 #define drive_gen9_i2c_sda_pg4 DRV_PINGROUP_ENTRY_Y(0x7064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1868 #define drive_soc_gpio270_py0 DRV_PINGROUP_ENTRY_Y(0xa004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1869 #define drive_soc_gpio271_py1 DRV_PINGROUP_ENTRY_Y(0xa00c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1870 #define drive_soc_gpio272_py2 DRV_PINGROUP_ENTRY_Y(0xa014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1871 #define drive_soc_gpio273_py3 DRV_PINGROUP_ENTRY_Y(0xa01c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1872 #define drive_soc_gpio274_py4 DRV_PINGROUP_ENTRY_Y(0xa024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1873 #define drive_soc_gpio275_py5 DRV_PINGROUP_ENTRY_Y(0xa02c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1874 #define drive_soc_gpio276_py6 DRV_PINGROUP_ENTRY_Y(0xa034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1875 #define drive_soc_gpio277_py7 DRV_PINGROUP_ENTRY_Y(0xa03c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1876 #define drive_soc_gpio278_pz0 DRV_PINGROUP_ENTRY_Y(0xa044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1877 #define drive_soc_gpio279_pz1 DRV_PINGROUP_ENTRY_Y(0xa04c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1878 #define drive_soc_gpio282_pz4 DRV_PINGROUP_ENTRY_Y(0xa054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1879 #define drive_soc_gpio283_pz5 DRV_PINGROUP_ENTRY_Y(0xa05c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1880 #define drive_soc_gpio284_pz6 DRV_PINGROUP_ENTRY_Y(0xa064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1881 #define drive_soc_gpio285_pz7 DRV_PINGROUP_ENTRY_Y(0xa06c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1882 #define drive_soc_gpio286_pal0 DRV_PINGROUP_ENTRY_Y(0xa074, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1883 #define drive_soc_gpio287_pal1 DRV_PINGROUP_ENTRY_Y(0xa07c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1884 #define drive_soc_gpio288_pal2 DRV_PINGROUP_ENTRY_Y(0xa084, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1885 #define drive_xhalt_trig_pz2 DRV_PINGROUP_ENTRY_Y(0xa08c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1886 #define drive_soc_gpio281_pz3 DRV_PINGROUP_ENTRY_Y(0xa094, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1887
1888 #define drive_ao_retention_n_paa2 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1889 #define drive_batt_oc_paa3 DRV_PINGROUP_ENTRY_Y(0x34, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1890 #define drive_power_on_paa5 DRV_PINGROUP_ENTRY_Y(0x3c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1891 #define drive_vcomp_alert_paa1 DRV_PINGROUP_ENTRY_Y(0x44, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1892 #define drive_bootv_ctl_n_paa4 DRV_PINGROUP_ENTRY_Y(0x4c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1893 #define drive_soc_gpio00_paa0 DRV_PINGROUP_ENTRY_Y(0x54, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1894 #define drive_soc_gpio07_paa7 DRV_PINGROUP_ENTRY_Y(0x5c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1895 #define drive_soc_gpio08_pbb0 DRV_PINGROUP_ENTRY_Y(0x64, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1896 #define drive_soc_gpio09_pbb1 DRV_PINGROUP_ENTRY_Y(0x6c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1897 #define drive_hdmi_cec_paa6 DRV_PINGROUP_ENTRY_Y(0x74, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1898 #define drive_gen2_i2c_scl_pcc0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1899 #define drive_gen2_i2c_sda_pcc1 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1900 #define drive_gen3_i2c_scl_pcc2 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1901 #define drive_gen3_i2c_sda_pcc3 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1902 #define drive_gp_pwm4_pcc4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1903 #define drive_uart0_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1904 #define drive_uart0_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1905 #define drive_spi2_sck_pcc7 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1906 #define drive_spi2_miso_pdd0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1907 #define drive_spi2_mosi_pdd1 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1908 #define drive_spi2_cs0_n_pdd2 DRV_PINGROUP_ENTRY_Y(0x1054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1909 #define drive_soc_gpio21_pdd3 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1910 #define drive_soc_gpio22_pdd4 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1911 #define drive_soc_gpio23_pdd5 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1912 #define drive_soc_gpio24_pdd6 DRV_PINGROUP_ENTRY_Y(0x1074, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1913 #define drive_soc_gpio25_pdd7 DRV_PINGROUP_ENTRY_Y(0x107c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1914 #define drive_soc_gpio26_pee0 DRV_PINGROUP_ENTRY_Y(0x1084, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1915 #define drive_soc_gpio27_pee1 DRV_PINGROUP_ENTRY_Y(0x108c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
1916 #define drive_soc_gpio28_pee2 DRV_PINGROUP_ENTRY_N
1917 #define drive_soc_gpio29_pee3 DRV_PINGROUP_ENTRY_N
1918
1919 #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \
1920 gpio_sfio_sel, schmitt_b) \
1921 { \
1922 .name = #pg_name, \
1923 .pins = pg_name##_pins, \
1924 .npins = ARRAY_SIZE(pg_name##_pins), \
1925 .funcs = { \
1926 TEGRA_MUX_##f0, \
1927 TEGRA_MUX_##f1, \
1928 TEGRA_MUX_##f2, \
1929 TEGRA_MUX_##f3, \
1930 }, \
1931 PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \
1932 e_input, e_lpdr, e_pbias_buf, \
1933 gpio_sfio_sel, schmitt_b) \
1934 drive_##pg_name, \
1935 }
1936
1937 static const struct tegra_pingroup tegra264_uphy_groups[] = {
1938 PINGROUP(eth1_mdio_pe0, ETH1_MDIO, RSVD1, RSVD2, RSVD3, 0x0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1939 PINGROUP(pex_l4_clkreq_n_pd0, PE4_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1940 PINGROUP(pex_l4_rst_n_pd1, PE4_RST_L, RSVD1, RSVD2, RSVD3, 0x10, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1941 PINGROUP(pex_l5_clkreq_n_pd2, PE5_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x18, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1942 PINGROUP(pex_l5_rst_n_pd3, PE5_RST_L, RSVD1, RSVD2, RSVD3, 0x20, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1943 PINGROUP(eth0_mdio_pd4, ETH0_MDIO, RSVD1, RSVD2, RSVD3, 0x28, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1944 PINGROUP(eth0_mdc_pd5, ETH0_MDC, RSVD1, RSVD2, RSVD3, 0x30, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1945 PINGROUP(eth1_mdc_pe1, ETH1_MDC, RSVD1, RSVD2, RSVD3, 0x38, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1946 PINGROUP(eth2_mdio_pe2, ETH2_MDIO, RSVD1, RSVD2, RSVD3, 0x40, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1947 PINGROUP(eth2_mdc_pe3, ETH2_MDC, RSVD1, RSVD2, RSVD3, 0x48, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1948 PINGROUP(eth3_mdio_pd6, ETH3_MDIO, RSVD1, RSVD2, RSVD3, 0x50, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1949 PINGROUP(eth3_mdc_pd7, ETH3_MDC, RSVD1, RSVD2, RSVD3, 0x58, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1950 PINGROUP(pex_l1_clkreq_n_pb0, PE1_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1951 PINGROUP(pex_l1_rst_n_pb1, PE1_RST_L, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1952 PINGROUP(pex_wake_n_pc2, RSVD0, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1953 PINGROUP(pex_l2_rst_n_pb3, PE2_RST_L, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1954 PINGROUP(pex_l2_clkreq_n_pb2, PE2_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1955 PINGROUP(pex_l3_clkreq_n_pb4, PE3_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1956 PINGROUP(pex_l3_rst_n_pb5, PE3_RST_L, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1957 PINGROUP(sgmii0_sma_mdio_pc0, SGMII0_SMA_MDIO, RSVD1, RSVD2, RSVD3, 0x2038, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1958 PINGROUP(sgmii0_sma_mdc_pc1, SGMII0_SMA_MDC, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1959 PINGROUP(soc_gpio113_pb6, USB_VBUS_EN0, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1960 PINGROUP(soc_gpio114_pb7, USB_VBUS_EN1, RSVD1, RSVD2, RSVD3, 0x2050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1961 PINGROUP(pwm1_pa0, GP_PWM1, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1962 PINGROUP(pwm6_pa1, GP_PWM6, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1963 PINGROUP(pwm7_pa2, GP_PWM7, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1964 PINGROUP(pwm8_pa3, GP_PWM8, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1965 PINGROUP(ufs0_ref_clk_pa4, UFS0, RSVD1, RSVD2, RSVD3, 0x3020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1966 PINGROUP(ufs0_rst_n_pa5, UFS0, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1967 };
1968
1969 static const struct tegra_pingroup tegra264_main_groups[] = {
1970 PINGROUP(cpu_pwr_req_ph0, RSVD0, RSVD1, RSVD2, RSVD3, 0x0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1971 PINGROUP(gpu_pwr_req_ph1, RSVD0, RSVD1, RSVD2, RSVD3, 0x8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1972 PINGROUP(uart10_cts_n_ph5, UARTK_CTS, RSVD1, RSVD2, RSVD3, 0x10, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1973 PINGROUP(uart10_rts_n_ph4, UARTK_RTS, RSVD1, RSVD2, RSVD3, 0x18, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1974 PINGROUP(uart10_rx_ph3, UARTK_RXD, RSVD1, RSVD2, RSVD3, 0x20, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1975 PINGROUP(uart10_tx_ph2, UARTK_TXD, RSVD1, RSVD2, RSVD3, 0x28, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1976 PINGROUP(spi3_cs0_pj1, SPI3_CS0, RSVD1, RSVD2, RSVD3, 0x30, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1977 PINGROUP(spi3_cs3_pj2, SPI3_CS3, RSVD1, RSVD2, RSVD3, 0x38, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1978 PINGROUP(spi3_miso_ph7, SPI3_DIN, RSVD1, RSVD2, RSVD3, 0x40, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1979 PINGROUP(spi3_mosi_pj0, SPI3_DOUT, RSVD1, RSVD2, RSVD3, 0x48, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1980 PINGROUP(spi3_sck_ph6, SPI3_SCK, RSVD1, RSVD2, RSVD3, 0x50, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1981 PINGROUP(uart5_cts_n_pj6, UARTF_CTS, RSVD1, RSVD2, RSVD3, 0x58, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1982 PINGROUP(uart5_rts_n_pj5, UARTF_RTS, RSVD1, RSVD2, RSVD3, 0x60, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1983 PINGROUP(uart5_rx_pj4, UARTF_RXD, RSVD1, RSVD2, RSVD3, 0x68, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1984 PINGROUP(uart5_tx_pj3, UARTF_TXD, RSVD1, RSVD2, RSVD3, 0x70, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1985 PINGROUP(spi1_cs0_pk2, SPI1_CS0, RSVD1, RSVD2, RSVD3, 0x78, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1986 PINGROUP(spi1_cs1_pk3, SPI1_CS1, RSVD1, RSVD2, RSVD3, 0x80, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1987 PINGROUP(spi1_miso_pk0, SPI1_DIN, RSVD1, RSVD2, RSVD3, 0x88, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1988 PINGROUP(spi1_mosi_pk1, SPI1_DOUT, RSVD1, RSVD2, RSVD3, 0x90, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1989 PINGROUP(spi1_sck_pj7, SPI1_SCK, RSVD1, RSVD2, RSVD3, 0x98, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1990 PINGROUP(extperiph2_clk_pk5, EXTPERIPH2_CLK, RSVD1, DMIC2_CLK, DSPK1_CLK, 0xa0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1991 PINGROUP(extperiph1_clk_pk4, EXTPERIPH1_CLK, RSVD1, DMIC2_DAT, DSPK1_DAT, 0xa8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1992 PINGROUP(gen12_i2c_scl_pk6, I2C12_CLK, RSVD1, RSVD2, RSVD3, 0xb0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1993 PINGROUP(gen12_i2c_sda_pk7, I2C12_DAT, RSVD1, RSVD2, RSVD3, 0xb8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1994 PINGROUP(soc_gpio124_pl0, RSVD0, SOC_THERM_OC3, RSVD2, RSVD3, 0x1000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1995 PINGROUP(soc_gpio125_pl1, RSVD0, I2S5_SCLK, RSVD2, RSVD3, 0x1008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1996 PINGROUP(fan_tach0_pl2, NV_THERM_FAN_TACH0, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1997 PINGROUP(soc_gpio127_pl3, RSVD0, RSVD1, NV_THERM_FAN_TACH1, RSVD3, 0x1018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1998 PINGROUP(soc_gpio128_pl4, RSVD0, I2S5_SDATA_IN, RSVD2, RSVD3, 0x1020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
1999 PINGROUP(soc_gpio129_pl5, RSVD0, EXTPERIPH3_CLK, I2C15_CLK, RSVD3, 0x1028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2000 PINGROUP(soc_gpio130_pl6, RSVD0, EXTPERIPH4_CLK, I2C15_DAT, RSVD3, 0x1030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2001 PINGROUP(soc_gpio131_pl7, RSVD0, I2S5_SDATA_OUT, RSVD2, RSVD3, 0x1038, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2002 PINGROUP(gp_pwm9_pm0, GP_PWM9, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2003 PINGROUP(soc_gpio133_pm1, RSVD0, I2S5_LRCK, RSVD2, RSVD3, 0x1048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2004 PINGROUP(uart9_cts_n_pm5, UARTJ_CTS, RSVD1, RSVD2, RSVD3, 0x1050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2005 PINGROUP(uart9_rts_n_pm4, UARTJ_RTS, RSVD1, RSVD2, RSVD3, 0x1058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2006 PINGROUP(uart9_rx_pm3, UARTJ_RXD, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2007 PINGROUP(uart9_tx_pm2, UARTJ_TXD, RSVD1, RSVD2, RSVD3, 0x1068, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2008 PINGROUP(sdmmc1_clk_px0, SDMMC1_CLK, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, -1, 5, 6, 13, -1, 10, -1),
2009 PINGROUP(sdmmc1_cmd_px1, SDMMC1_CMD, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, -1, 5, 6, 13, -1, 10, -1),
2010 PINGROUP(sdmmc1_comp, SDMMC1_COMP, RSVD1, RSVD2, RSVD3, 0x2010, 0, N, -1, -1, -1, -1, -1, -1, -1),
2011 PINGROUP(sdmmc1_dat3_px5, SDMMC1_DAT3, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, -1, 5, 6, 13, -1, 10, -1),
2012 PINGROUP(sdmmc1_dat2_px4, SDMMC1_DAT2, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, -1, 5, 6, 13, -1, 10, -1),
2013 PINGROUP(sdmmc1_dat1_px3, SDMMC1_DAT1, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, -1, 5, 6, 13, -1, 10, -1),
2014 PINGROUP(sdmmc1_dat0_px2, SDMMC1_DAT0, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, -1, 5, 6, 13, -1, 10, -1),
2015 PINGROUP(qspi0_cs_n_pt1, QSPI0_CS_N, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2016 PINGROUP(qspi0_io0_pt2, QSPI0_IO0, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2017 PINGROUP(qspi0_io1_pt3, QSPI0_IO1, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2018 PINGROUP(qspi0_io2_pt4, QSPI0_IO2, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2019 PINGROUP(qspi0_io3_pt5, QSPI0_IO3, RSVD1, RSVD2, RSVD3, 0x3020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2020 PINGROUP(qspi0_sck_pt0, QSPI0_SCK, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2021 PINGROUP(soc_gpio192_pt6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2022 PINGROUP(soc_gpio138_pp0, RSVD0, I2C14_CLK, DMIC1_DAT, RSVD3, 0x5000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2023 PINGROUP(soc_gpio139_pp1, RSVD0, I2C14_DAT, DMIC1_CLK, RSVD3, 0x5008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2024 PINGROUP(dap6_din_pp4, I2S6_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x5010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2025 PINGROUP(dap6_dout_pp3, I2S6_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x5018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2026 PINGROUP(dap6_fs_pp5, I2S6_LRCK, RSVD1, RSVD2, RSVD3, 0x5020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2027 PINGROUP(dap6_sclk_pp2, I2S6_SCLK, RSVD1, RSVD2, RSVD3, 0x5028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2028 PINGROUP(dap4_dout_pp7, I2S4_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x5030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2029 PINGROUP(dap4_sclk_pp6, I2S4_SCLK, RSVD1, RSVD2, RSVD3, 0x5038, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2030 PINGROUP(dap4_din_pq0, I2S4_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x5040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2031 PINGROUP(dap4_fs_pq1, I2S4_LRCK, RSVD1, RSVD2, RSVD3, 0x5048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2032 PINGROUP(spi5_cs0_pq5, SPI5_CS0, RSVD1, RSVD2, RSVD3, 0x5050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2033 PINGROUP(spi5_miso_pq3, SPI5_DIN, RSVD1, RSVD2, RSVD3, 0x5058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2034 PINGROUP(spi5_mosi_pq4, SPI5_DOUT, RSVD1, RSVD2, RSVD3, 0x5060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2035 PINGROUP(spi5_sck_pq2, SPI5_SCK, RSVD1, RSVD2, RSVD3, 0x5068, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2036 PINGROUP(soc_gpio152_pq6, RSVD0, I2S8_SCLK, RSVD2, RSVD3, 0x5070, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2037 PINGROUP(soc_gpio153_pq7, RSVD0, I2S8_SDATA_OUT, RSVD2, RSVD3, 0x5078, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2038 PINGROUP(soc_gpio155_pr1, RSVD0, I2S8_LRCK, RSVD2, RSVD3, 0x5080, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2039 PINGROUP(aud_mclk_pr0, AUD_MCLK, RSVD1, RSVD2, RSVD3, 0x5088, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2040 PINGROUP(dap1_sclk_pr2, I2S1_SCLK, RSVD1, RSVD2, RSVD3, 0x5090, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2041 PINGROUP(dap1_in_pr4, I2S1_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x5098, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2042 PINGROUP(dap1_out_pr3, I2S1_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x50a0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2043 PINGROUP(dap1_fs_pr5, I2S1_LRCK, RSVD1, RSVD2, RSVD3, 0x50a8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2044 PINGROUP(gen11_i2c_scl_pr6, I2C11_CLK, RSVD1, RSVD2, RSVD3, 0x50b0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2045 PINGROUP(gen11_i2c_sda_pr7, I2C11_DAT, RSVD1, RSVD2, RSVD3, 0x50b8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2046 PINGROUP(soc_gpio350_ps0, RSVD0, I2S8_SDATA_IN, RSVD2, RSVD3, 0x50c0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2047 PINGROUP(soc_gpio351_ps1, RSVD0, RSVD1, RSVD2, RSVD3, 0x50c8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2048 PINGROUP(gen0_i2c_scl_pw4, I2C0_CLK, RSVD1, RSVD2, RSVD3, 0x6000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2049 PINGROUP(gen0_i2c_sda_pw5, I2C0_DAT, RSVD1, RSVD2, RSVD3, 0x6008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2050 PINGROUP(gen1_i2c_scl_pw2, I2C1_CLK, RSVD1, RSVD2, RSVD3, 0x6010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2051 PINGROUP(gen1_i2c_sda_pw3, I2C1_DAT, RSVD1, RSVD2, RSVD3, 0x6018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2052 PINGROUP(dap2_fs_pw1, I2S2_LRCK, RSVD1, RSVD2, RSVD3, 0x6040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2053 PINGROUP(dap2_clk_pv6, I2S2_SCLK, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2054 PINGROUP(dap2_din_pv7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2055 PINGROUP(dap2_dout_pw0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2056 PINGROUP(pwm10_pv1, GP_PWM10, SDMMC1_CD, I2S7_LRCK, RSVD3, 0x6060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2057 PINGROUP(soc_gpio170_pu0, RSVD0, I2S7_SDATA_IN, CCLA_LA_TRIGGER_MUX, RSVD3, 0x6068, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2058 PINGROUP(soc_gpio171_pu1, RSVD0, SPI4_SCK, RSVD2, RSVD3, 0x6070, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2059 PINGROUP(soc_gpio172_pu2, RSVD0, SPI4_DIN, RSVD2, RSVD3, 0x6078, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2060 PINGROUP(soc_gpio173_pu3, RSVD0, SPI4_DOUT, RSVD2, RSVD3, 0x6080, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2061 PINGROUP(soc_gpio174_pu4, RSVD0, SPI4_CS0, RSVD2, RSVD3, 0x6088, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2062 PINGROUP(soc_gpio175_pu5, RSVD0, SPI4_CS1, RSVD2, RSVD3, 0x6090, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2063 PINGROUP(soc_gpio176_pu6, RSVD0, RSVD1, I2S7_SCLK, RSVD3, 0x6098, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2064 PINGROUP(soc_gpio177_pu7, RSVD0, GP_PWM5, RSVD2, RSVD3, 0x60a0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2065 PINGROUP(soc_gpio178_pv0, RSVD0, RSVD1, I2S7_SDATA_OUT, RSVD3, 0x60a8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2066 PINGROUP(uart4_cts_n_pv5, UARTE_CTS, RSVD1, RSVD2, RSVD3, 0x60b0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2067 PINGROUP(uart4_rts_n_pv4, UARTE_RTS, RSVD1, RSVD2, RSVD3, 0x60b8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2068 PINGROUP(uart4_rx_pv3, UARTE_RXD, RSVD1, RSVD2, RSVD3, 0x60c0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2069 PINGROUP(uart4_tx_pv2, UARTE_TXD, RSVD1, RSVD2, RSVD3, 0x60c8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2070 PINGROUP(pwr_i2c_sda_pw7, I2C5_DAT, RSVD1, RSVD2, RSVD3, 0x60d0, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2071 PINGROUP(pwr_i2c_scl_pw6, I2C5_CLK, RSVD1, RSVD2, RSVD3, 0x60d8, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2072 PINGROUP(soc_gpio250_pf0, DCA_VSYNC, DCB_VSYNC, DCC_VSYNC, DCD_VSYNC, 0x7000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2073 PINGROUP(soc_gpio251_pf1, DCA_HSYNC, DCB_HSYNC, DCC_HSYNC, DCD_HSYNC, 0x7008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2074 PINGROUP(soc_gpio252_pf2, RSVD0, DSA_LSPII, RSVD2, RSVD3, 0x7010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2075 PINGROUP(dp_aux_ch0_hpd_pf3, DP_AUX_CH0_HPD, DCE_VSYNC, DCF_VSYNC, DCG_VSYNC, 0x7018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2076 PINGROUP(dp_aux_ch1_hpd_pf4, DP_AUX_CH1_HPD, DCE_HSYNC, DCF_HSYNC, DCG_HSYNC, 0x7020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2077 PINGROUP(dp_aux_ch2_hpd_pf5, DP_AUX_CH2_HPD, DCH_VSYNC, RSVD2, RSVD3, 0x7028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2078 PINGROUP(dp_aux_ch3_hpd_pf6, DP_AUX_CH3_HPD, DCH_HSYNC, RSVD2, RSVD3, 0x7030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2079 PINGROUP(pwm2_pf7, GP_PWM2, BL_EN, RSVD2, RSVD3, 0x7038, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2080 PINGROUP(pwm3_pg0, GP_PWM3, BL_PWM_DIM0, RSVD2, RSVD3, 0x7040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2081 PINGROUP(gen7_i2c_scl_pg1, I2C7_CLK, RSVD1, SOUNDWIRE1_CLK, RSVD3, 0x7048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2082 PINGROUP(gen7_i2c_sda_pg2, I2C7_DAT, RSVD1, SOUNDWIRE1_DAT0, RSVD3, 0x7050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2083 PINGROUP(gen9_i2c_scl_pg3, I2C9_CLK, RSVD1, SOUNDWIRE1_DAT1, RSVD3, 0x7058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2084 PINGROUP(gen9_i2c_sda_pg4, I2C9_DAT, RSVD1, SOUNDWIRE1_DAT2, RSVD3, 0x7060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2085 PINGROUP(soc_gpio270_py0, RSVD0, I2C16_CLK, RSVD2, RSVD3, 0xa000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2086 PINGROUP(soc_gpio271_py1, RSVD0, I2C16_DAT, RSVD2, RSVD3, 0xa008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2087 PINGROUP(soc_gpio272_py2, RSVD0, I2S3_SCLK, RSVD2, RSVD3, 0xa010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2088 PINGROUP(soc_gpio273_py3, RSVD0, I2S3_SDATA_OUT, RSVD2, RSVD3, 0xa018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2089 PINGROUP(soc_gpio274_py4, RSVD0, I2S3_SDATA_IN, RSVD2, RSVD3, 0xa020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2090 PINGROUP(soc_gpio275_py5, RSVD0, I2S3_LRCK, RSVD2, RSVD3, 0xa028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2091 PINGROUP(soc_gpio276_py6, RSVD0, RSVD1, RSVD2, RSVD3, 0xa030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2092 PINGROUP(soc_gpio277_py7, RSVD0, RSVD1, RSVD2, RSVD3, 0xa038, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2093 PINGROUP(soc_gpio278_pz0, RSVD0, RSVD1, RSVD2, RSVD3, 0xa040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2094 PINGROUP(soc_gpio279_pz1, RSVD0, RSVD1, RSVD2, RSVD3, 0xa048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2095 PINGROUP(soc_gpio282_pz4, RSVD0, PM_TRIG1, RSVD2, RSVD3, 0xa050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2096 PINGROUP(soc_gpio283_pz5, RSVD0, RSVD1, RSVD2, RSVD3, 0xa058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2097 PINGROUP(soc_gpio284_pz6, RSVD0, RSVD1, RSVD2, RSVD3, 0xa060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2098 PINGROUP(soc_gpio285_pz7, RSVD0, RSVD1, RSVD2, RSVD3, 0xa068, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2099 PINGROUP(soc_gpio286_pal0, RSVD0, RSVD1, RSVD2, RSVD3, 0xa070, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2100 PINGROUP(soc_gpio287_pal1, RSVD0, RSVD1, RSVD2, RSVD3, 0xa078, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2101 PINGROUP(soc_gpio288_pal2, RSVD0, RSVD1, RSVD2, RSVD3, 0xa080, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2102 PINGROUP(xhalt_trig_pz2, XHALT_TRIG, RSVD1, RSVD2, RSVD3, 0xa088, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2103 PINGROUP(soc_gpio281_pz3, RSVD0, PM_TRIG0, RSVD2, RSVD3, 0xa090, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2104 };
2105
2106 static const struct tegra_pingroup tegra264_aon_groups[] = {
2107 PINGROUP(ao_retention_n_paa2, RSVD0, RSVD1, RSVD2, ISTCTRL_IST_DONE_N, 0x28, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2108 PINGROUP(batt_oc_paa3, SOC_THERM_OC2, RSVD1, RSVD2, RSVD3, 0x30, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2109 PINGROUP(power_on_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x38, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2110 PINGROUP(vcomp_alert_paa1, SOC_THERM_OC1, RSVD1, RSVD2, RSVD3, 0x40, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2111 PINGROUP(bootv_ctl_n_paa4, RSVD0, RSVD1, RSVD2, RSVD3, 0x48, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2112 PINGROUP(soc_gpio00_paa0, RSVD0, RSVD1, RSVD2, RSVD3, 0x50, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2113 PINGROUP(soc_gpio07_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x58, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2114 PINGROUP(soc_gpio08_pbb0, RSVD0, RSVD1, RSVD2, RSVD3, 0x60, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2115 PINGROUP(soc_gpio09_pbb1, RSVD0, RSVD1, RSVD2, RSVD3, 0x68, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2116 PINGROUP(hdmi_cec_paa6, HDMI_CEC, RSVD1, RSVD2, RSVD3, 0x70, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2117 PINGROUP(gen2_i2c_scl_pcc0, I2C2_CLK, RSVD1, RSVD2, RSVD3, 0x1000, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2118 PINGROUP(gen2_i2c_sda_pcc1, I2C2_DAT, RSVD1, RSVD2, RSVD3, 0x1008, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2119 PINGROUP(gen3_i2c_scl_pcc2, I2C3_CLK, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2120 PINGROUP(gen3_i2c_sda_pcc3, I2C3_DAT, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2121 PINGROUP(gp_pwm4_pcc4, GP_PWM4, TOUCH_CLK, RSVD2, RSVD3, 0x1020, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2122 PINGROUP(uart0_tx_pcc5, UARTA_TXD, RSVD1, UARTL_TXD, RSVD3, 0x1028, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2123 PINGROUP(uart0_rx_pcc6, UARTA_RXD, RSVD1, UARTL_RXD, RSVD3, 0x1030, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2124 PINGROUP(spi2_sck_pcc7, SPI2_SCK, RSVD1, I2S9_SCLK, SOUNDWIRE0_CLK, 0x1038, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2125 PINGROUP(spi2_miso_pdd0, SPI2_DIN, RSVD1, I2S9_SDATA_OUT, SOUNDWIRE0_DAT0, 0x1040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2126 PINGROUP(spi2_mosi_pdd1, SPI2_DOUT, RSVD1, I2S9_SDATA_IN, RSVD3, 0x1048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2127 PINGROUP(spi2_cs0_n_pdd2, SPI2_CS0, RSVD1, I2S9_LRCK, RSVD3, 0x1050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2128 PINGROUP(soc_gpio21_pdd3, RSVD0, TSC_SYNC1, DMIC5_DAT, RSVD3, 0x1058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2129 PINGROUP(soc_gpio22_pdd4, RSVD0, RSVD1, DMIC5_CLK, RSVD3, 0x1060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2130 PINGROUP(soc_gpio23_pdd5, RSVD0, RSVD1, TSC_EDGE_OUT2, TSC_EDGE_OUT0C, 0x1068, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2131 PINGROUP(soc_gpio24_pdd6, RSVD0, TSC_EDGE_OUT3, RSVD2, TSC_EDGE_OUT0D, 0x1070, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2132 PINGROUP(soc_gpio25_pdd7, RSVD0, TSC_EDGE_OUT0, RSVD2, TSC_EDGE_OUT0A, 0x1078, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2133 PINGROUP(soc_gpio26_pee0, RSVD0, TSC_EDGE_OUT1, RSVD2, TSC_EDGE_OUT0B, 0x1080, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2134 PINGROUP(soc_gpio27_pee1, RSVD0, TSC_SYNC0, RSVD2, RSVD3, 0x1088, 0, Y, 5, 7, 6, 8, -1, 10, 11),
2135 PINGROUP(soc_gpio28_pee2, L0L1_RST_OUT_N, RSVD1, RSVD2, RSVD3, 0x1090, 0, N, -1, -1, -1, -1, -1, 10, -1),
2136 PINGROUP(soc_gpio29_pee3, L2_RST_OUT_N, RSVD1, RSVD2, RSVD3, 0x1098, 0, N, -1, -1, -1, -1, -1, 10, -1),
2137 };
2138
2139 static const struct tegra_pinctrl_soc_data tegra264_uphy_pinctrl = {
2140 .pins = tegra264_uphy_pins,
2141 .npins = ARRAY_SIZE(tegra264_uphy_pins),
2142 .functions = tegra264_functions,
2143 .nfunctions = ARRAY_SIZE(tegra264_functions),
2144 .groups = tegra264_uphy_groups,
2145 .ngroups = ARRAY_SIZE(tegra264_uphy_groups),
2146 .hsm_in_mux = false,
2147 .schmitt_in_mux = true,
2148 .drvtype_in_mux = true,
2149 .sfsel_in_mux = true,
2150 };
2151
2152 static const struct tegra_pinctrl_soc_data tegra264_main_pinctrl = {
2153 .pins = tegra264_main_pins,
2154 .npins = ARRAY_SIZE(tegra264_main_pins),
2155 .functions = tegra264_functions,
2156 .nfunctions = ARRAY_SIZE(tegra264_functions),
2157 .groups = tegra264_main_groups,
2158 .ngroups = ARRAY_SIZE(tegra264_main_groups),
2159 .hsm_in_mux = false,
2160 .schmitt_in_mux = true,
2161 .drvtype_in_mux = true,
2162 .sfsel_in_mux = true,
2163 };
2164
2165 static const struct tegra_pinctrl_soc_data tegra264_aon_pinctrl = {
2166 .pins = tegra264_aon_pins,
2167 .npins = ARRAY_SIZE(tegra264_aon_pins),
2168 .functions = tegra264_functions,
2169 .nfunctions = ARRAY_SIZE(tegra264_functions),
2170 .groups = tegra264_aon_groups,
2171 .ngroups = ARRAY_SIZE(tegra264_aon_groups),
2172 .hsm_in_mux = false,
2173 .schmitt_in_mux = true,
2174 .drvtype_in_mux = true,
2175 .sfsel_in_mux = true,
2176 };
2177
tegra264_pinctrl_probe(struct platform_device * pdev)2178 static int tegra264_pinctrl_probe(struct platform_device *pdev)
2179 {
2180 const struct tegra_pinctrl_soc_data *soc = device_get_match_data(&pdev->dev);
2181
2182 return tegra_pinctrl_probe(pdev, soc);
2183 }
2184
2185 static const struct of_device_id tegra264_pinctrl_of_match[] = {
2186 { .compatible = "nvidia,tegra264-pinmux-uphy", .data = &tegra264_uphy_pinctrl},
2187 { .compatible = "nvidia,tegra264-pinmux-main", .data = &tegra264_main_pinctrl},
2188 { .compatible = "nvidia,tegra264-pinmux-aon", .data = &tegra264_aon_pinctrl},
2189 { }
2190 };
2191 MODULE_DEVICE_TABLE(of, tegra264_pinctrl_of_match);
2192
2193 static struct platform_driver tegra264_pinctrl_driver = {
2194 .driver = {
2195 .name = "tegra264-pinctrl",
2196 .of_match_table = tegra264_pinctrl_of_match,
2197 },
2198 .probe = tegra264_pinctrl_probe,
2199 };
2200
tegra264_pinctrl_init(void)2201 static int __init tegra264_pinctrl_init(void)
2202 {
2203 return platform_driver_register(&tegra264_pinctrl_driver);
2204 }
2205 module_init(tegra264_pinctrl_init);
2206
tegra264_pinctrl_exit(void)2207 static void __exit tegra264_pinctrl_exit(void)
2208 {
2209 platform_driver_unregister(&tegra264_pinctrl_driver);
2210 }
2211 module_exit(tegra264_pinctrl_exit);
2212
2213 MODULE_LICENSE("GPL");
2214 MODULE_AUTHOR("NVIDIA Corporation");
2215 MODULE_DESCRIPTION("NVIDIA Tegra264 pinctrl driver");
2216