1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Pinctrl data for the NVIDIA Tegra238 pinmux
4 *
5 * Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved.
6 */
7
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/property.h>
11 #include <linux/pinctrl/pinctrl.h>
12 #include <linux/pinctrl/pinmux.h>
13
14 #include "pinctrl-tegra.h"
15
16 /* Define unique ID for each pins */
17 enum {
18 TEGRA_PIN_GPU_PWR_REQ_PA0,
19 TEGRA_PIN_GP_PWM5_PA1,
20 TEGRA_PIN_GP_PWM6_PA2,
21 TEGRA_PIN_SPI3_SCK_PA3,
22 TEGRA_PIN_SPI3_MISO_PA4,
23 TEGRA_PIN_SPI3_MOSI_PA5,
24 TEGRA_PIN_SPI3_CS0_PA6,
25 TEGRA_PIN_SPI3_CS1_PA7,
26 TEGRA_PIN_SPI1_SCK_PB0,
27 TEGRA_PIN_SPI1_MISO_PB1,
28 TEGRA_PIN_SPI1_MOSI_PB2,
29 TEGRA_PIN_SPI1_CS0_PB3,
30 TEGRA_PIN_SPI1_CS1_PB4,
31 TEGRA_PIN_PWR_I2C_SCL_PC0,
32 TEGRA_PIN_PWR_I2C_SDA_PC1,
33 TEGRA_PIN_EXTPERIPH1_CLK_PC2,
34 TEGRA_PIN_EXTPERIPH2_CLK_PC3,
35 TEGRA_PIN_CAM_I2C_SCL_PC4,
36 TEGRA_PIN_CAM_I2C_SDA_PC5,
37 TEGRA_PIN_SOC_GPIO23_PC6,
38 TEGRA_PIN_SOC_GPIO24_PC7,
39 TEGRA_PIN_SOC_GPIO27_PD0,
40 TEGRA_PIN_SOC_GPIO55_PD1,
41 TEGRA_PIN_SOC_GPIO29_PD2,
42 TEGRA_PIN_SOC_GPIO33_PD3,
43 TEGRA_PIN_SOC_GPIO32_PD4,
44 TEGRA_PIN_SOC_GPIO35_PD5,
45 TEGRA_PIN_SOC_GPIO37_PD6,
46 TEGRA_PIN_SOC_GPIO56_PD7,
47 TEGRA_PIN_UART1_TX_PE0,
48 TEGRA_PIN_UART1_RX_PE1,
49 TEGRA_PIN_UART1_RTS_PE2,
50 TEGRA_PIN_UART1_CTS_PE3,
51 TEGRA_PIN_SOC_GPIO13_PF0,
52 TEGRA_PIN_SOC_GPIO14_PF1,
53 TEGRA_PIN_SOC_GPIO15_PF2,
54 TEGRA_PIN_SOC_GPIO16_PF3,
55 TEGRA_PIN_SOC_GPIO17_PF4,
56 TEGRA_PIN_SOC_GPIO18_PF5,
57 TEGRA_PIN_SOC_GPIO20_PF6,
58 TEGRA_PIN_SOC_GPIO21_PF7,
59 TEGRA_PIN_SOC_GPIO22_PG0,
60 TEGRA_PIN_SOC_GPIO06_PG1,
61 TEGRA_PIN_UART4_TX_PG2,
62 TEGRA_PIN_UART4_RX_PG3,
63 TEGRA_PIN_UART4_RTS_PG4,
64 TEGRA_PIN_UART4_CTS_PG5,
65 TEGRA_PIN_SOC_GPIO41_PG6,
66 TEGRA_PIN_SOC_GPIO42_PG7,
67 TEGRA_PIN_SOC_GPIO43_PH0,
68 TEGRA_PIN_SOC_GPIO44_PH1,
69 TEGRA_PIN_GEN1_I2C_SCL_PH2,
70 TEGRA_PIN_GEN1_I2C_SDA_PH3,
71 TEGRA_PIN_CPU_PWR_REQ_PH4,
72 TEGRA_PIN_SOC_GPIO07_PH5,
73 TEGRA_PIN_DAP3_CLK_PJ0,
74 TEGRA_PIN_DAP3_DOUT_PJ1,
75 TEGRA_PIN_DAP3_DIN_PJ2,
76 TEGRA_PIN_DAP3_FS_PJ3,
77 TEGRA_PIN_SOC_GPIO57_PJ4,
78 TEGRA_PIN_SOC_GPIO58_PJ5,
79 TEGRA_PIN_SOC_GPIO59_PJ6,
80 TEGRA_PIN_SOC_GPIO60_PJ7,
81 TEGRA_PIN_SOC_GPIO45_PK0,
82 TEGRA_PIN_SOC_GPIO46_PK1,
83 TEGRA_PIN_SOC_GPIO47_PK2,
84 TEGRA_PIN_SOC_GPIO48_PK3,
85 TEGRA_PIN_QSPI0_SCK_PL0,
86 TEGRA_PIN_QSPI0_IO0_PL1,
87 TEGRA_PIN_QSPI0_IO1_PL2,
88 TEGRA_PIN_QSPI0_CS_N_PL3,
89 TEGRA_PIN_SOC_GPIO152_PL4,
90 TEGRA_PIN_SOC_GPIO153_PL5,
91 TEGRA_PIN_SOC_GPIO154_PL6,
92 TEGRA_PIN_SOC_GPIO155_PL7,
93 TEGRA_PIN_SOC_GPIO156_PM0,
94 TEGRA_PIN_SOC_GPIO157_PM1,
95 TEGRA_PIN_SOC_GPIO158_PM2,
96 TEGRA_PIN_SOC_GPIO159_PM3,
97 TEGRA_PIN_SOC_GPIO160_PM4,
98 TEGRA_PIN_SOC_GPIO161_PM5,
99 TEGRA_PIN_SOC_GPIO162_PM6,
100 TEGRA_PIN_UART7_TX_PM7,
101 TEGRA_PIN_UART7_RX_PN0,
102 TEGRA_PIN_UART7_RTS_PN1,
103 TEGRA_PIN_UART7_CTS_PN2,
104 TEGRA_PIN_SOC_GPIO167_PP0,
105 TEGRA_PIN_SOC_GPIO168_PP1,
106 TEGRA_PIN_SOC_GPIO169_PP2,
107 TEGRA_PIN_SOC_GPIO170_PP3,
108 TEGRA_PIN_DAP4_SCLK_PP4,
109 TEGRA_PIN_DAP4_DOUT_PP5,
110 TEGRA_PIN_DAP4_DIN_PP6,
111 TEGRA_PIN_DAP4_FS_PP7,
112 TEGRA_PIN_SOC_GPIO171_PQ0,
113 TEGRA_PIN_SOC_GPIO172_PQ1,
114 TEGRA_PIN_SOC_GPIO173_PQ2,
115 TEGRA_PIN_SOC_GPIO61_PR0,
116 TEGRA_PIN_SOC_GPIO62_PR1,
117 TEGRA_PIN_SOC_GPIO63_PR2,
118 TEGRA_PIN_SOC_GPIO64_PR3,
119 TEGRA_PIN_SOC_GPIO65_PR4,
120 TEGRA_PIN_SOC_GPIO66_PR5,
121 TEGRA_PIN_SOC_GPIO67_PR6,
122 TEGRA_PIN_SOC_GPIO68_PR7,
123 TEGRA_PIN_GEN4_I2C_SCL_PS0,
124 TEGRA_PIN_GEN4_I2C_SDA_PS1,
125 TEGRA_PIN_SOC_GPIO75_PS2,
126 TEGRA_PIN_GEN7_I2C_SCL_PS3,
127 TEGRA_PIN_GEN7_I2C_SDA_PS4,
128 TEGRA_PIN_SOC_GPIO78_PS5,
129 TEGRA_PIN_GEN9_I2C_SCL_PS6,
130 TEGRA_PIN_GEN9_I2C_SDA_PS7,
131 TEGRA_PIN_SOC_GPIO81_PT0,
132 TEGRA_PIN_SOC_GPIO36_PT1,
133 TEGRA_PIN_SOC_GPIO53_PT2,
134 TEGRA_PIN_SOC_GPIO38_PT3,
135 TEGRA_PIN_SOC_GPIO40_PT4,
136 TEGRA_PIN_SOC_GPIO34_PT5,
137 TEGRA_PIN_USB_VBUS_EN0_PT6,
138 TEGRA_PIN_USB_VBUS_EN1_PT7,
139 TEGRA_PIN_SDMMC1_CLK_PU0,
140 TEGRA_PIN_SDMMC1_CMD_PU1,
141 TEGRA_PIN_SDMMC1_DAT0_PU2,
142 TEGRA_PIN_SDMMC1_DAT1_PU3,
143 TEGRA_PIN_SDMMC1_DAT2_PU4,
144 TEGRA_PIN_SDMMC1_DAT3_PU5,
145 TEGRA_PIN_UFS0_REF_CLK_PV0,
146 TEGRA_PIN_UFS0_RST_N_PV1,
147 TEGRA_PIN_PEX_L0_CLKREQ_N_PW0,
148 TEGRA_PIN_PEX_L0_RST_N_PW1,
149 TEGRA_PIN_PEX_L1_CLKREQ_N_PW2,
150 TEGRA_PIN_PEX_L1_RST_N_PW3,
151 TEGRA_PIN_PEX_L2_CLKREQ_N_PW4,
152 TEGRA_PIN_PEX_L2_RST_N_PW5,
153 TEGRA_PIN_PEX_L3_CLKREQ_N_PW6,
154 TEGRA_PIN_PEX_L3_RST_N_PW7,
155 TEGRA_PIN_PEX_WAKE_N_PX0,
156 TEGRA_PIN_DP_AUX_CH0_HPD_PX1,
157 TEGRA_PIN_SDMMC1_COMP,
158 };
159
160 enum {
161 TEGRA_PIN_BOOTV_CTL_N_PAA0,
162 TEGRA_PIN_SOC_GPIO00_PAA1,
163 TEGRA_PIN_VCOMP_ALERT_PAA2,
164 TEGRA_PIN_PWM1_PAA3,
165 TEGRA_PIN_BATT_OC_PAA4,
166 TEGRA_PIN_SOC_GPIO04_PAA5,
167 TEGRA_PIN_SOC_GPIO25_PAA6,
168 TEGRA_PIN_SOC_GPIO26_PAA7,
169 TEGRA_PIN_HDMI_CEC_PBB0,
170 TEGRA_PIN_SPI2_SCK_PCC0,
171 TEGRA_PIN_SPI2_MISO_PCC1,
172 TEGRA_PIN_SPI2_MOSI_PCC2,
173 TEGRA_PIN_SPI2_CS0_PCC3,
174 TEGRA_PIN_SPI2_CS1_PCC4,
175 TEGRA_PIN_UART3_TX_PCC5,
176 TEGRA_PIN_UART3_RX_PCC6,
177 TEGRA_PIN_GEN2_I2C_SCL_PCC7,
178 TEGRA_PIN_GEN2_I2C_SDA_PDD0,
179 TEGRA_PIN_GEN8_I2C_SCL_PDD1,
180 TEGRA_PIN_GEN8_I2C_SDA_PDD2,
181 TEGRA_PIN_TOUCH_CLK_PDD3,
182 TEGRA_PIN_DMIC1_CLK_PDD4,
183 TEGRA_PIN_DMIC1_DAT_PDD5,
184 TEGRA_PIN_SOC_GPIO19_PDD6,
185 TEGRA_PIN_PWM2_PDD7,
186 TEGRA_PIN_PWM3_PEE0,
187 TEGRA_PIN_PWM7_PEE1,
188 TEGRA_PIN_SOC_GPIO49_PEE2,
189 TEGRA_PIN_SOC_GPIO82_PEE3,
190 TEGRA_PIN_SOC_GPIO50_PEE4,
191 TEGRA_PIN_SOC_GPIO83_PEE5,
192 TEGRA_PIN_SOC_GPIO69_PFF0,
193 TEGRA_PIN_SOC_GPIO70_PFF1,
194 TEGRA_PIN_SOC_GPIO71_PFF2,
195 TEGRA_PIN_SOC_GPIO72_PFF3,
196 TEGRA_PIN_SOC_GPIO73_PFF4,
197 TEGRA_PIN_SOC_GPIO74_PFF5,
198 TEGRA_PIN_SOC_GPIO80_PFF6,
199 TEGRA_PIN_SOC_GPIO76_PFF7,
200 TEGRA_PIN_SOC_GPIO77_PGG0,
201 TEGRA_PIN_SOC_GPIO84_PGG1,
202 TEGRA_PIN_UART2_TX_PGG2,
203 TEGRA_PIN_UART2_RX_PGG3,
204 TEGRA_PIN_UART2_RTS_PGG4,
205 TEGRA_PIN_UART2_CTS_PGG5,
206 TEGRA_PIN_SOC_GPIO85_PGG6,
207 TEGRA_PIN_UART5_TX_PGG7,
208 TEGRA_PIN_UART5_RX_PHH0,
209 TEGRA_PIN_UART5_RTS_PHH1,
210 TEGRA_PIN_UART5_CTS_PHH2,
211 TEGRA_PIN_SOC_GPIO86_PHH3,
212 };
213
214 /* Table for pin descriptor */
215 static const struct pinctrl_pin_desc tegra238_pins[] = {
216 PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PA0, "GPU_PWR_REQ_PA0"),
217 PINCTRL_PIN(TEGRA_PIN_GP_PWM5_PA1, "GP_PWM5_PA1"),
218 PINCTRL_PIN(TEGRA_PIN_GP_PWM6_PA2, "GP_PWM6_PA2"),
219 PINCTRL_PIN(TEGRA_PIN_SPI3_SCK_PA3, "SPI3_SCK_PA3"),
220 PINCTRL_PIN(TEGRA_PIN_SPI3_MISO_PA4, "SPI3_MISO_PA4"),
221 PINCTRL_PIN(TEGRA_PIN_SPI3_MOSI_PA5, "SPI3_MOSI_PA5"),
222 PINCTRL_PIN(TEGRA_PIN_SPI3_CS0_PA6, "SPI3_CS0_PA6"),
223 PINCTRL_PIN(TEGRA_PIN_SPI3_CS1_PA7, "SPI3_CS1_PA7"),
224 PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PB0, "SPI1_SCK_PB0"),
225 PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PB1, "SPI1_MISO_PB1"),
226 PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PB2, "SPI1_MOSI_PB2"),
227 PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PB3, "SPI1_CS0_PB3"),
228 PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PB4, "SPI1_CS1_PB4"),
229 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PC0, "PWR_I2C_SCL_PC0"),
230 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PC1, "PWR_I2C_SDA_PC1"),
231 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PC2, "EXTPERIPH1_CLK_PC2"),
232 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PC3, "EXTPERIPH2_CLK_PC3"),
233 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PC4, "CAM_I2C_SCL_PC4"),
234 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PC5, "CAM_I2C_SDA_PC5"),
235 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO23_PC6, "SOC_GPIO23_PC6"),
236 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO24_PC7, "SOC_GPIO24_PC7"),
237 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO27_PD0, "SOC_GPIO27_PD0"),
238 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO55_PD1, "SOC_GPIO55_PD1"),
239 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO29_PD2, "SOC_GPIO29_PD2"),
240 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO33_PD3, "SOC_GPIO33_PD3"),
241 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO32_PD4, "SOC_GPIO32_PD4"),
242 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO35_PD5, "SOC_GPIO35_PD5"),
243 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO37_PD6, "SOC_GPIO37_PD6"),
244 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO56_PD7, "SOC_GPIO56_PD7"),
245 PINCTRL_PIN(TEGRA_PIN_UART1_TX_PE0, "UART1_TX_PE0"),
246 PINCTRL_PIN(TEGRA_PIN_UART1_RX_PE1, "UART1_RX_PE1"),
247 PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PE2, "UART1_RTS_PE2"),
248 PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PE3, "UART1_CTS_PE3"),
249 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO13_PF0, "SOC_GPIO13_PF0"),
250 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO14_PF1, "SOC_GPIO14_PF1"),
251 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO15_PF2, "SOC_GPIO15_PF2"),
252 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO16_PF3, "SOC_GPIO16_PF3"),
253 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO17_PF4, "SOC_GPIO17_PF4"),
254 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO18_PF5, "SOC_GPIO18_PF5"),
255 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO20_PF6, "SOC_GPIO20_PF6"),
256 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO21_PF7, "SOC_GPIO21_PF7"),
257 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO22_PG0, "SOC_GPIO22_PG0"),
258 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO06_PG1, "SOC_GPIO06_PG1"),
259 PINCTRL_PIN(TEGRA_PIN_UART4_TX_PG2, "UART4_TX_PG2"),
260 PINCTRL_PIN(TEGRA_PIN_UART4_RX_PG3, "UART4_RX_PG3"),
261 PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PG4, "UART4_RTS_PG4"),
262 PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PG5, "UART4_CTS_PG5"),
263 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO41_PG6, "SOC_GPIO41_PG6"),
264 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO42_PG7, "SOC_GPIO42_PG7"),
265 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO43_PH0, "SOC_GPIO43_PH0"),
266 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO44_PH1, "SOC_GPIO44_PH1"),
267 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PH2, "GEN1_I2C_SCL_PH2"),
268 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PH3, "GEN1_I2C_SDA_PH3"),
269 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ_PH4, "CPU_PWR_REQ_PH4"),
270 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO07_PH5, "SOC_GPIO07_PH5"),
271 PINCTRL_PIN(TEGRA_PIN_DAP3_CLK_PJ0, "DAP3_CLK_PJ0"),
272 PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PJ1, "DAP3_DOUT_PJ1"),
273 PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PJ2, "DAP3_DIN_PJ2"),
274 PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PJ3, "DAP3_FS_PJ3"),
275 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO57_PJ4, "SOC_GPIO57_PJ4"),
276 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO58_PJ5, "SOC_GPIO58_PJ5"),
277 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO59_PJ6, "SOC_GPIO59_PJ6"),
278 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO60_PJ7, "SOC_GPIO60_PJ7"),
279 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO45_PK0, "SOC_GPIO45_PK0"),
280 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO46_PK1, "SOC_GPIO46_PK1"),
281 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO47_PK2, "SOC_GPIO47_PK2"),
282 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO48_PK3, "SOC_GPIO48_PK3"),
283 PINCTRL_PIN(TEGRA_PIN_QSPI0_SCK_PL0, "QSPI0_SCK_PL0"),
284 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO0_PL1, "QSPI0_IO0_PL1"),
285 PINCTRL_PIN(TEGRA_PIN_QSPI0_IO1_PL2, "QSPI0_IO1_PL2"),
286 PINCTRL_PIN(TEGRA_PIN_QSPI0_CS_N_PL3, "QSPI0_CS_N_PL3"),
287 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO152_PL4, "SOC_GPIO152_PL4"),
288 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO153_PL5, "SOC_GPIO153_PL5"),
289 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO154_PL6, "SOC_GPIO154_PL6"),
290 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO155_PL7, "SOC_GPIO155_PL7"),
291 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO156_PM0, "SOC_GPIO156_PM0"),
292 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO157_PM1, "SOC_GPIO157_PM1"),
293 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO158_PM2, "SOC_GPIO158_PM2"),
294 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO159_PM3, "SOC_GPIO159_PM3"),
295 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO160_PM4, "SOC_GPIO160_PM4"),
296 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO161_PM5, "SOC_GPIO161_PM5"),
297 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO162_PM6, "SOC_GPIO162_PM6"),
298 PINCTRL_PIN(TEGRA_PIN_UART7_TX_PM7, "UART7_TX_PM7"),
299 PINCTRL_PIN(TEGRA_PIN_UART7_RX_PN0, "UART7_RX_PN0"),
300 PINCTRL_PIN(TEGRA_PIN_UART7_RTS_PN1, "UART7_RTS_PN1"),
301 PINCTRL_PIN(TEGRA_PIN_UART7_CTS_PN2, "UART7_CTS_PN2"),
302 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO167_PP0, "SOC_GPIO167_PP0"),
303 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO168_PP1, "SOC_GPIO168_PP1"),
304 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO169_PP2, "SOC_GPIO169_PP2"),
305 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO170_PP3, "SOC_GPIO170_PP3"),
306 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP4, "DAP4_SCLK_PP4"),
307 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP5, "DAP4_DOUT_PP5"),
308 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP6, "DAP4_DIN_PP6"),
309 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP7, "DAP4_FS_PP7"),
310 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO171_PQ0, "SOC_GPIO171_PQ0"),
311 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO172_PQ1, "SOC_GPIO172_PQ1"),
312 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO173_PQ2, "SOC_GPIO173_PQ2"),
313 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO61_PR0, "SOC_GPIO61_PR0"),
314 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO62_PR1, "SOC_GPIO62_PR1"),
315 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO63_PR2, "SOC_GPIO63_PR2"),
316 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO64_PR3, "SOC_GPIO64_PR3"),
317 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO65_PR4, "SOC_GPIO65_PR4"),
318 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO66_PR5, "SOC_GPIO66_PR5"),
319 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO67_PR6, "SOC_GPIO67_PR6"),
320 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO68_PR7, "SOC_GPIO68_PR7"),
321 PINCTRL_PIN(TEGRA_PIN_GEN4_I2C_SCL_PS0, "GEN4_I2C_SCL_PS0"),
322 PINCTRL_PIN(TEGRA_PIN_GEN4_I2C_SDA_PS1, "GEN4_I2C_SDA_PS1"),
323 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO75_PS2, "SOC_GPIO75_PS2"),
324 PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PS3, "GEN7_I2C_SCL_PS3"),
325 PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PS4, "GEN7_I2C_SDA_PS4"),
326 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO78_PS5, "SOC_GPIO78_PS5"),
327 PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PS6, "GEN9_I2C_SCL_PS6"),
328 PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PS7, "GEN9_I2C_SDA_PS7"),
329 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO81_PT0, "SOC_GPIO81_PT0"),
330 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO36_PT1, "SOC_GPIO36_PT1"),
331 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO53_PT2, "SOC_GPIO53_PT2"),
332 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO38_PT3, "SOC_GPIO38_PT3"),
333 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO40_PT4, "SOC_GPIO40_PT4"),
334 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO34_PT5, "SOC_GPIO34_PT5"),
335 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PT6, "USB_VBUS_EN0_PT6"),
336 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PT7, "USB_VBUS_EN1_PT7"),
337 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PU0, "SDMMC1_CLK_PU0"),
338 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PU1, "SDMMC1_CMD_PU1"),
339 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PU2, "SDMMC1_DAT0_PU2"),
340 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PU3, "SDMMC1_DAT1_PU3"),
341 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PU4, "SDMMC1_DAT2_PU4"),
342 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PU5, "SDMMC1_DAT3_PU5"),
343 PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PV0, "UFS0_REF_CLK_PV0"),
344 PINCTRL_PIN(TEGRA_PIN_UFS0_RST_N_PV1, "UFS0_RST_N_PV1"),
345 PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PW0, "PEX_L0_CLKREQ_N_PW0"),
346 PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PW1, "PEX_L0_RST_N_PW1"),
347 PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PW2, "PEX_L1_CLKREQ_N_PW2"),
348 PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PW3, "PEX_L1_RST_N_PW3"),
349 PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PW4, "PEX_L2_CLKREQ_N_PW4"),
350 PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PW5, "PEX_L2_RST_N_PW5"),
351 PINCTRL_PIN(TEGRA_PIN_PEX_L3_CLKREQ_N_PW6, "PEX_L3_CLKREQ_N_PW6"),
352 PINCTRL_PIN(TEGRA_PIN_PEX_L3_RST_N_PW7, "PEX_L3_RST_N_PW7"),
353 PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PX0, "PEX_WAKE_N_PX0"),
354 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PX1, "DP_AUX_CH0_HPD_PX1"),
355 PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),
356 };
357
358 static const struct pinctrl_pin_desc tegra238_aon_pins[] = {
359 PINCTRL_PIN(TEGRA_PIN_BOOTV_CTL_N_PAA0, "BOOTV_CTL_N_PAA0"),
360 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO00_PAA1, "SOC_GPIO00_PAA1"),
361 PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PAA2, "VCOMP_ALERT_PAA2"),
362 PINCTRL_PIN(TEGRA_PIN_PWM1_PAA3, "PWM1_PAA3"),
363 PINCTRL_PIN(TEGRA_PIN_BATT_OC_PAA4, "BATT_OC_PAA4"),
364 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO04_PAA5, "SOC_GPIO04_PAA5"),
365 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO25_PAA6, "SOC_GPIO25_PAA6"),
366 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO26_PAA7, "SOC_GPIO26_PAA7"),
367 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PBB0, "HDMI_CEC_PBB0"),
368 PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"),
369 PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"),
370 PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"),
371 PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"),
372 PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_PCC4, "SPI2_CS1_PCC4"),
373 PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"),
374 PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"),
375 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"),
376 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"),
377 PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"),
378 PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"),
379 PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PDD3, "TOUCH_CLK_PDD3"),
380 PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PDD4, "DMIC1_CLK_PDD4"),
381 PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PDD5, "DMIC1_DAT_PDD5"),
382 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO19_PDD6, "SOC_GPIO19_PDD6"),
383 PINCTRL_PIN(TEGRA_PIN_PWM2_PDD7, "PWM2_PDD7"),
384 PINCTRL_PIN(TEGRA_PIN_PWM3_PEE0, "PWM3_PEE0"),
385 PINCTRL_PIN(TEGRA_PIN_PWM7_PEE1, "PWM7_PEE1"),
386 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO49_PEE2, "SOC_GPIO49_PEE2"),
387 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO82_PEE3, "SOC_GPIO82_PEE3"),
388 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO50_PEE4, "SOC_GPIO50_PEE4"),
389 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO83_PEE5, "SOC_GPIO83_PEE5"),
390 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO69_PFF0, "SOC_GPIO69_PFF0"),
391 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO70_PFF1, "SOC_GPIO70_PFF1"),
392 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO71_PFF2, "SOC_GPIO71_PFF2"),
393 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO72_PFF3, "SOC_GPIO72_PFF3"),
394 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO73_PFF4, "SOC_GPIO73_PFF4"),
395 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO74_PFF5, "SOC_GPIO74_PFF5"),
396 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO80_PFF6, "SOC_GPIO80_PFF6"),
397 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO76_PFF7, "SOC_GPIO76_PFF7"),
398 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO77_PGG0, "SOC_GPIO77_PGG0"),
399 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO84_PGG1, "SOC_GPIO84_PGG1"),
400 PINCTRL_PIN(TEGRA_PIN_UART2_TX_PGG2, "UART2_TX_PGG2"),
401 PINCTRL_PIN(TEGRA_PIN_UART2_RX_PGG3, "UART2_RX_PGG3"),
402 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PGG4, "UART2_RTS_PGG4"),
403 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PGG5, "UART2_CTS_PGG5"),
404 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO85_PGG6, "SOC_GPIO85_PGG6"),
405 PINCTRL_PIN(TEGRA_PIN_UART5_TX_PGG7, "UART5_TX_PGG7"),
406 PINCTRL_PIN(TEGRA_PIN_UART5_RX_PHH0, "UART5_RX_PHH0"),
407 PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PHH1, "UART5_RTS_PHH1"),
408 PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PHH2, "UART5_CTS_PHH2"),
409 PINCTRL_PIN(TEGRA_PIN_SOC_GPIO86_PHH3, "SOC_GPIO86_PHH3"),
410 };
411
412 static const unsigned int gpu_pwr_req_pa0_pins[] = {
413 TEGRA_PIN_GPU_PWR_REQ_PA0,
414 };
415
416 static const unsigned int gp_pwm5_pa1_pins[] = {
417 TEGRA_PIN_GP_PWM5_PA1,
418 };
419
420 static const unsigned int gp_pwm6_pa2_pins[] = {
421 TEGRA_PIN_GP_PWM6_PA2,
422 };
423
424 static const unsigned int spi3_sck_pa3_pins[] = {
425 TEGRA_PIN_SPI3_SCK_PA3,
426 };
427
428 static const unsigned int spi3_miso_pa4_pins[] = {
429 TEGRA_PIN_SPI3_MISO_PA4,
430 };
431
432 static const unsigned int spi3_mosi_pa5_pins[] = {
433 TEGRA_PIN_SPI3_MOSI_PA5,
434 };
435
436 static const unsigned int spi3_cs0_pa6_pins[] = {
437 TEGRA_PIN_SPI3_CS0_PA6,
438 };
439
440 static const unsigned int spi3_cs1_pa7_pins[] = {
441 TEGRA_PIN_SPI3_CS1_PA7,
442 };
443
444 static const unsigned int spi1_sck_pb0_pins[] = {
445 TEGRA_PIN_SPI1_SCK_PB0,
446 };
447
448 static const unsigned int spi1_miso_pb1_pins[] = {
449 TEGRA_PIN_SPI1_MISO_PB1,
450 };
451
452 static const unsigned int spi1_mosi_pb2_pins[] = {
453 TEGRA_PIN_SPI1_MOSI_PB2,
454 };
455
456 static const unsigned int spi1_cs0_pb3_pins[] = {
457 TEGRA_PIN_SPI1_CS0_PB3,
458 };
459
460 static const unsigned int spi1_cs1_pb4_pins[] = {
461 TEGRA_PIN_SPI1_CS1_PB4,
462 };
463
464 static const unsigned int pwr_i2c_scl_pc0_pins[] = {
465 TEGRA_PIN_PWR_I2C_SCL_PC0,
466 };
467
468 static const unsigned int pwr_i2c_sda_pc1_pins[] = {
469 TEGRA_PIN_PWR_I2C_SDA_PC1,
470 };
471
472 static const unsigned int extperiph1_clk_pc2_pins[] = {
473 TEGRA_PIN_EXTPERIPH1_CLK_PC2,
474 };
475
476 static const unsigned int extperiph2_clk_pc3_pins[] = {
477 TEGRA_PIN_EXTPERIPH2_CLK_PC3,
478 };
479
480 static const unsigned int cam_i2c_scl_pc4_pins[] = {
481 TEGRA_PIN_CAM_I2C_SCL_PC4,
482 };
483
484 static const unsigned int cam_i2c_sda_pc5_pins[] = {
485 TEGRA_PIN_CAM_I2C_SDA_PC5,
486 };
487
488 static const unsigned int soc_gpio23_pc6_pins[] = {
489 TEGRA_PIN_SOC_GPIO23_PC6,
490 };
491
492 static const unsigned int soc_gpio24_pc7_pins[] = {
493 TEGRA_PIN_SOC_GPIO24_PC7,
494 };
495
496 static const unsigned int soc_gpio27_pd0_pins[] = {
497 TEGRA_PIN_SOC_GPIO27_PD0,
498 };
499
500 static const unsigned int soc_gpio55_pd1_pins[] = {
501 TEGRA_PIN_SOC_GPIO55_PD1,
502 };
503
504 static const unsigned int soc_gpio29_pd2_pins[] = {
505 TEGRA_PIN_SOC_GPIO29_PD2,
506 };
507
508 static const unsigned int soc_gpio33_pd3_pins[] = {
509 TEGRA_PIN_SOC_GPIO33_PD3,
510 };
511
512 static const unsigned int soc_gpio32_pd4_pins[] = {
513 TEGRA_PIN_SOC_GPIO32_PD4,
514 };
515
516 static const unsigned int soc_gpio35_pd5_pins[] = {
517 TEGRA_PIN_SOC_GPIO35_PD5,
518 };
519
520 static const unsigned int soc_gpio37_pd6_pins[] = {
521 TEGRA_PIN_SOC_GPIO37_PD6,
522 };
523
524 static const unsigned int soc_gpio56_pd7_pins[] = {
525 TEGRA_PIN_SOC_GPIO56_PD7,
526 };
527
528 static const unsigned int uart1_tx_pe0_pins[] = {
529 TEGRA_PIN_UART1_TX_PE0,
530 };
531
532 static const unsigned int uart1_rx_pe1_pins[] = {
533 TEGRA_PIN_UART1_RX_PE1,
534 };
535
536 static const unsigned int uart1_rts_pe2_pins[] = {
537 TEGRA_PIN_UART1_RTS_PE2,
538 };
539
540 static const unsigned int uart1_cts_pe3_pins[] = {
541 TEGRA_PIN_UART1_CTS_PE3,
542 };
543
544 static const unsigned int soc_gpio13_pf0_pins[] = {
545 TEGRA_PIN_SOC_GPIO13_PF0,
546 };
547
548 static const unsigned int soc_gpio14_pf1_pins[] = {
549 TEGRA_PIN_SOC_GPIO14_PF1,
550 };
551
552 static const unsigned int soc_gpio15_pf2_pins[] = {
553 TEGRA_PIN_SOC_GPIO15_PF2,
554 };
555
556 static const unsigned int soc_gpio16_pf3_pins[] = {
557 TEGRA_PIN_SOC_GPIO16_PF3,
558 };
559
560 static const unsigned int soc_gpio17_pf4_pins[] = {
561 TEGRA_PIN_SOC_GPIO17_PF4,
562 };
563
564 static const unsigned int soc_gpio18_pf5_pins[] = {
565 TEGRA_PIN_SOC_GPIO18_PF5,
566 };
567
568 static const unsigned int soc_gpio20_pf6_pins[] = {
569 TEGRA_PIN_SOC_GPIO20_PF6,
570 };
571
572 static const unsigned int soc_gpio21_pf7_pins[] = {
573 TEGRA_PIN_SOC_GPIO21_PF7,
574 };
575
576 static const unsigned int soc_gpio22_pg0_pins[] = {
577 TEGRA_PIN_SOC_GPIO22_PG0,
578 };
579
580 static const unsigned int soc_gpio06_pg1_pins[] = {
581 TEGRA_PIN_SOC_GPIO06_PG1,
582 };
583
584 static const unsigned int uart4_tx_pg2_pins[] = {
585 TEGRA_PIN_UART4_TX_PG2,
586 };
587
588 static const unsigned int uart4_rx_pg3_pins[] = {
589 TEGRA_PIN_UART4_RX_PG3,
590 };
591
592 static const unsigned int uart4_rts_pg4_pins[] = {
593 TEGRA_PIN_UART4_RTS_PG4,
594 };
595
596 static const unsigned int uart4_cts_pg5_pins[] = {
597 TEGRA_PIN_UART4_CTS_PG5,
598 };
599
600 static const unsigned int soc_gpio41_pg6_pins[] = {
601 TEGRA_PIN_SOC_GPIO41_PG6,
602 };
603
604 static const unsigned int soc_gpio42_pg7_pins[] = {
605 TEGRA_PIN_SOC_GPIO42_PG7,
606 };
607
608 static const unsigned int soc_gpio43_ph0_pins[] = {
609 TEGRA_PIN_SOC_GPIO43_PH0,
610 };
611
612 static const unsigned int soc_gpio44_ph1_pins[] = {
613 TEGRA_PIN_SOC_GPIO44_PH1,
614 };
615
616 static const unsigned int gen1_i2c_scl_ph2_pins[] = {
617 TEGRA_PIN_GEN1_I2C_SCL_PH2,
618 };
619
620 static const unsigned int gen1_i2c_sda_ph3_pins[] = {
621 TEGRA_PIN_GEN1_I2C_SDA_PH3,
622 };
623
624 static const unsigned int cpu_pwr_req_ph4_pins[] = {
625 TEGRA_PIN_CPU_PWR_REQ_PH4,
626 };
627
628 static const unsigned int soc_gpio07_ph5_pins[] = {
629 TEGRA_PIN_SOC_GPIO07_PH5,
630 };
631
632 static const unsigned int dap3_clk_pj0_pins[] = {
633 TEGRA_PIN_DAP3_CLK_PJ0,
634 };
635
636 static const unsigned int dap3_dout_pj1_pins[] = {
637 TEGRA_PIN_DAP3_DOUT_PJ1,
638 };
639
640 static const unsigned int dap3_din_pj2_pins[] = {
641 TEGRA_PIN_DAP3_DIN_PJ2,
642 };
643
644 static const unsigned int dap3_fs_pj3_pins[] = {
645 TEGRA_PIN_DAP3_FS_PJ3,
646 };
647
648 static const unsigned int soc_gpio57_pj4_pins[] = {
649 TEGRA_PIN_SOC_GPIO57_PJ4,
650 };
651
652 static const unsigned int soc_gpio58_pj5_pins[] = {
653 TEGRA_PIN_SOC_GPIO58_PJ5,
654 };
655
656 static const unsigned int soc_gpio59_pj6_pins[] = {
657 TEGRA_PIN_SOC_GPIO59_PJ6,
658 };
659
660 static const unsigned int soc_gpio60_pj7_pins[] = {
661 TEGRA_PIN_SOC_GPIO60_PJ7,
662 };
663
664 static const unsigned int soc_gpio45_pk0_pins[] = {
665 TEGRA_PIN_SOC_GPIO45_PK0,
666 };
667
668 static const unsigned int soc_gpio46_pk1_pins[] = {
669 TEGRA_PIN_SOC_GPIO46_PK1,
670 };
671
672 static const unsigned int soc_gpio47_pk2_pins[] = {
673 TEGRA_PIN_SOC_GPIO47_PK2,
674 };
675
676 static const unsigned int soc_gpio48_pk3_pins[] = {
677 TEGRA_PIN_SOC_GPIO48_PK3,
678 };
679
680 static const unsigned int qspi0_sck_pl0_pins[] = {
681 TEGRA_PIN_QSPI0_SCK_PL0,
682 };
683
684 static const unsigned int qspi0_io0_pl1_pins[] = {
685 TEGRA_PIN_QSPI0_IO0_PL1,
686 };
687
688 static const unsigned int qspi0_io1_pl2_pins[] = {
689 TEGRA_PIN_QSPI0_IO1_PL2,
690 };
691
692 static const unsigned int qspi0_cs_n_pl3_pins[] = {
693 TEGRA_PIN_QSPI0_CS_N_PL3,
694 };
695
696 static const unsigned int soc_gpio152_pl4_pins[] = {
697 TEGRA_PIN_SOC_GPIO152_PL4,
698 };
699
700 static const unsigned int soc_gpio153_pl5_pins[] = {
701 TEGRA_PIN_SOC_GPIO153_PL5,
702 };
703
704 static const unsigned int soc_gpio154_pl6_pins[] = {
705 TEGRA_PIN_SOC_GPIO154_PL6,
706 };
707
708 static const unsigned int soc_gpio155_pl7_pins[] = {
709 TEGRA_PIN_SOC_GPIO155_PL7,
710 };
711
712 static const unsigned int soc_gpio156_pm0_pins[] = {
713 TEGRA_PIN_SOC_GPIO156_PM0,
714 };
715
716 static const unsigned int soc_gpio157_pm1_pins[] = {
717 TEGRA_PIN_SOC_GPIO157_PM1,
718 };
719
720 static const unsigned int soc_gpio158_pm2_pins[] = {
721 TEGRA_PIN_SOC_GPIO158_PM2,
722 };
723
724 static const unsigned int soc_gpio159_pm3_pins[] = {
725 TEGRA_PIN_SOC_GPIO159_PM3,
726 };
727
728 static const unsigned int soc_gpio160_pm4_pins[] = {
729 TEGRA_PIN_SOC_GPIO160_PM4,
730 };
731
732 static const unsigned int soc_gpio161_pm5_pins[] = {
733 TEGRA_PIN_SOC_GPIO161_PM5,
734 };
735
736 static const unsigned int soc_gpio162_pm6_pins[] = {
737 TEGRA_PIN_SOC_GPIO162_PM6,
738 };
739
740 static const unsigned int uart7_tx_pm7_pins[] = {
741 TEGRA_PIN_UART7_TX_PM7,
742 };
743
744 static const unsigned int uart7_rx_pn0_pins[] = {
745 TEGRA_PIN_UART7_RX_PN0,
746 };
747
748 static const unsigned int uart7_rts_pn1_pins[] = {
749 TEGRA_PIN_UART7_RTS_PN1,
750 };
751
752 static const unsigned int uart7_cts_pn2_pins[] = {
753 TEGRA_PIN_UART7_CTS_PN2,
754 };
755
756 static const unsigned int soc_gpio167_pp0_pins[] = {
757 TEGRA_PIN_SOC_GPIO167_PP0,
758 };
759
760 static const unsigned int soc_gpio168_pp1_pins[] = {
761 TEGRA_PIN_SOC_GPIO168_PP1,
762 };
763
764 static const unsigned int soc_gpio169_pp2_pins[] = {
765 TEGRA_PIN_SOC_GPIO169_PP2,
766 };
767
768 static const unsigned int soc_gpio170_pp3_pins[] = {
769 TEGRA_PIN_SOC_GPIO170_PP3,
770 };
771
772 static const unsigned int dap4_sclk_pp4_pins[] = {
773 TEGRA_PIN_DAP4_SCLK_PP4,
774 };
775
776 static const unsigned int dap4_dout_pp5_pins[] = {
777 TEGRA_PIN_DAP4_DOUT_PP5,
778 };
779
780 static const unsigned int dap4_din_pp6_pins[] = {
781 TEGRA_PIN_DAP4_DIN_PP6,
782 };
783
784 static const unsigned int dap4_fs_pp7_pins[] = {
785 TEGRA_PIN_DAP4_FS_PP7,
786 };
787
788 static const unsigned int soc_gpio171_pq0_pins[] = {
789 TEGRA_PIN_SOC_GPIO171_PQ0,
790 };
791
792 static const unsigned int soc_gpio172_pq1_pins[] = {
793 TEGRA_PIN_SOC_GPIO172_PQ1,
794 };
795
796 static const unsigned int soc_gpio173_pq2_pins[] = {
797 TEGRA_PIN_SOC_GPIO173_PQ2,
798 };
799
800 static const unsigned int soc_gpio61_pr0_pins[] = {
801 TEGRA_PIN_SOC_GPIO61_PR0,
802 };
803
804 static const unsigned int soc_gpio62_pr1_pins[] = {
805 TEGRA_PIN_SOC_GPIO62_PR1,
806 };
807
808 static const unsigned int soc_gpio63_pr2_pins[] = {
809 TEGRA_PIN_SOC_GPIO63_PR2,
810 };
811
812 static const unsigned int soc_gpio64_pr3_pins[] = {
813 TEGRA_PIN_SOC_GPIO64_PR3,
814 };
815
816 static const unsigned int soc_gpio65_pr4_pins[] = {
817 TEGRA_PIN_SOC_GPIO65_PR4,
818 };
819
820 static const unsigned int soc_gpio66_pr5_pins[] = {
821 TEGRA_PIN_SOC_GPIO66_PR5,
822 };
823
824 static const unsigned int soc_gpio67_pr6_pins[] = {
825 TEGRA_PIN_SOC_GPIO67_PR6,
826 };
827
828 static const unsigned int soc_gpio68_pr7_pins[] = {
829 TEGRA_PIN_SOC_GPIO68_PR7,
830 };
831
832 static const unsigned int gen4_i2c_scl_ps0_pins[] = {
833 TEGRA_PIN_GEN4_I2C_SCL_PS0,
834 };
835
836 static const unsigned int gen4_i2c_sda_ps1_pins[] = {
837 TEGRA_PIN_GEN4_I2C_SDA_PS1,
838 };
839
840 static const unsigned int soc_gpio75_ps2_pins[] = {
841 TEGRA_PIN_SOC_GPIO75_PS2,
842 };
843
844 static const unsigned int gen7_i2c_scl_ps3_pins[] = {
845 TEGRA_PIN_GEN7_I2C_SCL_PS3,
846 };
847
848 static const unsigned int gen7_i2c_sda_ps4_pins[] = {
849 TEGRA_PIN_GEN7_I2C_SDA_PS4,
850 };
851
852 static const unsigned int soc_gpio78_ps5_pins[] = {
853 TEGRA_PIN_SOC_GPIO78_PS5,
854 };
855
856 static const unsigned int gen9_i2c_scl_ps6_pins[] = {
857 TEGRA_PIN_GEN9_I2C_SCL_PS6,
858 };
859
860 static const unsigned int gen9_i2c_sda_ps7_pins[] = {
861 TEGRA_PIN_GEN9_I2C_SDA_PS7,
862 };
863
864 static const unsigned int soc_gpio81_pt0_pins[] = {
865 TEGRA_PIN_SOC_GPIO81_PT0,
866 };
867
868 static const unsigned int soc_gpio36_pt1_pins[] = {
869 TEGRA_PIN_SOC_GPIO36_PT1,
870 };
871
872 static const unsigned int soc_gpio53_pt2_pins[] = {
873 TEGRA_PIN_SOC_GPIO53_PT2,
874 };
875
876 static const unsigned int soc_gpio38_pt3_pins[] = {
877 TEGRA_PIN_SOC_GPIO38_PT3,
878 };
879
880 static const unsigned int soc_gpio40_pt4_pins[] = {
881 TEGRA_PIN_SOC_GPIO40_PT4,
882 };
883
884 static const unsigned int soc_gpio34_pt5_pins[] = {
885 TEGRA_PIN_SOC_GPIO34_PT5,
886 };
887
888 static const unsigned int usb_vbus_en0_pt6_pins[] = {
889 TEGRA_PIN_USB_VBUS_EN0_PT6,
890 };
891
892 static const unsigned int usb_vbus_en1_pt7_pins[] = {
893 TEGRA_PIN_USB_VBUS_EN1_PT7,
894 };
895
896 static const unsigned int sdmmc1_clk_pu0_pins[] = {
897 TEGRA_PIN_SDMMC1_CLK_PU0,
898 };
899
900 static const unsigned int sdmmc1_cmd_pu1_pins[] = {
901 TEGRA_PIN_SDMMC1_CMD_PU1,
902 };
903
904 static const unsigned int sdmmc1_dat0_pu2_pins[] = {
905 TEGRA_PIN_SDMMC1_DAT0_PU2,
906 };
907
908 static const unsigned int sdmmc1_dat1_pu3_pins[] = {
909 TEGRA_PIN_SDMMC1_DAT1_PU3,
910 };
911
912 static const unsigned int sdmmc1_dat2_pu4_pins[] = {
913 TEGRA_PIN_SDMMC1_DAT2_PU4,
914 };
915
916 static const unsigned int sdmmc1_dat3_pu5_pins[] = {
917 TEGRA_PIN_SDMMC1_DAT3_PU5,
918 };
919
920 static const unsigned int ufs0_ref_clk_pv0_pins[] = {
921 TEGRA_PIN_UFS0_REF_CLK_PV0,
922 };
923
924 static const unsigned int ufs0_rst_n_pv1_pins[] = {
925 TEGRA_PIN_UFS0_RST_N_PV1,
926 };
927
928 static const unsigned int pex_l0_clkreq_n_pw0_pins[] = {
929 TEGRA_PIN_PEX_L0_CLKREQ_N_PW0,
930 };
931
932 static const unsigned int pex_l0_rst_n_pw1_pins[] = {
933 TEGRA_PIN_PEX_L0_RST_N_PW1,
934 };
935
936 static const unsigned int pex_l1_clkreq_n_pw2_pins[] = {
937 TEGRA_PIN_PEX_L1_CLKREQ_N_PW2,
938 };
939
940 static const unsigned int pex_l1_rst_n_pw3_pins[] = {
941 TEGRA_PIN_PEX_L1_RST_N_PW3,
942 };
943
944 static const unsigned int pex_l2_clkreq_n_pw4_pins[] = {
945 TEGRA_PIN_PEX_L2_CLKREQ_N_PW4,
946 };
947
948 static const unsigned int pex_l2_rst_n_pw5_pins[] = {
949 TEGRA_PIN_PEX_L2_RST_N_PW5,
950 };
951
952 static const unsigned int pex_l3_clkreq_n_pw6_pins[] = {
953 TEGRA_PIN_PEX_L3_CLKREQ_N_PW6,
954 };
955
956 static const unsigned int pex_l3_rst_n_pw7_pins[] = {
957 TEGRA_PIN_PEX_L3_RST_N_PW7,
958 };
959
960 static const unsigned int pex_wake_n_px0_pins[] = {
961 TEGRA_PIN_PEX_WAKE_N_PX0,
962 };
963
964 static const unsigned int dp_aux_ch0_hpd_px1_pins[] = {
965 TEGRA_PIN_DP_AUX_CH0_HPD_PX1,
966 };
967
968 static const unsigned int bootv_ctl_n_paa0_pins[] = {
969 TEGRA_PIN_BOOTV_CTL_N_PAA0,
970 };
971
972 static const unsigned int soc_gpio00_paa1_pins[] = {
973 TEGRA_PIN_SOC_GPIO00_PAA1,
974 };
975
976 static const unsigned int vcomp_alert_paa2_pins[] = {
977 TEGRA_PIN_VCOMP_ALERT_PAA2,
978 };
979
980 static const unsigned int pwm1_paa3_pins[] = {
981 TEGRA_PIN_PWM1_PAA3,
982 };
983
984 static const unsigned int batt_oc_paa4_pins[] = {
985 TEGRA_PIN_BATT_OC_PAA4,
986 };
987
988 static const unsigned int soc_gpio04_paa5_pins[] = {
989 TEGRA_PIN_SOC_GPIO04_PAA5,
990 };
991
992 static const unsigned int soc_gpio25_paa6_pins[] = {
993 TEGRA_PIN_SOC_GPIO25_PAA6,
994 };
995
996 static const unsigned int soc_gpio26_paa7_pins[] = {
997 TEGRA_PIN_SOC_GPIO26_PAA7,
998 };
999
1000 static const unsigned int hdmi_cec_pbb0_pins[] = {
1001 TEGRA_PIN_HDMI_CEC_PBB0,
1002 };
1003
1004 static const unsigned int spi2_sck_pcc0_pins[] = {
1005 TEGRA_PIN_SPI2_SCK_PCC0,
1006 };
1007
1008 static const unsigned int spi2_miso_pcc1_pins[] = {
1009 TEGRA_PIN_SPI2_MISO_PCC1,
1010 };
1011
1012 static const unsigned int spi2_mosi_pcc2_pins[] = {
1013 TEGRA_PIN_SPI2_MOSI_PCC2,
1014 };
1015
1016 static const unsigned int spi2_cs0_pcc3_pins[] = {
1017 TEGRA_PIN_SPI2_CS0_PCC3,
1018 };
1019
1020 static const unsigned int spi2_cs1_pcc4_pins[] = {
1021 TEGRA_PIN_SPI2_CS1_PCC4,
1022 };
1023
1024 static const unsigned int uart3_tx_pcc5_pins[] = {
1025 TEGRA_PIN_UART3_TX_PCC5,
1026 };
1027
1028 static const unsigned int uart3_rx_pcc6_pins[] = {
1029 TEGRA_PIN_UART3_RX_PCC6,
1030 };
1031
1032 static const unsigned int gen2_i2c_scl_pcc7_pins[] = {
1033 TEGRA_PIN_GEN2_I2C_SCL_PCC7,
1034 };
1035
1036 static const unsigned int gen2_i2c_sda_pdd0_pins[] = {
1037 TEGRA_PIN_GEN2_I2C_SDA_PDD0,
1038 };
1039
1040 static const unsigned int gen8_i2c_scl_pdd1_pins[] = {
1041 TEGRA_PIN_GEN8_I2C_SCL_PDD1,
1042 };
1043
1044 static const unsigned int gen8_i2c_sda_pdd2_pins[] = {
1045 TEGRA_PIN_GEN8_I2C_SDA_PDD2,
1046 };
1047
1048 static const unsigned int touch_clk_pdd3_pins[] = {
1049 TEGRA_PIN_TOUCH_CLK_PDD3,
1050 };
1051
1052 static const unsigned int dmic1_clk_pdd4_pins[] = {
1053 TEGRA_PIN_DMIC1_CLK_PDD4,
1054 };
1055
1056 static const unsigned int dmic1_dat_pdd5_pins[] = {
1057 TEGRA_PIN_DMIC1_DAT_PDD5,
1058 };
1059
1060 static const unsigned int soc_gpio19_pdd6_pins[] = {
1061 TEGRA_PIN_SOC_GPIO19_PDD6,
1062 };
1063
1064 static const unsigned int pwm2_pdd7_pins[] = {
1065 TEGRA_PIN_PWM2_PDD7,
1066 };
1067
1068 static const unsigned int pwm3_pee0_pins[] = {
1069 TEGRA_PIN_PWM3_PEE0,
1070 };
1071
1072 static const unsigned int pwm7_pee1_pins[] = {
1073 TEGRA_PIN_PWM7_PEE1,
1074 };
1075
1076 static const unsigned int soc_gpio49_pee2_pins[] = {
1077 TEGRA_PIN_SOC_GPIO49_PEE2,
1078 };
1079
1080 static const unsigned int soc_gpio82_pee3_pins[] = {
1081 TEGRA_PIN_SOC_GPIO82_PEE3,
1082 };
1083
1084 static const unsigned int soc_gpio50_pee4_pins[] = {
1085 TEGRA_PIN_SOC_GPIO50_PEE4,
1086 };
1087
1088 static const unsigned int soc_gpio83_pee5_pins[] = {
1089 TEGRA_PIN_SOC_GPIO83_PEE5,
1090 };
1091
1092 static const unsigned int soc_gpio69_pff0_pins[] = {
1093 TEGRA_PIN_SOC_GPIO69_PFF0,
1094 };
1095
1096 static const unsigned int soc_gpio70_pff1_pins[] = {
1097 TEGRA_PIN_SOC_GPIO70_PFF1,
1098 };
1099
1100 static const unsigned int soc_gpio71_pff2_pins[] = {
1101 TEGRA_PIN_SOC_GPIO71_PFF2,
1102 };
1103
1104 static const unsigned int soc_gpio72_pff3_pins[] = {
1105 TEGRA_PIN_SOC_GPIO72_PFF3,
1106 };
1107
1108 static const unsigned int soc_gpio73_pff4_pins[] = {
1109 TEGRA_PIN_SOC_GPIO73_PFF4,
1110 };
1111
1112 static const unsigned int soc_gpio74_pff5_pins[] = {
1113 TEGRA_PIN_SOC_GPIO74_PFF5,
1114 };
1115
1116 static const unsigned int soc_gpio80_pff6_pins[] = {
1117 TEGRA_PIN_SOC_GPIO80_PFF6,
1118 };
1119
1120 static const unsigned int soc_gpio76_pff7_pins[] = {
1121 TEGRA_PIN_SOC_GPIO76_PFF7,
1122 };
1123
1124 static const unsigned int soc_gpio77_pgg0_pins[] = {
1125 TEGRA_PIN_SOC_GPIO77_PGG0,
1126 };
1127
1128 static const unsigned int soc_gpio84_pgg1_pins[] = {
1129 TEGRA_PIN_SOC_GPIO84_PGG1,
1130 };
1131
1132 static const unsigned int uart2_tx_pgg2_pins[] = {
1133 TEGRA_PIN_UART2_TX_PGG2,
1134 };
1135
1136 static const unsigned int uart2_rx_pgg3_pins[] = {
1137 TEGRA_PIN_UART2_RX_PGG3,
1138 };
1139
1140 static const unsigned int uart2_rts_pgg4_pins[] = {
1141 TEGRA_PIN_UART2_RTS_PGG4,
1142 };
1143
1144 static const unsigned int uart2_cts_pgg5_pins[] = {
1145 TEGRA_PIN_UART2_CTS_PGG5,
1146 };
1147
1148 static const unsigned int soc_gpio85_pgg6_pins[] = {
1149 TEGRA_PIN_SOC_GPIO85_PGG6,
1150 };
1151
1152 static const unsigned int uart5_tx_pgg7_pins[] = {
1153 TEGRA_PIN_UART5_TX_PGG7,
1154 };
1155
1156 static const unsigned int uart5_rx_phh0_pins[] = {
1157 TEGRA_PIN_UART5_RX_PHH0,
1158 };
1159
1160 static const unsigned int uart5_rts_phh1_pins[] = {
1161 TEGRA_PIN_UART5_RTS_PHH1,
1162 };
1163
1164 static const unsigned int uart5_cts_phh2_pins[] = {
1165 TEGRA_PIN_UART5_CTS_PHH2,
1166 };
1167
1168 static const unsigned int soc_gpio86_phh3_pins[] = {
1169 TEGRA_PIN_SOC_GPIO86_PHH3,
1170 };
1171
1172 static const unsigned int sdmmc1_comp_pins[] = {
1173 TEGRA_PIN_SDMMC1_COMP,
1174 };
1175
1176 /* Define unique ID for each function */
1177 enum tegra_mux_dt {
1178 TEGRA_MUX_DCA_VSYNC,
1179 TEGRA_MUX_DCA_HSYNC,
1180 TEGRA_MUX_DISPLAYA,
1181 TEGRA_MUX_RSVD0,
1182 TEGRA_MUX_I2C7_CLK,
1183 TEGRA_MUX_I2C7_DAT,
1184 TEGRA_MUX_I2C4_DAT,
1185 TEGRA_MUX_I2C4_CLK,
1186 TEGRA_MUX_I2C9_DAT,
1187 TEGRA_MUX_I2C9_CLK,
1188 TEGRA_MUX_USB_VBUS_EN0,
1189 TEGRA_MUX_USB_VBUS_EN1,
1190 TEGRA_MUX_SPI3_DIN,
1191 TEGRA_MUX_SPI1_CS0,
1192 TEGRA_MUX_SPI3_CS0,
1193 TEGRA_MUX_SPI1_DIN,
1194 TEGRA_MUX_SPI3_CS1,
1195 TEGRA_MUX_SPI1_SCK,
1196 TEGRA_MUX_SPI3_SCK,
1197 TEGRA_MUX_SPI1_CS1,
1198 TEGRA_MUX_SPI1_DOUT,
1199 TEGRA_MUX_SPI3_DOUT,
1200 TEGRA_MUX_GP_PWM5,
1201 TEGRA_MUX_GP_PWM6,
1202 TEGRA_MUX_EXTPERIPH2_CLK,
1203 TEGRA_MUX_EXTPERIPH1_CLK,
1204 TEGRA_MUX_I2C3_DAT,
1205 TEGRA_MUX_I2C3_CLK,
1206 TEGRA_MUX_EXTPERIPH4_CLK,
1207 TEGRA_MUX_EXTPERIPH3_CLK,
1208 TEGRA_MUX_DMIC2_DAT,
1209 TEGRA_MUX_DMIC2_CLK,
1210 TEGRA_MUX_UARTA_CTS,
1211 TEGRA_MUX_UARTA_RTS,
1212 TEGRA_MUX_UARTA_RXD,
1213 TEGRA_MUX_UARTA_TXD,
1214 TEGRA_MUX_I2C5_CLK,
1215 TEGRA_MUX_I2C5_DAT,
1216 TEGRA_MUX_UARTD_CTS,
1217 TEGRA_MUX_UARTD_RTS,
1218 TEGRA_MUX_UARTD_RXD,
1219 TEGRA_MUX_UARTD_TXD,
1220 TEGRA_MUX_I2C1_CLK,
1221 TEGRA_MUX_I2C1_DAT,
1222 TEGRA_MUX_SDMMC1_CD,
1223 TEGRA_MUX_I2S2_SCLK,
1224 TEGRA_MUX_I2S2_SDATA_OUT,
1225 TEGRA_MUX_I2S2_SDATA_IN,
1226 TEGRA_MUX_I2S2_LRCK,
1227 TEGRA_MUX_I2S4_SCLK,
1228 TEGRA_MUX_I2S4_SDATA_OUT,
1229 TEGRA_MUX_I2S4_SDATA_IN,
1230 TEGRA_MUX_I2S4_LRCK,
1231 TEGRA_MUX_I2S1_SCLK,
1232 TEGRA_MUX_I2S1_SDATA_OUT,
1233 TEGRA_MUX_I2S1_SDATA_IN,
1234 TEGRA_MUX_I2S1_LRCK,
1235 TEGRA_MUX_AUD_MCLK,
1236 TEGRA_MUX_I2S3_LRCK,
1237 TEGRA_MUX_I2S3_SCLK,
1238 TEGRA_MUX_I2S3_SDATA_IN,
1239 TEGRA_MUX_I2S3_SDATA_OUT,
1240 TEGRA_MUX_PE2_CLKREQ_L,
1241 TEGRA_MUX_PE1_CLKREQ_L,
1242 TEGRA_MUX_PE1_RST_L,
1243 TEGRA_MUX_PE0_CLKREQ_L,
1244 TEGRA_MUX_PE0_RST_L,
1245 TEGRA_MUX_PE2_RST_L,
1246 TEGRA_MUX_PE3_CLKREQ_L,
1247 TEGRA_MUX_PE3_RST_L,
1248 TEGRA_MUX_DP_AUX_CH0_HPD,
1249 TEGRA_MUX_QSPI0_IO0,
1250 TEGRA_MUX_QSPI0_IO1,
1251 TEGRA_MUX_QSPI0_SCK,
1252 TEGRA_MUX_QSPI0_CS_N,
1253 TEGRA_MUX_UARTG_CTS,
1254 TEGRA_MUX_UARTG_RTS,
1255 TEGRA_MUX_UARTG_TXD,
1256 TEGRA_MUX_UARTG_RXD,
1257 TEGRA_MUX_SDMMC1_CLK,
1258 TEGRA_MUX_SDMMC1_CMD,
1259 TEGRA_MUX_SDMMC1_COMP,
1260 TEGRA_MUX_SDMMC1_DAT3,
1261 TEGRA_MUX_SDMMC1_DAT2,
1262 TEGRA_MUX_SDMMC1_DAT1,
1263 TEGRA_MUX_SDMMC1_DAT0,
1264 TEGRA_MUX_UFS0,
1265 TEGRA_MUX_SOC_THERM_OC1,
1266 TEGRA_MUX_HDMI_CEC,
1267 TEGRA_MUX_GP_PWM4,
1268 TEGRA_MUX_UARTC_RXD,
1269 TEGRA_MUX_UARTC_TXD,
1270 TEGRA_MUX_I2C8_DAT,
1271 TEGRA_MUX_I2C8_CLK,
1272 TEGRA_MUX_SPI2_DOUT,
1273 TEGRA_MUX_I2C2_CLK,
1274 TEGRA_MUX_SPI2_CS0,
1275 TEGRA_MUX_I2C2_DAT,
1276 TEGRA_MUX_SPI2_SCK,
1277 TEGRA_MUX_SPI2_DIN,
1278 TEGRA_MUX_PPC_MODE_1,
1279 TEGRA_MUX_PPC_READY,
1280 TEGRA_MUX_PPC_MODE_2,
1281 TEGRA_MUX_PPC_CC,
1282 TEGRA_MUX_PPC_MODE_0,
1283 TEGRA_MUX_PPC_INT_N,
1284 TEGRA_MUX_UARTE_TXD,
1285 TEGRA_MUX_UARTE_RXD,
1286 TEGRA_MUX_UARTB_TXD,
1287 TEGRA_MUX_UARTB_RXD,
1288 TEGRA_MUX_UARTB_CTS,
1289 TEGRA_MUX_UARTB_RTS,
1290 TEGRA_MUX_UARTE_CTS,
1291 TEGRA_MUX_UARTE_RTS,
1292 TEGRA_MUX_GP_PWM7,
1293 TEGRA_MUX_GP_PWM2,
1294 TEGRA_MUX_GP_PWM3,
1295 TEGRA_MUX_GP_PWM1,
1296 TEGRA_MUX_SPI2_CS1,
1297 TEGRA_MUX_DMIC1_CLK,
1298 TEGRA_MUX_DMIC1_DAT,
1299 TEGRA_MUX_RSVD1,
1300 TEGRA_MUX_DCB_HSYNC,
1301 TEGRA_MUX_DCB_VSYNC,
1302 TEGRA_MUX_SOC_THERM_OC4,
1303 TEGRA_MUX_GP_PWM8,
1304 TEGRA_MUX_NV_THERM_FAN_TACH0,
1305 TEGRA_MUX_WDT_RESET_OUTA,
1306 TEGRA_MUX_CCLA_LA_TRIGGER_MUX,
1307 TEGRA_MUX_DSPK1_DAT,
1308 TEGRA_MUX_DSPK1_CLK,
1309 TEGRA_MUX_NV_THERM_FAN_TACH1,
1310 TEGRA_MUX_DSPK0_DAT,
1311 TEGRA_MUX_DSPK0_CLK,
1312 TEGRA_MUX_I2S5_SCLK,
1313 TEGRA_MUX_I2S6_LRCK,
1314 TEGRA_MUX_I2S6_SDATA_IN,
1315 TEGRA_MUX_I2S6_SCLK,
1316 TEGRA_MUX_I2S6_SDATA_OUT,
1317 TEGRA_MUX_I2S5_LRCK,
1318 TEGRA_MUX_I2S5_SDATA_OUT,
1319 TEGRA_MUX_I2S5_SDATA_IN,
1320 TEGRA_MUX_SDMMC1_PE3_RST_L,
1321 TEGRA_MUX_SDMMC1_PE3_CLKREQ_L,
1322 TEGRA_MUX_TOUCH_CLK,
1323 TEGRA_MUX_PPC_I2C_DAT,
1324 TEGRA_MUX_WDT_RESET_OUTB,
1325 TEGRA_MUX_SPI5_CS1,
1326 TEGRA_MUX_PPC_RST_N,
1327 TEGRA_MUX_PPC_I2C_CLK,
1328 TEGRA_MUX_SPI4_CS1,
1329 TEGRA_MUX_SOC_THERM_OC3,
1330 TEGRA_MUX_SPI5_SCK,
1331 TEGRA_MUX_SPI5_MISO,
1332 TEGRA_MUX_SPI4_SCK,
1333 TEGRA_MUX_SPI4_MISO,
1334 TEGRA_MUX_SPI4_CS0,
1335 TEGRA_MUX_SPI4_MOSI,
1336 TEGRA_MUX_SPI5_CS0,
1337 TEGRA_MUX_SPI5_MOSI,
1338 TEGRA_MUX_LED_BLINK,
1339 TEGRA_MUX_RSVD2,
1340 TEGRA_MUX_DMIC3_CLK,
1341 TEGRA_MUX_DMIC3_DAT,
1342 TEGRA_MUX_DMIC4_CLK,
1343 TEGRA_MUX_DMIC4_DAT,
1344 TEGRA_MUX_TSC_EDGE_OUT0,
1345 TEGRA_MUX_TSC_EDGE_OUT3,
1346 TEGRA_MUX_TSC_EDGE_OUT1,
1347 TEGRA_MUX_TSC_EDGE_OUT2,
1348 TEGRA_MUX_DMIC5_CLK,
1349 TEGRA_MUX_DMIC5_DAT,
1350 TEGRA_MUX_RSVD3,
1351 TEGRA_MUX_SDMMC1_WP,
1352 TEGRA_MUX_TSC_EDGE_OUT0A,
1353 TEGRA_MUX_TSC_EDGE_OUT0D,
1354 TEGRA_MUX_TSC_EDGE_OUT0B,
1355 TEGRA_MUX_TSC_EDGE_OUT0C,
1356 TEGRA_MUX_SOC_THERM_OC2,
1357 };
1358
1359 /* Make list of each function name */
1360 #define TEGRA_PIN_FUNCTION(lid) #lid
1361
1362 static const char * const tegra238_functions[] = {
1363 TEGRA_PIN_FUNCTION(dca_vsync),
1364 TEGRA_PIN_FUNCTION(dca_hsync),
1365 TEGRA_PIN_FUNCTION(displaya),
1366 TEGRA_PIN_FUNCTION(rsvd0),
1367 TEGRA_PIN_FUNCTION(i2c7_clk),
1368 TEGRA_PIN_FUNCTION(i2c7_dat),
1369 TEGRA_PIN_FUNCTION(i2c4_dat),
1370 TEGRA_PIN_FUNCTION(i2c4_clk),
1371 TEGRA_PIN_FUNCTION(i2c9_dat),
1372 TEGRA_PIN_FUNCTION(i2c9_clk),
1373 TEGRA_PIN_FUNCTION(usb_vbus_en0),
1374 TEGRA_PIN_FUNCTION(usb_vbus_en1),
1375 TEGRA_PIN_FUNCTION(spi3_din),
1376 TEGRA_PIN_FUNCTION(spi1_cs0),
1377 TEGRA_PIN_FUNCTION(spi3_cs0),
1378 TEGRA_PIN_FUNCTION(spi1_din),
1379 TEGRA_PIN_FUNCTION(spi3_cs1),
1380 TEGRA_PIN_FUNCTION(spi1_sck),
1381 TEGRA_PIN_FUNCTION(spi3_sck),
1382 TEGRA_PIN_FUNCTION(spi1_cs1),
1383 TEGRA_PIN_FUNCTION(spi1_dout),
1384 TEGRA_PIN_FUNCTION(spi3_dout),
1385 TEGRA_PIN_FUNCTION(gp_pwm5),
1386 TEGRA_PIN_FUNCTION(gp_pwm6),
1387 TEGRA_PIN_FUNCTION(extperiph2_clk),
1388 TEGRA_PIN_FUNCTION(extperiph1_clk),
1389 TEGRA_PIN_FUNCTION(i2c3_dat),
1390 TEGRA_PIN_FUNCTION(i2c3_clk),
1391 TEGRA_PIN_FUNCTION(extperiph4_clk),
1392 TEGRA_PIN_FUNCTION(extperiph3_clk),
1393 TEGRA_PIN_FUNCTION(dmic2_dat),
1394 TEGRA_PIN_FUNCTION(dmic2_clk),
1395 TEGRA_PIN_FUNCTION(uarta_cts),
1396 TEGRA_PIN_FUNCTION(uarta_rts),
1397 TEGRA_PIN_FUNCTION(uarta_rxd),
1398 TEGRA_PIN_FUNCTION(uarta_txd),
1399 TEGRA_PIN_FUNCTION(i2c5_clk),
1400 TEGRA_PIN_FUNCTION(i2c5_dat),
1401 TEGRA_PIN_FUNCTION(uartd_cts),
1402 TEGRA_PIN_FUNCTION(uartd_rts),
1403 TEGRA_PIN_FUNCTION(uartd_rxd),
1404 TEGRA_PIN_FUNCTION(uartd_txd),
1405 TEGRA_PIN_FUNCTION(i2c1_clk),
1406 TEGRA_PIN_FUNCTION(i2c1_dat),
1407 TEGRA_PIN_FUNCTION(sdmmc1_cd),
1408 TEGRA_PIN_FUNCTION(i2s2_sclk),
1409 TEGRA_PIN_FUNCTION(i2s2_sdata_out),
1410 TEGRA_PIN_FUNCTION(i2s2_sdata_in),
1411 TEGRA_PIN_FUNCTION(i2s2_lrck),
1412 TEGRA_PIN_FUNCTION(i2s4_sclk),
1413 TEGRA_PIN_FUNCTION(i2s4_sdata_out),
1414 TEGRA_PIN_FUNCTION(i2s4_sdata_in),
1415 TEGRA_PIN_FUNCTION(i2s4_lrck),
1416 TEGRA_PIN_FUNCTION(i2s1_sclk),
1417 TEGRA_PIN_FUNCTION(i2s1_sdata_out),
1418 TEGRA_PIN_FUNCTION(i2s1_sdata_in),
1419 TEGRA_PIN_FUNCTION(i2s1_lrck),
1420 TEGRA_PIN_FUNCTION(aud_mclk),
1421 TEGRA_PIN_FUNCTION(i2s3_lrck),
1422 TEGRA_PIN_FUNCTION(i2s3_sclk),
1423 TEGRA_PIN_FUNCTION(i2s3_sdata_in),
1424 TEGRA_PIN_FUNCTION(i2s3_sdata_out),
1425 TEGRA_PIN_FUNCTION(pe2_clkreq_l),
1426 TEGRA_PIN_FUNCTION(pe1_clkreq_l),
1427 TEGRA_PIN_FUNCTION(pe1_rst_l),
1428 TEGRA_PIN_FUNCTION(pe0_clkreq_l),
1429 TEGRA_PIN_FUNCTION(pe0_rst_l),
1430 TEGRA_PIN_FUNCTION(pe2_rst_l),
1431 TEGRA_PIN_FUNCTION(pe3_clkreq_l),
1432 TEGRA_PIN_FUNCTION(pe3_rst_l),
1433 TEGRA_PIN_FUNCTION(dp_aux_ch0_hpd),
1434 TEGRA_PIN_FUNCTION(qspi0_io0),
1435 TEGRA_PIN_FUNCTION(qspi0_io1),
1436 TEGRA_PIN_FUNCTION(qspi0_sck),
1437 TEGRA_PIN_FUNCTION(qspi0_cs_n),
1438 TEGRA_PIN_FUNCTION(uartg_cts),
1439 TEGRA_PIN_FUNCTION(uartg_rts),
1440 TEGRA_PIN_FUNCTION(uartg_txd),
1441 TEGRA_PIN_FUNCTION(uartg_rxd),
1442 TEGRA_PIN_FUNCTION(sdmmc1_clk),
1443 TEGRA_PIN_FUNCTION(sdmmc1_cmd),
1444 TEGRA_PIN_FUNCTION(sdmmc1_comp),
1445 TEGRA_PIN_FUNCTION(sdmmc1_dat3),
1446 TEGRA_PIN_FUNCTION(sdmmc1_dat2),
1447 TEGRA_PIN_FUNCTION(sdmmc1_dat1),
1448 TEGRA_PIN_FUNCTION(sdmmc1_dat0),
1449 TEGRA_PIN_FUNCTION(ufs0),
1450 TEGRA_PIN_FUNCTION(soc_therm_oc1),
1451 TEGRA_PIN_FUNCTION(hdmi_cec),
1452 TEGRA_PIN_FUNCTION(gp_pwm4),
1453 TEGRA_PIN_FUNCTION(uartc_rxd),
1454 TEGRA_PIN_FUNCTION(uartc_txd),
1455 TEGRA_PIN_FUNCTION(i2c8_dat),
1456 TEGRA_PIN_FUNCTION(i2c8_clk),
1457 TEGRA_PIN_FUNCTION(spi2_dout),
1458 TEGRA_PIN_FUNCTION(i2c2_clk),
1459 TEGRA_PIN_FUNCTION(spi2_cs0),
1460 TEGRA_PIN_FUNCTION(i2c2_dat),
1461 TEGRA_PIN_FUNCTION(spi2_sck),
1462 TEGRA_PIN_FUNCTION(spi2_din),
1463 TEGRA_PIN_FUNCTION(ppc_mode_1),
1464 TEGRA_PIN_FUNCTION(ppc_ready),
1465 TEGRA_PIN_FUNCTION(ppc_mode_2),
1466 TEGRA_PIN_FUNCTION(ppc_cc),
1467 TEGRA_PIN_FUNCTION(ppc_mode_0),
1468 TEGRA_PIN_FUNCTION(ppc_int_n),
1469 TEGRA_PIN_FUNCTION(uarte_txd),
1470 TEGRA_PIN_FUNCTION(uarte_rxd),
1471 TEGRA_PIN_FUNCTION(uartb_txd),
1472 TEGRA_PIN_FUNCTION(uartb_rxd),
1473 TEGRA_PIN_FUNCTION(uartb_cts),
1474 TEGRA_PIN_FUNCTION(uartb_rts),
1475 TEGRA_PIN_FUNCTION(uarte_cts),
1476 TEGRA_PIN_FUNCTION(uarte_rts),
1477 TEGRA_PIN_FUNCTION(gp_pwm7),
1478 TEGRA_PIN_FUNCTION(gp_pwm2),
1479 TEGRA_PIN_FUNCTION(gp_pwm3),
1480 TEGRA_PIN_FUNCTION(gp_pwm1),
1481 TEGRA_PIN_FUNCTION(spi2_cs1),
1482 TEGRA_PIN_FUNCTION(dmic1_clk),
1483 TEGRA_PIN_FUNCTION(dmic1_dat),
1484 TEGRA_PIN_FUNCTION(rsvd1),
1485 TEGRA_PIN_FUNCTION(dcb_hsync),
1486 TEGRA_PIN_FUNCTION(dcb_vsync),
1487 TEGRA_PIN_FUNCTION(soc_therm_oc4),
1488 TEGRA_PIN_FUNCTION(gp_pwm8),
1489 TEGRA_PIN_FUNCTION(nv_therm_fan_tach0),
1490 TEGRA_PIN_FUNCTION(wdt_reset_outa),
1491 TEGRA_PIN_FUNCTION(ccla_la_trigger_mux),
1492 TEGRA_PIN_FUNCTION(dspk1_dat),
1493 TEGRA_PIN_FUNCTION(dspk1_clk),
1494 TEGRA_PIN_FUNCTION(nv_therm_fan_tach1),
1495 TEGRA_PIN_FUNCTION(dspk0_dat),
1496 TEGRA_PIN_FUNCTION(dspk0_clk),
1497 TEGRA_PIN_FUNCTION(i2s5_sclk),
1498 TEGRA_PIN_FUNCTION(i2s6_lrck),
1499 TEGRA_PIN_FUNCTION(i2s6_sdata_in),
1500 TEGRA_PIN_FUNCTION(i2s6_sclk),
1501 TEGRA_PIN_FUNCTION(i2s6_sdata_out),
1502 TEGRA_PIN_FUNCTION(i2s5_lrck),
1503 TEGRA_PIN_FUNCTION(i2s5_sdata_out),
1504 TEGRA_PIN_FUNCTION(i2s5_sdata_in),
1505 TEGRA_PIN_FUNCTION(sdmmc1_pe3_rst_l),
1506 TEGRA_PIN_FUNCTION(sdmmc1_pe3_clkreq_l),
1507 TEGRA_PIN_FUNCTION(touch_clk),
1508 TEGRA_PIN_FUNCTION(ppc_i2c_dat),
1509 TEGRA_PIN_FUNCTION(wdt_reset_outb),
1510 TEGRA_PIN_FUNCTION(spi5_cs1),
1511 TEGRA_PIN_FUNCTION(ppc_rst_n),
1512 TEGRA_PIN_FUNCTION(ppc_i2c_clk),
1513 TEGRA_PIN_FUNCTION(spi4_cs1),
1514 TEGRA_PIN_FUNCTION(soc_therm_oc3),
1515 TEGRA_PIN_FUNCTION(spi5_sck),
1516 TEGRA_PIN_FUNCTION(spi5_miso),
1517 TEGRA_PIN_FUNCTION(spi4_sck),
1518 TEGRA_PIN_FUNCTION(spi4_miso),
1519 TEGRA_PIN_FUNCTION(spi4_cs0),
1520 TEGRA_PIN_FUNCTION(spi4_mosi),
1521 TEGRA_PIN_FUNCTION(spi5_cs0),
1522 TEGRA_PIN_FUNCTION(spi5_mosi),
1523 TEGRA_PIN_FUNCTION(led_blink),
1524 TEGRA_PIN_FUNCTION(rsvd2),
1525 TEGRA_PIN_FUNCTION(dmic3_clk),
1526 TEGRA_PIN_FUNCTION(dmic3_dat),
1527 TEGRA_PIN_FUNCTION(dmic4_clk),
1528 TEGRA_PIN_FUNCTION(dmic4_dat),
1529 TEGRA_PIN_FUNCTION(tsc_edge_out0),
1530 TEGRA_PIN_FUNCTION(tsc_edge_out3),
1531 TEGRA_PIN_FUNCTION(tsc_edge_out1),
1532 TEGRA_PIN_FUNCTION(tsc_edge_out2),
1533 TEGRA_PIN_FUNCTION(dmic5_clk),
1534 TEGRA_PIN_FUNCTION(dmic5_dat),
1535 TEGRA_PIN_FUNCTION(rsvd3),
1536 TEGRA_PIN_FUNCTION(sdmmc1_wp),
1537 TEGRA_PIN_FUNCTION(tsc_edge_out0a),
1538 TEGRA_PIN_FUNCTION(tsc_edge_out0d),
1539 TEGRA_PIN_FUNCTION(tsc_edge_out0b),
1540 TEGRA_PIN_FUNCTION(tsc_edge_out0c),
1541 TEGRA_PIN_FUNCTION(soc_therm_oc2),
1542 };
1543
1544 #define PINGROUP_REG_Y(r) ((r))
1545 #define PINGROUP_REG_N(r) -1
1546
1547 #define DRV_PINGROUP_Y(r) ((r))
1548
1549 #define DRV_PINGROUP_ENTRY_N \
1550 .drv_reg = -1, \
1551 .drv_bank = -1, \
1552 .drvdn_bit = -1, \
1553 .drvup_bit = -1, \
1554 .slwr_bit = -1, \
1555 .slwf_bit = -1
1556
1557 #define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
1558 drvup_w, slwr_b, slwr_w, slwf_b, \
1559 slwf_w, bank) \
1560 .drv_reg = DRV_PINGROUP_Y(r), \
1561 .drv_bank = bank, \
1562 .drvdn_bit = drvdn_b, \
1563 .drvdn_width = drvdn_w, \
1564 .drvup_bit = drvup_b, \
1565 .drvup_width = drvup_w, \
1566 .slwr_bit = slwr_b, \
1567 .slwr_width = slwr_w, \
1568 .slwf_bit = slwf_b, \
1569 .slwf_width = slwf_w
1570
1571 #define PIN_PINGROUP_ENTRY_N \
1572 .mux_reg = -1, \
1573 .pupd_reg = -1, \
1574 .tri_reg = -1, \
1575 .einput_bit = -1, \
1576 .e_io_hv_bit = -1, \
1577 .odrain_bit = -1, \
1578 .lock_bit = -1, \
1579 .parked_bit = -1, \
1580 .lpmd_bit = -1, \
1581 .drvtype_bit = -1, \
1582 .lpdr_bit = -1, \
1583 .pbias_buf_bit = -1, \
1584 .preemp_bit = -1, \
1585 .rfu_in_bit = -1
1586
1587 #define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \
1588 e_lpdr, e_pbias_buf, gpio_sfio_sel, \
1589 schmitt_b) \
1590 .mux_reg = PINGROUP_REG_Y(r), \
1591 .lpmd_bit = -1, \
1592 .lock_bit = -1, \
1593 .hsm_bit = -1, \
1594 .mux_bank = bank, \
1595 .mux_bit = 0, \
1596 .pupd_reg = PINGROUP_REG_##pupd(r), \
1597 .pupd_bank = bank, \
1598 .pupd_bit = 2, \
1599 .tri_reg = PINGROUP_REG_Y(r), \
1600 .tri_bank = bank, \
1601 .tri_bit = 4, \
1602 .einput_bit = e_input, \
1603 .sfsel_bit = gpio_sfio_sel, \
1604 .schmitt_bit = schmitt_b, \
1605 .drvtype_bit = 13, \
1606 .lpdr_bit = e_lpdr,
1607
1608 #define drive_soc_gpio36_pt1 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1609 #define drive_soc_gpio53_pt2 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1610 #define drive_soc_gpio38_pt3 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1611 #define drive_soc_gpio40_pt4 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1612 #define drive_soc_gpio75_ps2 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1613 #define drive_soc_gpio81_pt0 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1614 #define drive_soc_gpio78_ps5 DRV_PINGROUP_ENTRY_Y(0x10044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1615 #define drive_soc_gpio34_pt5 DRV_PINGROUP_ENTRY_Y(0x1004c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1616 #define drive_gen7_i2c_scl_ps3 DRV_PINGROUP_ENTRY_Y(0x100a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1617 #define drive_gen7_i2c_sda_ps4 DRV_PINGROUP_ENTRY_Y(0x100ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1618 #define drive_gen4_i2c_sda_ps1 DRV_PINGROUP_ENTRY_Y(0x100b4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1619 #define drive_gen4_i2c_scl_ps0 DRV_PINGROUP_ENTRY_Y(0x100bc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1620 #define drive_gen9_i2c_sda_ps7 DRV_PINGROUP_ENTRY_Y(0x100c4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1621 #define drive_gen9_i2c_scl_ps6 DRV_PINGROUP_ENTRY_Y(0x100cc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1622 #define drive_usb_vbus_en0_pt6 DRV_PINGROUP_ENTRY_Y(0x100d4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1623 #define drive_usb_vbus_en1_pt7 DRV_PINGROUP_ENTRY_Y(0x100dc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1624 #define drive_soc_gpio61_pr0 DRV_PINGROUP_ENTRY_Y(0x1f004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1625 #define drive_soc_gpio62_pr1 DRV_PINGROUP_ENTRY_Y(0x1f00c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1626 #define drive_soc_gpio63_pr2 DRV_PINGROUP_ENTRY_Y(0x1f014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1627 #define drive_soc_gpio64_pr3 DRV_PINGROUP_ENTRY_Y(0x1f01c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1628 #define drive_soc_gpio65_pr4 DRV_PINGROUP_ENTRY_Y(0x1f024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1629 #define drive_soc_gpio66_pr5 DRV_PINGROUP_ENTRY_Y(0x1f02c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1630 #define drive_soc_gpio67_pr6 DRV_PINGROUP_ENTRY_Y(0x1f034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1631 #define drive_soc_gpio68_pr7 DRV_PINGROUP_ENTRY_Y(0x1f03c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1632 #define drive_spi3_miso_pa4 DRV_PINGROUP_ENTRY_Y(0xd004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1633 #define drive_spi1_cs0_pb3 DRV_PINGROUP_ENTRY_Y(0xd00c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1634 #define drive_spi3_cs0_pa6 DRV_PINGROUP_ENTRY_Y(0xd014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1635 #define drive_spi1_miso_pb1 DRV_PINGROUP_ENTRY_Y(0xd01c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1636 #define drive_spi3_cs1_pa7 DRV_PINGROUP_ENTRY_Y(0xd024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1637 #define drive_spi1_sck_pb0 DRV_PINGROUP_ENTRY_Y(0xd02c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1638 #define drive_spi3_sck_pa3 DRV_PINGROUP_ENTRY_Y(0xd034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1639 #define drive_spi1_cs1_pb4 DRV_PINGROUP_ENTRY_Y(0xd03c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1640 #define drive_spi1_mosi_pb2 DRV_PINGROUP_ENTRY_Y(0xd044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1641 #define drive_spi3_mosi_pa5 DRV_PINGROUP_ENTRY_Y(0xd04c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1642 #define drive_gpu_pwr_req_pa0 DRV_PINGROUP_ENTRY_Y(0xd054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1643 #define drive_gp_pwm5_pa1 DRV_PINGROUP_ENTRY_Y(0xd05c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1644 #define drive_gp_pwm6_pa2 DRV_PINGROUP_ENTRY_Y(0xd064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1645 #define drive_extperiph2_clk_pc3 DRV_PINGROUP_ENTRY_Y(0x4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1646 #define drive_extperiph1_clk_pc2 DRV_PINGROUP_ENTRY_Y(0xc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1647 #define drive_cam_i2c_sda_pc5 DRV_PINGROUP_ENTRY_Y(0x14, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1648 #define drive_cam_i2c_scl_pc4 DRV_PINGROUP_ENTRY_Y(0x1c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1649 #define drive_soc_gpio23_pc6 DRV_PINGROUP_ENTRY_Y(0x24, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1650 #define drive_soc_gpio24_pc7 DRV_PINGROUP_ENTRY_Y(0x2c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1651 #define drive_soc_gpio27_pd0 DRV_PINGROUP_ENTRY_Y(0x44, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1652 #define drive_soc_gpio29_pd2 DRV_PINGROUP_ENTRY_Y(0x54, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1653 #define drive_soc_gpio32_pd4 DRV_PINGROUP_ENTRY_Y(0x6c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1654 #define drive_soc_gpio33_pd3 DRV_PINGROUP_ENTRY_Y(0x74, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1655 #define drive_soc_gpio35_pd5 DRV_PINGROUP_ENTRY_Y(0x7c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1656 #define drive_soc_gpio37_pd6 DRV_PINGROUP_ENTRY_Y(0x84, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1657 #define drive_soc_gpio56_pd7 DRV_PINGROUP_ENTRY_Y(0x8c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1658 #define drive_soc_gpio55_pd1 DRV_PINGROUP_ENTRY_Y(0x94, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1659 #define drive_uart1_cts_pe3 DRV_PINGROUP_ENTRY_Y(0x9c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1660 #define drive_uart1_rts_pe2 DRV_PINGROUP_ENTRY_Y(0xa4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1661 #define drive_uart1_rx_pe1 DRV_PINGROUP_ENTRY_Y(0xac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1662 #define drive_uart1_tx_pe0 DRV_PINGROUP_ENTRY_Y(0xb4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1663 #define drive_pwr_i2c_scl_pc0 DRV_PINGROUP_ENTRY_Y(0xbc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1664 #define drive_pwr_i2c_sda_pc1 DRV_PINGROUP_ENTRY_Y(0xc4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1665 #define drive_cpu_pwr_req_ph4 DRV_PINGROUP_ENTRY_Y(0x4004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1666 #define drive_uart4_cts_pg5 DRV_PINGROUP_ENTRY_Y(0x400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1667 #define drive_uart4_rts_pg4 DRV_PINGROUP_ENTRY_Y(0x4014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1668 #define drive_uart4_rx_pg3 DRV_PINGROUP_ENTRY_Y(0x401c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1669 #define drive_uart4_tx_pg2 DRV_PINGROUP_ENTRY_Y(0x4024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1670 #define drive_gen1_i2c_scl_ph2 DRV_PINGROUP_ENTRY_Y(0x402c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1671 #define drive_gen1_i2c_sda_ph3 DRV_PINGROUP_ENTRY_Y(0x4034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1672 #define drive_soc_gpio20_pf6 DRV_PINGROUP_ENTRY_Y(0x403c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1673 #define drive_soc_gpio21_pf7 DRV_PINGROUP_ENTRY_Y(0x4044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1674 #define drive_soc_gpio22_pg0 DRV_PINGROUP_ENTRY_Y(0x404c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1675 #define drive_soc_gpio13_pf0 DRV_PINGROUP_ENTRY_Y(0x4054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1676 #define drive_soc_gpio14_pf1 DRV_PINGROUP_ENTRY_Y(0x405c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1677 #define drive_soc_gpio15_pf2 DRV_PINGROUP_ENTRY_Y(0x4064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1678 #define drive_soc_gpio16_pf3 DRV_PINGROUP_ENTRY_Y(0x406c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1679 #define drive_soc_gpio17_pf4 DRV_PINGROUP_ENTRY_Y(0x4074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1680 #define drive_soc_gpio18_pf5 DRV_PINGROUP_ENTRY_Y(0x407c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1681 #define drive_soc_gpio41_pg6 DRV_PINGROUP_ENTRY_Y(0x408c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1682 #define drive_soc_gpio42_pg7 DRV_PINGROUP_ENTRY_Y(0x4094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1683 #define drive_soc_gpio43_ph0 DRV_PINGROUP_ENTRY_Y(0x409c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1684 #define drive_soc_gpio44_ph1 DRV_PINGROUP_ENTRY_Y(0x40a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1685 #define drive_soc_gpio06_pg1 DRV_PINGROUP_ENTRY_Y(0x40ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1686 #define drive_soc_gpio07_ph5 DRV_PINGROUP_ENTRY_Y(0x40b4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1687 #define drive_dap4_sclk_pp4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1688 #define drive_dap4_dout_pp5 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1689 #define drive_dap4_din_pp6 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1690 #define drive_dap4_fs_pp7 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1691 #define drive_soc_gpio167_pp0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1692 #define drive_soc_gpio168_pp1 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1693 #define drive_soc_gpio169_pp2 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1694 #define drive_soc_gpio170_pp3 DRV_PINGROUP_ENTRY_Y(0x205c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1695 #define drive_soc_gpio171_pq0 DRV_PINGROUP_ENTRY_Y(0x2064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1696 #define drive_soc_gpio172_pq1 DRV_PINGROUP_ENTRY_Y(0x206c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1697 #define drive_soc_gpio173_pq2 DRV_PINGROUP_ENTRY_Y(0x2074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1698 #define drive_soc_gpio45_pk0 DRV_PINGROUP_ENTRY_Y(0x18004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1699 #define drive_soc_gpio46_pk1 DRV_PINGROUP_ENTRY_Y(0x1800c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1700 #define drive_soc_gpio47_pk2 DRV_PINGROUP_ENTRY_Y(0x18014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1701 #define drive_soc_gpio48_pk3 DRV_PINGROUP_ENTRY_Y(0x1801c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1702 #define drive_soc_gpio57_pj4 DRV_PINGROUP_ENTRY_Y(0x18024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1703 #define drive_soc_gpio58_pj5 DRV_PINGROUP_ENTRY_Y(0x1802c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1704 #define drive_soc_gpio59_pj6 DRV_PINGROUP_ENTRY_Y(0x18034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1705 #define drive_soc_gpio60_pj7 DRV_PINGROUP_ENTRY_Y(0x1803c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1706 #define drive_dap3_fs_pj3 DRV_PINGROUP_ENTRY_Y(0x18064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1707 #define drive_dap3_clk_pj0 DRV_PINGROUP_ENTRY_Y(0x1806c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1708 #define drive_dap3_din_pj2 DRV_PINGROUP_ENTRY_Y(0x18074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1709 #define drive_dap3_dout_pj1 DRV_PINGROUP_ENTRY_Y(0x1807c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1710 #define drive_pex_l2_clkreq_n_pw4 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1711 #define drive_pex_wake_n_px0 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1712 #define drive_pex_l1_clkreq_n_pw2 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1713 #define drive_pex_l1_rst_n_pw3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1714 #define drive_pex_l0_clkreq_n_pw0 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1715 #define drive_pex_l0_rst_n_pw1 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1716 #define drive_pex_l2_rst_n_pw5 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1717 #define drive_pex_l3_clkreq_n_pw6 DRV_PINGROUP_ENTRY_Y(0x703c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1718 #define drive_pex_l3_rst_n_pw7 DRV_PINGROUP_ENTRY_Y(0x7044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1719 #define drive_dp_aux_ch0_hpd_px1 DRV_PINGROUP_ENTRY_Y(0x704c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1720 #define drive_qspi0_io0_pl1 DRV_PINGROUP_ENTRY_Y(0xb004, 12, 5, 24, 5, -1, -1, -1, -1, 0)
1721 #define drive_qspi0_io1_pl2 DRV_PINGROUP_ENTRY_Y(0xb00c, 12, 5, 24, 5, -1, -1, -1, -1, 0)
1722 #define drive_qspi0_sck_pl0 DRV_PINGROUP_ENTRY_Y(0xb014, 12, 5, 24, 5, -1, -1, -1, -1, 0)
1723 #define drive_qspi0_cs_n_pl3 DRV_PINGROUP_ENTRY_Y(0xb01c, 12, 5, 24, 5, -1, -1, -1, -1, 0)
1724 #define drive_soc_gpio156_pm0 DRV_PINGROUP_ENTRY_Y(0xb024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1725 #define drive_soc_gpio155_pl7 DRV_PINGROUP_ENTRY_Y(0xb02c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1726 #define drive_soc_gpio160_pm4 DRV_PINGROUP_ENTRY_Y(0xb034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1727 #define drive_soc_gpio154_pl6 DRV_PINGROUP_ENTRY_Y(0xb03c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1728 #define drive_soc_gpio152_pl4 DRV_PINGROUP_ENTRY_Y(0xb044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1729 #define drive_soc_gpio153_pl5 DRV_PINGROUP_ENTRY_Y(0xb04c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1730 #define drive_soc_gpio161_pm5 DRV_PINGROUP_ENTRY_Y(0xb054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1731 #define drive_soc_gpio162_pm6 DRV_PINGROUP_ENTRY_Y(0xb05c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1732 #define drive_soc_gpio159_pm3 DRV_PINGROUP_ENTRY_Y(0xb064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1733 #define drive_soc_gpio157_pm1 DRV_PINGROUP_ENTRY_Y(0xb06c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1734 #define drive_soc_gpio158_pm2 DRV_PINGROUP_ENTRY_Y(0xb074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1735 #define drive_uart7_cts_pn2 DRV_PINGROUP_ENTRY_Y(0xb07c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1736 #define drive_uart7_rts_pn1 DRV_PINGROUP_ENTRY_Y(0xb084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1737 #define drive_uart7_tx_pm7 DRV_PINGROUP_ENTRY_Y(0xb08c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1738 #define drive_uart7_rx_pn0 DRV_PINGROUP_ENTRY_Y(0xb094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1739 #define drive_sdmmc1_clk_pu0 DRV_PINGROUP_ENTRY_Y(0x8004, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1740 #define drive_sdmmc1_cmd_pu1 DRV_PINGROUP_ENTRY_Y(0x800c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1741 #define drive_sdmmc1_dat3_pu5 DRV_PINGROUP_ENTRY_Y(0x801c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1742 #define drive_sdmmc1_dat2_pu4 DRV_PINGROUP_ENTRY_Y(0x8024, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1743 #define drive_sdmmc1_dat1_pu3 DRV_PINGROUP_ENTRY_Y(0x802c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1744 #define drive_sdmmc1_dat0_pu2 DRV_PINGROUP_ENTRY_Y(0x8034, 28, 2, 30, 2, -1, -1, -1, -1, 0)
1745 #define drive_ufs0_rst_n_pv1 DRV_PINGROUP_ENTRY_Y(0x11004, 12, 5, 24, 5, -1, -1, -1, -1, 0)
1746 #define drive_ufs0_ref_clk_pv0 DRV_PINGROUP_ENTRY_Y(0x1100c, 12, 5, 24, 5, -1, -1, -1, -1, 0)
1747 #define drive_batt_oc_paa4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1748 #define drive_bootv_ctl_n_paa0 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1749 #define drive_vcomp_alert_paa2 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1750 #define drive_hdmi_cec_pbb0 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1751 #define drive_touch_clk_pdd3 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1752 #define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x1074, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1753 #define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x107c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1754 #define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x1084, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1755 #define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x108c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1756 #define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x1094, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1757 #define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x109c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1758 #define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x10a4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1759 #define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x10ac, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1760 #define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x10b4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1761 #define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x10bc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1762 #define drive_soc_gpio49_pee2 DRV_PINGROUP_ENTRY_Y(0x10c4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1763 #define drive_soc_gpio50_pee4 DRV_PINGROUP_ENTRY_Y(0x10cc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1764 #define drive_soc_gpio82_pee3 DRV_PINGROUP_ENTRY_Y(0x10d4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1765 #define drive_soc_gpio71_pff2 DRV_PINGROUP_ENTRY_Y(0x10dc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1766 #define drive_soc_gpio76_pff7 DRV_PINGROUP_ENTRY_Y(0x10e4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1767 #define drive_soc_gpio74_pff5 DRV_PINGROUP_ENTRY_Y(0x10ec, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1768 #define drive_soc_gpio00_paa1 DRV_PINGROUP_ENTRY_Y(0x10f4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1769 #define drive_soc_gpio19_pdd6 DRV_PINGROUP_ENTRY_Y(0x10fc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1770 #define drive_soc_gpio86_phh3 DRV_PINGROUP_ENTRY_Y(0x1104, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1771 #define drive_soc_gpio72_pff3 DRV_PINGROUP_ENTRY_Y(0x110c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1772 #define drive_soc_gpio77_pgg0 DRV_PINGROUP_ENTRY_Y(0x1114, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1773 #define drive_soc_gpio80_pff6 DRV_PINGROUP_ENTRY_Y(0x111c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1774 #define drive_soc_gpio84_pgg1 DRV_PINGROUP_ENTRY_Y(0x1124, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1775 #define drive_soc_gpio83_pee5 DRV_PINGROUP_ENTRY_Y(0x112c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1776 #define drive_soc_gpio73_pff4 DRV_PINGROUP_ENTRY_Y(0x1134, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1777 #define drive_soc_gpio70_pff1 DRV_PINGROUP_ENTRY_Y(0x113c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1778 #define drive_soc_gpio04_paa5 DRV_PINGROUP_ENTRY_Y(0x1144, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1779 #define drive_soc_gpio85_pgg6 DRV_PINGROUP_ENTRY_Y(0x114c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1780 #define drive_soc_gpio69_pff0 DRV_PINGROUP_ENTRY_Y(0x1154, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1781 #define drive_soc_gpio25_paa6 DRV_PINGROUP_ENTRY_Y(0x115c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1782 #define drive_soc_gpio26_paa7 DRV_PINGROUP_ENTRY_Y(0x1164, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1783 #define drive_uart5_tx_pgg7 DRV_PINGROUP_ENTRY_Y(0x116c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1784 #define drive_uart5_rx_phh0 DRV_PINGROUP_ENTRY_Y(0x1174, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1785 #define drive_uart2_tx_pgg2 DRV_PINGROUP_ENTRY_Y(0x117c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1786 #define drive_uart2_rx_pgg3 DRV_PINGROUP_ENTRY_Y(0x1184, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1787 #define drive_uart2_cts_pgg5 DRV_PINGROUP_ENTRY_Y(0x118c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1788 #define drive_uart2_rts_pgg4 DRV_PINGROUP_ENTRY_Y(0x1194, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1789 #define drive_uart5_cts_phh2 DRV_PINGROUP_ENTRY_Y(0x119c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1790 #define drive_uart5_rts_phh1 DRV_PINGROUP_ENTRY_Y(0x11a4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1791 #define drive_pwm7_pee1 DRV_PINGROUP_ENTRY_Y(0x11ac, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1792 #define drive_pwm2_pdd7 DRV_PINGROUP_ENTRY_Y(0x11b4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1793 #define drive_pwm3_pee0 DRV_PINGROUP_ENTRY_Y(0x11bc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1794 #define drive_pwm1_paa3 DRV_PINGROUP_ENTRY_Y(0x11c4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1795 #define drive_spi2_cs1_pcc4 DRV_PINGROUP_ENTRY_Y(0x11cc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1796 #define drive_dmic1_clk_pdd4 DRV_PINGROUP_ENTRY_Y(0x11d4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1797 #define drive_dmic1_dat_pdd5 DRV_PINGROUP_ENTRY_Y(0x11dc, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1798
1799 #define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N
1800
1801 #define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \
1802 gpio_sfio_sel, schmitt_b) \
1803 { \
1804 .name = #pg_name, \
1805 .pins = pg_name##_pins, \
1806 .npins = ARRAY_SIZE(pg_name##_pins), \
1807 .funcs = { \
1808 TEGRA_MUX_##f0, \
1809 TEGRA_MUX_##f1, \
1810 TEGRA_MUX_##f2, \
1811 TEGRA_MUX_##f3, \
1812 }, \
1813 PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \
1814 e_input, e_lpdr, e_pbias_buf, \
1815 gpio_sfio_sel, schmitt_b) \
1816 drive_##pg_name, \
1817 }
1818
1819 static const struct tegra_pingroup tegra238_groups[] = {
1820 PINGROUP(soc_gpio36_pt1, DCA_VSYNC, RSVD1, RSVD2, RSVD3, 0x10000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1821 PINGROUP(soc_gpio53_pt2, DCA_HSYNC, RSVD1, RSVD2, RSVD3, 0x10008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1822 PINGROUP(soc_gpio38_pt3, DISPLAYA, DCB_HSYNC, RSVD2, RSVD3, 0x10018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1823 PINGROUP(soc_gpio40_pt4, RSVD0, DCB_VSYNC, RSVD2, RSVD3, 0x10028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1824 PINGROUP(soc_gpio75_ps2, RSVD0, RSVD1, RSVD2, RSVD3, 0x10030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1825 PINGROUP(soc_gpio81_pt0, RSVD0, RSVD1, RSVD2, RSVD3, 0x10038, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1826 PINGROUP(soc_gpio78_ps5, RSVD0, RSVD1, RSVD2, RSVD3, 0x10040, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1827 PINGROUP(soc_gpio34_pt5, RSVD0, RSVD1, RSVD2, RSVD3, 0x10048, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1828 PINGROUP(gen7_i2c_scl_ps3, I2C7_CLK, RSVD1, RSVD2, RSVD3, 0x100a0, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1829 PINGROUP(gen7_i2c_sda_ps4, I2C7_DAT, RSVD1, RSVD2, RSVD3, 0x100a8, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1830 PINGROUP(gen4_i2c_sda_ps1, I2C4_DAT, RSVD1, RSVD2, RSVD3, 0x100b0, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1831 PINGROUP(gen4_i2c_scl_ps0, I2C4_CLK, RSVD1, RSVD2, RSVD3, 0x100b8, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1832 PINGROUP(gen9_i2c_sda_ps7, I2C9_DAT, RSVD1, RSVD2, RSVD3, 0x100c0, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1833 PINGROUP(gen9_i2c_scl_ps6, I2C9_CLK, RSVD1, RSVD2, RSVD3, 0x100c8, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1834 PINGROUP(usb_vbus_en0_pt6, USB_VBUS_EN0, RSVD1, RSVD2, RSVD3, 0x100d0, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1835 PINGROUP(usb_vbus_en1_pt7, USB_VBUS_EN1, RSVD1, RSVD2, RSVD3, 0x100d8, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1836 PINGROUP(soc_gpio61_pr0, RSVD0, SOC_THERM_OC4, RSVD2, RSVD3, 0x1f000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1837 PINGROUP(soc_gpio62_pr1, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1838 PINGROUP(soc_gpio63_pr2, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1839 PINGROUP(soc_gpio64_pr3, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1840 PINGROUP(soc_gpio65_pr4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1841 PINGROUP(soc_gpio66_pr5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1842 PINGROUP(soc_gpio67_pr6, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f030, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1843 PINGROUP(soc_gpio68_pr7, RSVD0, RSVD1, RSVD2, RSVD3, 0x1f038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1844 PINGROUP(spi3_miso_pa4, SPI3_DIN, RSVD1, RSVD2, RSVD3, 0xd000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1845 PINGROUP(spi1_cs0_pb3, SPI1_CS0, RSVD1, RSVD2, RSVD3, 0xd008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1846 PINGROUP(spi3_cs0_pa6, SPI3_CS0, RSVD1, RSVD2, RSVD3, 0xd010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1847 PINGROUP(spi1_miso_pb1, SPI1_DIN, RSVD1, RSVD2, RSVD3, 0xd018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1848 PINGROUP(spi3_cs1_pa7, SPI3_CS1, RSVD1, RSVD2, RSVD3, 0xd020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1849 PINGROUP(spi1_sck_pb0, SPI1_SCK, RSVD1, RSVD2, RSVD3, 0xd028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1850 PINGROUP(spi3_sck_pa3, SPI3_SCK, RSVD1, RSVD2, RSVD3, 0xd030, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1851 PINGROUP(spi1_cs1_pb4, SPI1_CS1, RSVD1, RSVD2, RSVD3, 0xd038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1852 PINGROUP(spi1_mosi_pb2, SPI1_DOUT, RSVD1, RSVD2, RSVD3, 0xd040, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1853 PINGROUP(spi3_mosi_pa5, SPI3_DOUT, RSVD1, RSVD2, RSVD3, 0xd048, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1854 PINGROUP(gpu_pwr_req_pa0, RSVD0, RSVD1, RSVD2, RSVD3, 0xd050, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1855 PINGROUP(gp_pwm5_pa1, GP_PWM5, RSVD1, RSVD2, RSVD3, 0xd058, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1856 PINGROUP(gp_pwm6_pa2, GP_PWM6, RSVD1, RSVD2, RSVD3, 0xd060, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1857 PINGROUP(extperiph2_clk_pc3, EXTPERIPH2_CLK, RSVD1, RSVD2, RSVD3, 0x0000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1858 PINGROUP(extperiph1_clk_pc2, EXTPERIPH1_CLK, RSVD1, RSVD2, RSVD3, 0x0008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1859 PINGROUP(cam_i2c_sda_pc5, I2C3_DAT, RSVD1, RSVD2, RSVD3, 0x0010, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1860 PINGROUP(cam_i2c_scl_pc4, I2C3_CLK, RSVD1, RSVD2, RSVD3, 0x0018, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1861 PINGROUP(soc_gpio23_pc6, RSVD0, RSVD1, RSVD2, RSVD3, 0x0020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1862 PINGROUP(soc_gpio24_pc7, RSVD0, RSVD1, RSVD2, RSVD3, 0x0028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1863 PINGROUP(soc_gpio27_pd0, RSVD0, GP_PWM8, RSVD2, RSVD3, 0x0040, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1864 PINGROUP(soc_gpio29_pd2, RSVD0, NV_THERM_FAN_TACH0, RSVD2, RSVD3, 0x0050, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1865 PINGROUP(soc_gpio32_pd4, EXTPERIPH4_CLK, RSVD1, RSVD2, RSVD3, 0x0068, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1866 PINGROUP(soc_gpio33_pd3, EXTPERIPH3_CLK, RSVD1, RSVD2, RSVD3, 0x0070, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1867 PINGROUP(soc_gpio35_pd5, RSVD0, RSVD1, RSVD2, RSVD3, 0x0078, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1868 PINGROUP(soc_gpio37_pd6, DMIC2_DAT, RSVD1, RSVD2, RSVD3, 0x0080, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1869 PINGROUP(soc_gpio56_pd7, DMIC2_CLK, RSVD1, RSVD2, RSVD3, 0x0088, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1870 PINGROUP(soc_gpio55_pd1, RSVD0, WDT_RESET_OUTA, RSVD2, RSVD3, 0x0090, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1871 PINGROUP(uart1_cts_pe3, UARTA_CTS, RSVD1, RSVD2, RSVD3, 0x0098, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1872 PINGROUP(uart1_rts_pe2, UARTA_RTS, RSVD1, RSVD2, RSVD3, 0x00a0, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1873 PINGROUP(uart1_rx_pe1, UARTA_RXD, RSVD1, RSVD2, RSVD3, 0x00a8, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1874 PINGROUP(uart1_tx_pe0, UARTA_TXD, RSVD1, RSVD2, RSVD3, 0x00b0, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1875 PINGROUP(pwr_i2c_scl_pc0, I2C5_CLK, RSVD1, RSVD2, RSVD3, 0x00b8, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1876 PINGROUP(pwr_i2c_sda_pc1, I2C5_DAT, RSVD1, RSVD2, RSVD3, 0x00c0, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1877 PINGROUP(cpu_pwr_req_ph4, RSVD0, RSVD1, RSVD2, RSVD3, 0x4000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1878 PINGROUP(uart4_cts_pg5, UARTD_CTS, RSVD1, RSVD2, RSVD3, 0x4008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1879 PINGROUP(uart4_rts_pg4, UARTD_RTS, RSVD1, RSVD2, RSVD3, 0x4010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1880 PINGROUP(uart4_rx_pg3, UARTD_RXD, RSVD1, RSVD2, RSVD3, 0x4018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1881 PINGROUP(uart4_tx_pg2, UARTD_TXD, RSVD1, RSVD2, RSVD3, 0x4020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1882 PINGROUP(gen1_i2c_scl_ph2, I2C1_CLK, RSVD1, RSVD2, RSVD3, 0x4028, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1883 PINGROUP(gen1_i2c_sda_ph3, I2C1_DAT, RSVD1, RSVD2, RSVD3, 0x4030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1884 PINGROUP(soc_gpio20_pf6, SDMMC1_CD, RSVD1, RSVD2, RSVD3, 0x4038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1885 PINGROUP(soc_gpio21_pf7, RSVD0, RSVD1, RSVD2, RSVD3, 0x4040, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1886 PINGROUP(soc_gpio22_pg0, RSVD0, RSVD1, RSVD2, RSVD3, 0x4048, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1887 PINGROUP(soc_gpio13_pf0, RSVD0, RSVD1, RSVD2, RSVD3, 0x4050, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1888 PINGROUP(soc_gpio14_pf1, RSVD0, RSVD1, RSVD2, RSVD3, 0x4058, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1889 PINGROUP(soc_gpio15_pf2, RSVD0, RSVD1, RSVD2, RSVD3, 0x4060, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1890 PINGROUP(soc_gpio16_pf3, RSVD0, RSVD1, RSVD2, RSVD3, 0x4068, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1891 PINGROUP(soc_gpio17_pf4, RSVD0, CCLA_LA_TRIGGER_MUX, RSVD2, RSVD3, 0x4070, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1892 PINGROUP(soc_gpio18_pf5, RSVD0, RSVD1, RSVD2, RSVD3, 0x4078, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1893 PINGROUP(soc_gpio41_pg6, I2S2_SCLK, RSVD1, RSVD2, RSVD3, 0x4088, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1894 PINGROUP(soc_gpio42_pg7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x4090, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1895 PINGROUP(soc_gpio43_ph0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x4098, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1896 PINGROUP(soc_gpio44_ph1, I2S2_LRCK, RSVD1, RSVD2, RSVD3, 0x40a0, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1897 PINGROUP(soc_gpio06_pg1, RSVD0, RSVD1, RSVD2, RSVD3, 0x40a8, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1898 PINGROUP(soc_gpio07_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0x40b0, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1899 PINGROUP(dap4_sclk_pp4, I2S4_SCLK, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1900 PINGROUP(dap4_dout_pp5, I2S4_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1901 PINGROUP(dap4_din_pp6, I2S4_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1902 PINGROUP(dap4_fs_pp7, I2S4_LRCK, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1903 PINGROUP(soc_gpio167_pp0, RSVD0, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1904 PINGROUP(soc_gpio168_pp1, RSVD0, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1905 PINGROUP(soc_gpio169_pp2, RSVD0, RSVD1, RSVD2, RSVD3, 0x2050, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1906 PINGROUP(soc_gpio170_pp3, RSVD0, RSVD1, RSVD2, RSVD3, 0x2058, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1907 PINGROUP(soc_gpio171_pq0, RSVD0, RSVD1, RSVD2, RSVD3, 0x2060, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1908 PINGROUP(soc_gpio172_pq1, RSVD0, RSVD1, RSVD2, RSVD3, 0x2068, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1909 PINGROUP(soc_gpio173_pq2, RSVD0, RSVD1, RSVD2, RSVD3, 0x2070, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1910 PINGROUP(soc_gpio45_pk0, I2S1_SCLK, DSPK1_DAT, DMIC3_CLK, RSVD3, 0x18000, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1911 PINGROUP(soc_gpio46_pk1, I2S1_SDATA_OUT, DSPK1_CLK, DMIC3_DAT, RSVD3, 0x18008, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1912 PINGROUP(soc_gpio47_pk2, I2S1_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x18010, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1913 PINGROUP(soc_gpio48_pk3, I2S1_LRCK, RSVD1, RSVD2, RSVD3, 0x18018, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1914 PINGROUP(soc_gpio57_pj4, RSVD0, RSVD1, RSVD2, SDMMC1_WP, 0x18020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1915 PINGROUP(soc_gpio58_pj5, RSVD0, RSVD1, RSVD2, RSVD3, 0x18028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1916 PINGROUP(soc_gpio59_pj6, AUD_MCLK, RSVD1, RSVD2, RSVD3, 0x18030, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1917 PINGROUP(soc_gpio60_pj7, RSVD0, NV_THERM_FAN_TACH1, RSVD2, RSVD3, 0x18038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1918 PINGROUP(dap3_fs_pj3, I2S3_LRCK, RSVD1, RSVD2, RSVD3, 0x18060, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1919 PINGROUP(dap3_clk_pj0, I2S3_SCLK, DSPK0_DAT, DMIC4_CLK, RSVD3, 0x18068, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1920 PINGROUP(dap3_din_pj2, I2S3_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x18070, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1921 PINGROUP(dap3_dout_pj1, I2S3_SDATA_OUT, DSPK0_CLK, DMIC4_DAT, RSVD3, 0x18078, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1922 PINGROUP(pex_l2_clkreq_n_pw4, PE2_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x7000, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1923 PINGROUP(pex_wake_n_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0x7008, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1924 PINGROUP(pex_l1_clkreq_n_pw2, PE1_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x7010, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1925 PINGROUP(pex_l1_rst_n_pw3, PE1_RST_L, RSVD1, RSVD2, RSVD3, 0x7018, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1926 PINGROUP(pex_l0_clkreq_n_pw0, PE0_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x7020, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1927 PINGROUP(pex_l0_rst_n_pw1, PE0_RST_L, RSVD1, RSVD2, RSVD3, 0x7028, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1928 PINGROUP(pex_l2_rst_n_pw5, PE2_RST_L, RSVD1, RSVD2, RSVD3, 0x7030, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1929 PINGROUP(pex_l3_clkreq_n_pw6, PE3_CLKREQ_L, RSVD1, RSVD2, RSVD3, 0x7038, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1930 PINGROUP(pex_l3_rst_n_pw7, PE3_RST_L, RSVD1, RSVD2, RSVD3, 0x7040, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1931 PINGROUP(dp_aux_ch0_hpd_px1, DP_AUX_CH0_HPD, RSVD1, RSVD2, RSVD3, 0x7048, 0, Y, 5, 7, 6, 8, -1, 10, 12),
1932 PINGROUP(qspi0_io0_pl1, QSPI0_IO0, RSVD1, RSVD2, RSVD3, 0xb000, 0, Y, -1, 5, 6, -1, -1, 10, 12),
1933 PINGROUP(qspi0_io1_pl2, QSPI0_IO1, RSVD1, RSVD2, RSVD3, 0xb008, 0, Y, -1, 5, 6, -1, -1, 10, 12),
1934 PINGROUP(qspi0_sck_pl0, QSPI0_SCK, RSVD1, RSVD2, RSVD3, 0xb010, 0, Y, -1, 5, 6, -1, -1, 10, 12),
1935 PINGROUP(qspi0_cs_n_pl3, QSPI0_CS_N, RSVD1, RSVD2, RSVD3, 0xb018, 0, Y, -1, 5, 6, -1, -1, 10, 12),
1936 PINGROUP(soc_gpio156_pm0, RSVD0, I2S5_SCLK, RSVD2, RSVD3, 0xb020, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1937 PINGROUP(soc_gpio155_pl7, RSVD0, I2S6_LRCK, RSVD2, RSVD3, 0xb028, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1938 PINGROUP(soc_gpio160_pm4, RSVD0, RSVD1, RSVD2, RSVD3, 0xb030, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1939 PINGROUP(soc_gpio154_pl6, RSVD0, I2S6_SDATA_IN, RSVD2, RSVD3, 0xb038, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1940 PINGROUP(soc_gpio152_pl4, RSVD0, I2S6_SCLK, RSVD2, RSVD3, 0xb040, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1941 PINGROUP(soc_gpio153_pl5, RSVD0, I2S6_SDATA_OUT, RSVD2, RSVD3, 0xb048, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1942 PINGROUP(soc_gpio161_pm5, RSVD0, RSVD1, RSVD2, RSVD3, 0xb050, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1943 PINGROUP(soc_gpio162_pm6, RSVD0, RSVD1, RSVD2, RSVD3, 0xb058, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1944 PINGROUP(soc_gpio159_pm3, RSVD0, I2S5_LRCK, RSVD2, RSVD3, 0xb060, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1945 PINGROUP(soc_gpio157_pm1, RSVD0, I2S5_SDATA_OUT, RSVD2, RSVD3, 0xb068, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1946 PINGROUP(soc_gpio158_pm2, RSVD0, I2S5_SDATA_IN, RSVD2, RSVD3, 0xb070, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1947 PINGROUP(uart7_cts_pn2, UARTG_CTS, RSVD1, RSVD2, RSVD3, 0xb078, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1948 PINGROUP(uart7_rts_pn1, UARTG_RTS, RSVD1, RSVD2, RSVD3, 0xb080, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1949 PINGROUP(uart7_tx_pm7, UARTG_TXD, RSVD1, RSVD2, RSVD3, 0xb088, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1950 PINGROUP(uart7_rx_pn0, UARTG_RXD, RSVD1, RSVD2, RSVD3, 0xb090, 0, Y, -1, 7, 6, 8, -1, 10, 12),
1951 PINGROUP(sdmmc1_clk_pu0, SDMMC1_CLK, RSVD1, RSVD2, RSVD3, 0x8000, 0, Y, -1, 5, 6, -1, 9, 10, 12),
1952 PINGROUP(sdmmc1_cmd_pu1, SDMMC1_CMD, RSVD1, RSVD2, RSVD3, 0x8008, 0, Y, -1, 5, 6, -1, 9, 10, 12),
1953 PINGROUP(sdmmc1_comp, SDMMC1_COMP, RSVD1, RSVD2, RSVD3, 0x8010, 0, N, -1, -1, -1, -1, -1, -1, -1),
1954 PINGROUP(sdmmc1_dat3_pu5, SDMMC1_DAT3, SDMMC1_PE3_RST_L, RSVD2, RSVD3, 0x8018, 0, Y, -1, 5, 6, -1, 9, 10, 12),
1955 PINGROUP(sdmmc1_dat2_pu4, SDMMC1_DAT2, SDMMC1_PE3_CLKREQ_L, RSVD2, RSVD3, 0x8020, 0, Y, -1, 5, 6, -1, 9, 10, 12),
1956 PINGROUP(sdmmc1_dat1_pu3, SDMMC1_DAT1, RSVD1, RSVD2, RSVD3, 0x8028, 0, Y, -1, 5, 6, -1, 9, 10, 12),
1957 PINGROUP(sdmmc1_dat0_pu2, SDMMC1_DAT0, RSVD1, RSVD2, RSVD3, 0x8030, 0, Y, -1, 5, 6, -1, 9, 10, 12),
1958 PINGROUP(ufs0_rst_n_pv1, UFS0, RSVD1, RSVD2, RSVD3, 0x11000, 0, Y, -1, 5, 6, -1, -1, 10, 12),
1959 PINGROUP(ufs0_ref_clk_pv0, UFS0, RSVD1, RSVD2, RSVD3, 0x11008, 0, Y, -1, 5, 6, -1, -1, 10, 12),
1960
1961 };
1962
1963 static const struct tegra_pingroup tegra238_aon_groups[] = {
1964 PINGROUP(bootv_ctl_n_paa0, RSVD0, RSVD1, RSVD2, RSVD3, 0x1028, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1965 PINGROUP(soc_gpio00_paa1, RSVD0, RSVD1, RSVD2, RSVD3, 0x10f0, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1966 PINGROUP(vcomp_alert_paa2, SOC_THERM_OC1, RSVD1, RSVD2, RSVD3, 0x1058, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1967 PINGROUP(pwm1_paa3, GP_PWM1, RSVD1, RSVD2, RSVD3, 0x11c0, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1968 PINGROUP(batt_oc_paa4, SOC_THERM_OC2, RSVD1, RSVD2, RSVD3, 0x1020, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1969 PINGROUP(soc_gpio04_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1140, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1970 PINGROUP(soc_gpio25_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x1158, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1971 PINGROUP(soc_gpio26_paa7, RSVD0, SOC_THERM_OC3, RSVD2, RSVD3, 0x1160, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1972 PINGROUP(hdmi_cec_pbb0, HDMI_CEC, RSVD1, RSVD2, RSVD3, 0x1060, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1973 PINGROUP(spi2_sck_pcc0, SPI2_SCK, RSVD1, RSVD2, RSVD3, 0x10b0, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1974 PINGROUP(spi2_miso_pcc1, SPI2_DIN, RSVD1, RSVD2, RSVD3, 0x10b8, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1975 PINGROUP(spi2_mosi_pcc2, SPI2_DOUT, RSVD1, RSVD2, RSVD3, 0x1090, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1976 PINGROUP(spi2_cs0_pcc3, SPI2_CS0, RSVD1, RSVD2, RSVD3, 0x10a0, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1977 PINGROUP(spi2_cs1_pcc4, SPI2_CS1, RSVD1, RSVD2, RSVD3, 0x11c8, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1978 PINGROUP(uart3_tx_pcc5, UARTC_TXD, RSVD1, RSVD2, RSVD3, 0x1078, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1979 PINGROUP(uart3_rx_pcc6, UARTC_RXD, RSVD1, RSVD2, RSVD3, 0x1070, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1980 PINGROUP(gen2_i2c_scl_pcc7, I2C2_CLK, RSVD1, RSVD2, RSVD3, 0x1098, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1981 PINGROUP(gen2_i2c_sda_pdd0, I2C2_DAT, RSVD1, RSVD2, RSVD3, 0x10a8, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1982 PINGROUP(gen8_i2c_scl_pdd1, I2C8_CLK, RSVD1, RSVD2, RSVD3, 0x1088, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1983 PINGROUP(gen8_i2c_sda_pdd2, I2C8_DAT, RSVD1, RSVD2, RSVD3, 0x1080, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1984 PINGROUP(touch_clk_pdd3, GP_PWM4, TOUCH_CLK, RSVD2, RSVD3, 0x1068, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1985 PINGROUP(dmic1_clk_pdd4, DMIC1_CLK, RSVD1, DMIC5_CLK, RSVD3, 0x11d0, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1986 PINGROUP(dmic1_dat_pdd5, DMIC1_DAT, RSVD1, DMIC5_DAT, RSVD3, 0x11d8, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1987 PINGROUP(soc_gpio19_pdd6, RSVD0, WDT_RESET_OUTB, RSVD2, RSVD3, 0x10f8, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1988 PINGROUP(soc_gpio49_pee2, RSVD0, RSVD1, RSVD2, RSVD3, 0x10c0, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1989 PINGROUP(soc_gpio50_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x10c8, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1990 PINGROUP(soc_gpio82_pee3, RSVD0, RSVD1, RSVD2, RSVD3, 0x10d0, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1991 PINGROUP(soc_gpio71_pff2, PPC_MODE_1, RSVD1, RSVD2, RSVD3, 0x10d8, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1992 PINGROUP(soc_gpio76_pff7, RSVD0, RSVD1, TSC_EDGE_OUT0, TSC_EDGE_OUT0A, 0x10e0, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1993 PINGROUP(soc_gpio74_pff5, PPC_READY, PPC_I2C_DAT, RSVD2, RSVD3, 0x10e8, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1994 PINGROUP(soc_gpio86_phh3, RSVD0, SPI5_CS1, TSC_EDGE_OUT3, TSC_EDGE_OUT0D, 0x1100, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1995 PINGROUP(soc_gpio72_pff3, PPC_MODE_2, RSVD1, RSVD2, RSVD3, 0x1108, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1996 PINGROUP(soc_gpio77_pgg0, RSVD0, RSVD1, TSC_EDGE_OUT1, TSC_EDGE_OUT0B, 0x1110, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1997 PINGROUP(soc_gpio80_pff6, RSVD0, PPC_RST_N, RSVD2, RSVD3, 0x1118, 1, Y, 5, 7, 6, 8, -1, 10, 12),
1998 PINGROUP(soc_gpio84_pgg1, RSVD0, RSVD1, TSC_EDGE_OUT2, TSC_EDGE_OUT0C, 0x1120, 1, Y, -1, 7, 6, 8, -1, 10, 12),
1999 PINGROUP(soc_gpio83_pee5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1128, 1, Y, -1, 7, 6, 8, -1, 10, 12),
2000 PINGROUP(soc_gpio73_pff4, PPC_CC, PPC_I2C_CLK, RSVD2, RSVD3, 0x1130, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2001 PINGROUP(soc_gpio70_pff1, PPC_MODE_0, RSVD1, RSVD2, RSVD3, 0x1138, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2002 PINGROUP(soc_gpio85_pgg6, RSVD0, SPI4_CS1, RSVD2, RSVD3, 0x1148, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2003 PINGROUP(soc_gpio69_pff0, PPC_INT_N, RSVD1, RSVD2, RSVD3, 0x1150, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2004 PINGROUP(uart5_tx_pgg7, UARTE_TXD, SPI5_SCK, RSVD2, RSVD3, 0x1168, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2005 PINGROUP(uart5_rx_phh0, UARTE_RXD, SPI5_MISO, RSVD2, RSVD3, 0x1170, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2006 PINGROUP(uart2_tx_pgg2, UARTB_TXD, SPI4_SCK, RSVD2, RSVD3, 0x1178, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2007 PINGROUP(uart2_rx_pgg3, UARTB_RXD, SPI4_MISO, RSVD2, RSVD3, 0x1180, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2008 PINGROUP(uart2_cts_pgg5, UARTB_CTS, SPI4_CS0, RSVD2, RSVD3, 0x1188, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2009 PINGROUP(uart2_rts_pgg4, UARTB_RTS, SPI4_MOSI, RSVD2, RSVD3, 0x1190, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2010 PINGROUP(uart5_cts_phh2, UARTE_CTS, SPI5_CS0, RSVD2, RSVD3, 0x1198, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2011 PINGROUP(uart5_rts_phh1, UARTE_RTS, SPI5_MOSI, RSVD2, RSVD3, 0x11a0, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2012 PINGROUP(pwm2_pdd7, GP_PWM2, LED_BLINK, RSVD2, RSVD3, 0x11b0, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2013 PINGROUP(pwm3_pee0, GP_PWM3, RSVD1, RSVD2, RSVD3, 0x11b8, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2014 PINGROUP(pwm7_pee1, GP_PWM7, RSVD1, RSVD2, RSVD3, 0x11a8, 1, Y, 5, 7, 6, 8, -1, 10, 12),
2015 };
2016
2017 static const struct tegra_pinctrl_soc_data tegra238_pinctrl_aon = {
2018 .pins = tegra238_aon_pins,
2019 .npins = ARRAY_SIZE(tegra238_aon_pins),
2020 .functions = tegra238_functions,
2021 .nfunctions = ARRAY_SIZE(tegra238_functions),
2022 .groups = tegra238_aon_groups,
2023 .ngroups = ARRAY_SIZE(tegra238_aon_groups),
2024 .hsm_in_mux = false,
2025 .schmitt_in_mux = true,
2026 .drvtype_in_mux = true,
2027 .sfsel_in_mux = true,
2028 };
2029
2030 static const struct tegra_pinctrl_soc_data tegra238_pinctrl = {
2031 .pins = tegra238_pins,
2032 .npins = ARRAY_SIZE(tegra238_pins),
2033 .functions = tegra238_functions,
2034 .nfunctions = ARRAY_SIZE(tegra238_functions),
2035 .groups = tegra238_groups,
2036 .ngroups = ARRAY_SIZE(tegra238_groups),
2037 .hsm_in_mux = false,
2038 .schmitt_in_mux = true,
2039 .drvtype_in_mux = true,
2040 .sfsel_in_mux = true,
2041 };
2042
tegra238_pinctrl_probe(struct platform_device * pdev)2043 static int tegra238_pinctrl_probe(struct platform_device *pdev)
2044 {
2045 const struct tegra_pinctrl_soc_data *soc = device_get_match_data(&pdev->dev);
2046
2047 return tegra_pinctrl_probe(pdev, soc);
2048 }
2049
2050 static const struct of_device_id tegra238_pinctrl_of_match[] = {
2051 { .compatible = "nvidia,tegra238-pinmux", .data = &tegra238_pinctrl },
2052 { .compatible = "nvidia,tegra238-pinmux-aon", .data = &tegra238_pinctrl_aon },
2053 { }
2054 };
2055 MODULE_DEVICE_TABLE(of, tegra238_pinctrl_of_match);
2056
2057 static struct platform_driver tegra238_pinctrl_driver = {
2058 .driver = {
2059 .name = "tegra238-pinctrl",
2060 .of_match_table = tegra238_pinctrl_of_match,
2061 },
2062 .probe = tegra238_pinctrl_probe,
2063 };
2064
tegra238_pinctrl_init(void)2065 static int __init tegra238_pinctrl_init(void)
2066 {
2067 return platform_driver_register(&tegra238_pinctrl_driver);
2068 }
2069 module_init(tegra238_pinctrl_init);
2070
tegra238_pinctrl_exit(void)2071 static void __exit tegra238_pinctrl_exit(void)
2072 {
2073 platform_driver_unregister(&tegra238_pinctrl_driver);
2074 }
2075 module_exit(tegra238_pinctrl_exit);
2076
2077 MODULE_LICENSE("GPL");
2078 MODULE_AUTHOR("NVIDIA Corporation");
2079 MODULE_DESCRIPTION("NVIDIA Tegra238 pinctrl driver");
2080