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Searched refs:dram_speed_mts (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c232 .dram_speed_mts = 8960.0,
243 .dram_speed_mts = 11104.0,
254 .dram_speed_mts = 14000.0,
265 .dram_speed_mts = 16000.0,
276 .dram_speed_mts = 16000.0,
288 .dram_speed_mts = 16000.0,
343 .dram_speed_mts = 8960.0,
354 .dram_speed_mts = 11104.0,
365 .dram_speed_mts = 14000.0,
376 .dram_speed_mts = 16000.0,
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/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c139 .dram_speed_mts = 18000.0,
246 …clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table… in dcn32_build_wm_range_table_fpu()
248 …clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table… in dcn32_build_wm_range_table_fpu()
250 …clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table… in dcn32_build_wm_range_table_fpu()
252 …clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table… in dcn32_build_wm_range_table_fpu()
370 memory_bw_kbytes_sec = entry->dram_speed_mts * in calculate_net_bw_in_kbytes_sec()
400 entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans * in get_optimal_ntuple()
406 entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans * in get_optimal_ntuple()
408 } else if (entry->dram_speed_mts > 0) { in get_optimal_ntuple()
409 float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans * in get_optimal_ntuple()
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/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_translation_helper.c373 p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock; in dml2_init_soc_states()
393 p->in_states->state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock; in dml2_init_soc_states()
409 p->in_states->state_array[0].dram_speed_mts = 100 * transactions_per_mem_clock; in dml2_init_soc_states()
429 p->in_states->state_array[1].dram_speed_mts = 1000 * transactions_per_mem_clock; in dml2_init_soc_states()
446 p->in_states->state_array[0].dram_speed_mts = 97 * transactions_per_mem_clock; //100 * in dml2_init_soc_states()
466 p->in_states->state_array[1].dram_speed_mts = 1125 * transactions_per_mem_clock; in dml2_init_soc_states()
542 p->in_states->state_array[i].dram_speed_mts = in dml2_init_soc_states()
578 if (p->in_states->state_array[i].dram_speed_mts > max_uclk_mhz) in dml2_init_soc_states()
579 max_uclk_mhz = (int)p->in_states->state_array[i].dram_speed_mts; in dml2_init_soc_states()
604 p->out_states->state_array[i].dram_speed_mts = p->in_states->state_array[i].dram_speed_mts; in dml2_init_soc_states()
[all …]
H A Ddml2_wrapper_fpu.c217 …>v20.dml_core_ctx.states.state_array[result].dram_speed_mts < s_global->dummy_pstate_table[i].dram… in calculate_lowest_supported_state_for_temp_read()
418 …clk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; in dml2_validate_and_build_resource()
476 …clk_mts = (unsigned int)dml2->v20.dml_core_ctx.states.state_array[lowest_state_idx].dram_speed_mts; in dml2_validate_and_build_resource()
H A Ddisplay_mode_util.c645 dml_print("DML: state_bbox: dram_speed_mts = %f\n", state->dram_speed_mts); in dml_print_soc_state_bounding_box()
H A Ddisplay_mode_core_structs.h288 dml_float_t dram_speed_mts; member
H A Ddisplay_mode_core.c6333 mode_lib->ms.state.dram_speed_mts); in dml_prefetch_check()
8043 mode_lib->ms.state.dram_speed_mts); in dml_core_mode_support()
8046 mode_lib->ms.state.dram_speed_mts); in dml_core_mode_support()
8069 …mode_lib->ms.state.dram_speed_mts * mode_lib->ms.soc.num_chans * mode_lib->ms.soc.dram_channel_wid… in dml_core_mode_support()
8148 …s->is_max_dram_pwr_state = (mode_lib->ms.max_state.dram_speed_mts == mode_lib->ms.state.dram_speed… in dml_core_mode_support()
8262 mode_lib->ms.DRAMSpeed = mode_lib->ms.state.dram_speed_mts; in dml_core_mode_support()
10102 mode_lib->ms.DRAMSpeed = (dml_float_t)state->dram_speed_mts; in fetch_socbb_params()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h31 uint32_t dram_speed_mts; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c150 .dram_speed_mts = 2000.0,
161 .dram_speed_mts = 3600.0,
172 .dram_speed_mts = 6800.0,
183 .dram_speed_mts = 14000.0,
195 .dram_speed_mts = 14000.0,
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c632 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * in dcn31_update_bw_bounding_box_fpu()
700 …dcn3_15_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->ent… in dcn315_update_bw_bounding_box_fpu()
772 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * in dcn316_update_bw_bounding_box_fpu()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c2140 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local
2233 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn30_update_bw_bounding_box()
2237 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
2246 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn30_update_bw_bounding_box()
2252 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn30_update_bw_bounding_box()
2257 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts); in dcn30_update_bw_bounding_box()
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h163 double dram_speed_mts; member
H A Ddisplay_mode_vba.c382 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()
403 mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()