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Searched refs:dram_channel_width_bytes (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c175 .dram_channel_width_bytes = 4,
271 .dram_channel_width_bytes = 4,
419 .dram_channel_width_bytes = 4,
683 if (bw_params->dram_channel_width_bytes > 0) in dcn315_update_bw_bounding_box_fpu()
684 dcn3_15_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes; in dcn315_update_bw_bounding_box_fpu()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h57 uint32_t dram_channel_width_bytes; member
/linux/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/
H A Ddcn42_soc_and_ip_translator.c148 dml_clk_table->dram_config.channel_width_bytes = dc_bw_params->dram_channel_width_bytes; in dcn42_update_soc_bb_with_values_from_clk_mgr()
/linux/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h193 unsigned int dram_channel_width_bytes; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c171 .dram_channel_width_bytes = 2,
375 dcn3_2_soc.dram_channel_width_bytes * in calculate_net_bw_in_kbytes_sec()
404 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100))); in get_optimal_ntuple()
410 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100))); in get_optimal_ntuple()
413 dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100)); in get_optimal_ntuple()
2614 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100); in dcn32_get_optimal_dcfclk_fclk_for_uclk()
2616 dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100); in dcn32_get_optimal_dcfclk_fclk_for_uclk()
3107 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes) { in dcn32_update_bw_bounding_box_fpu()
3108 unsigned int dram_channel_width_bytes = (unsigned int)dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn32_update_bw_bounding_box_fpu()
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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h219 double dram_channel_width_bytes; member
H A Ddisplay_mode_vba.c367 mode_lib->vba.DRAMChannelWidth = soc->dram_channel_width_bytes; // new! in fetch_socbb_params()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddml2_translation_helper.c270 out->dram_channel_width_bytes = 2; in dml2_init_socbb_params()
327 out->dram_channel_width_bytes = dml2->config.bbox_overrides.dram_chanel_width_bytes; in dml2_init_socbb_params()
691 out->dram_channel_width_bytes = (dml_uint_t)in_soc_params->dram_channel_width_bytes; in dml2_translate_socbb_params()
H A Ddisplay_mode_util.c691 dml_print("DML: soc_bbox: dram_channel_width_bytes = %d\n", soc->dram_channel_width_bytes); in dml_print_soc_bounding_box()
H A Ddisplay_mode_core_structs.h349 dml_uint_t dram_channel_width_bytes; member
H A Ddisplay_mode_core.c5887 DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes * in DSCDelayRequirement()
5913 dml_float_t IdealDRAMBandwidth = DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes; in DSCDelayRequirement()
5954 dml_float_t IdealDRAMBandwidth = DRAMSpeed * soc->num_chans * soc->dram_channel_width_bytes; in CalculateVActiveBandwithSupport()
8161 mode_lib->ms.state.dram_speed_mts * mode_lib->ms.soc.num_chans * mode_lib->ms.soc.dram_channel_width_bytes * in dml_core_mode_support()
8902 dml_print("DML::%s: mode_lib->ms.soc.dram_channel_width_bytes = %u\n", __func__, mode_lib->ms.soc.dram_channel_width_bytes); in dml_core_mode_programming()
/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dbios_parser2.c2526 info->dram_channel_width_bytes = (1 << info_v23->vram_module[0].channel_width) / 8;
2545 info->dram_channel_width_bytes = (1 << info_v24->vram_module[0].channel_width) / 8; in get_integrated_info_v11()
2564 info->dram_channel_width_bytes = (1 << info_v25->vram_module[0].channel_width) / 8; in get_integrated_info_v11()
2583 info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8; in get_integrated_info_v11()
2602 info->dram_channel_width_bytes = (1 << info_v40->channel_width) / 8; in get_integrated_info_v11()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c309 .dram_channel_width_bytes = 2,
420 .dram_channel_width_bytes = 2,
531 .dram_channel_width_bytes = 16,
745 .dram_channel_width_bytes = 4,
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c216 .dram_channel_width_bytes = 2,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/
H A Ddcn42_clk_mgr.c1082 dcn42_bw_params.dram_channel_width_bytes = ctx->dc_bios->integrated_info->memory_type == 0x22 ? 8 : 4; in dcn42_clk_mgr_construct()