1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 3 #ifndef _UAPI_ASM_X86_AMD_HSMP_H_ 4 #define _UAPI_ASM_X86_AMD_HSMP_H_ 5 6 #include <linux/types.h> 7 8 #pragma pack(4) 9 10 #define HSMP_MAX_MSG_LEN 8 11 12 /* 13 * HSMP Messages supported 14 */ 15 enum hsmp_message_ids { 16 HSMP_TEST = 1, /* 01h Increments input value by 1 */ 17 HSMP_GET_SMU_VER, /* 02h SMU FW version */ 18 HSMP_GET_PROTO_VER, /* 03h HSMP interface version */ 19 HSMP_GET_SOCKET_POWER, /* 04h average package power consumption */ 20 HSMP_SET_SOCKET_POWER_LIMIT, /* 05h Set the socket power limit */ 21 HSMP_GET_SOCKET_POWER_LIMIT, /* 06h Get current socket power limit */ 22 HSMP_GET_SOCKET_POWER_LIMIT_MAX,/* 07h Get maximum socket power value */ 23 HSMP_SET_BOOST_LIMIT, /* 08h Set a core maximum frequency limit */ 24 HSMP_SET_BOOST_LIMIT_SOCKET, /* 09h Set socket maximum frequency level */ 25 HSMP_GET_BOOST_LIMIT, /* 0Ah Get current frequency limit */ 26 HSMP_GET_PROC_HOT, /* 0Bh Get PROCHOT status */ 27 HSMP_SET_XGMI_LINK_WIDTH, /* 0Ch Set max and min width of xGMI Link */ 28 HSMP_SET_DF_PSTATE, /* 0Dh Alter APEnable/Disable messages behavior */ 29 HSMP_SET_AUTO_DF_PSTATE, /* 0Eh Enable DF P-State Performance Boost algorithm */ 30 HSMP_GET_FCLK_MCLK, /* 0Fh Get FCLK and MEMCLK for current socket */ 31 HSMP_GET_CCLK_THROTTLE_LIMIT, /* 10h Get CCLK frequency limit in socket */ 32 HSMP_GET_C0_PERCENT, /* 11h Get average C0 residency in socket */ 33 HSMP_SET_NBIO_DPM_LEVEL, /* 12h Set max/min LCLK DPM Level for a given NBIO */ 34 HSMP_GET_NBIO_DPM_LEVEL, /* 13h Get LCLK DPM level min and max for a given NBIO */ 35 HSMP_GET_DDR_BANDWIDTH, /* 14h Get theoretical maximum and current DDR Bandwidth */ 36 HSMP_GET_TEMP_MONITOR, /* 15h Get socket temperature */ 37 HSMP_GET_DIMM_TEMP_RANGE, /* 16h Get per-DIMM temperature range and refresh rate */ 38 HSMP_GET_DIMM_POWER, /* 17h Get per-DIMM power consumption */ 39 HSMP_GET_DIMM_THERMAL, /* 18h Get per-DIMM thermal sensors */ 40 HSMP_GET_SOCKET_FREQ_LIMIT, /* 19h Get current active frequency per socket */ 41 HSMP_GET_CCLK_CORE_LIMIT, /* 1Ah Get CCLK frequency limit per core */ 42 HSMP_GET_RAILS_SVI, /* 1Bh Get SVI-based Telemetry for all rails */ 43 HSMP_GET_SOCKET_FMAX_FMIN, /* 1Ch Get Fmax and Fmin per socket */ 44 HSMP_GET_IOLINK_BANDWITH, /* 1Dh Get current bandwidth on IO Link */ 45 HSMP_GET_XGMI_BANDWITH, /* 1Eh Get current bandwidth on xGMI Link */ 46 HSMP_SET_GMI3_WIDTH, /* 1Fh Set max and min GMI3 Link width */ 47 HSMP_SET_PCI_RATE, /* 20h Control link rate on PCIe devices */ 48 HSMP_SET_POWER_MODE, /* 21h Select power efficiency profile policy */ 49 HSMP_SET_PSTATE_MAX_MIN, /* 22h Set the max and min DF P-State */ 50 HSMP_GET_METRIC_TABLE_VER, /* 23h Get metrics table version */ 51 HSMP_GET_METRIC_TABLE, /* 24h Get metrics table */ 52 HSMP_GET_METRIC_TABLE_DRAM_ADDR,/* 25h Get metrics table dram address */ 53 HSMP_SET_XGMI_PSTATE_RANGE, /* 26h Set xGMI P-state range */ 54 HSMP_CPU_RAIL_ISO_FREQ_POLICY, /* 27h Get/Set Cpu Iso frequency policy */ 55 HSMP_DFC_ENABLE_CTRL, /* 28h Enable/Disable DF C-state */ 56 HSMP_PC6_ENABLE, /* 29h Get/Set PC6 enable/disable status */ 57 HSMP_CC6_ENABLE, /* 2Ah Get/Set CC6 enable/disable status */ 58 HSMP_GET_RAPL_UNITS = 0x30, /* 30h Get scaling factor for energy */ 59 HSMP_GET_RAPL_CORE_COUNTER, /* 31h Get core energy counter value */ 60 HSMP_GET_RAPL_PACKAGE_COUNTER, /* 32h Get package energy counter value */ 61 HSMP_DIMM_SB_RD, /* 33h Get DIMM sideband data */ 62 HSMP_READ_CCD_POWER, /* 34h Get average CCD power */ 63 HSMP_READ_TDELTA, /* 35h Get thermal behaviour */ 64 HSMP_GET_SVI3_VR_CTRL_TEMP, /* 36h Get SVI3 VR controller rail temp */ 65 HSMP_GET_ENABLED_HSMP_CMDS, /* 37h Get supported HSMP commands */ 66 HSMP_SET_GET_FLOOR_LIMIT, /* 38h Get/Set core floor frequency limit */ 67 HSMP_DIMM_SB_WR, /* 39h Set DIMM sideband data */ 68 HSMP_SDPS_LIMIT, /* 3Ah Get/Set SDPS limit */ 69 HSMP_PQOS_TRAFFIC_PRIORITY, /* 3Bh Get/Set traffic priority */ 70 HSMP_PQOS_FLOATING_BW, /* 3Ch Get/Set max floating bandwidth */ 71 HSMP_MSG_ID_MAX, 72 }; 73 74 struct hsmp_message { 75 __u32 msg_id; /* Message ID */ 76 __u16 num_args; /* Number of input argument words in message */ 77 __u16 response_sz; /* Number of expected output/response words */ 78 __u32 args[HSMP_MAX_MSG_LEN]; /* argument/response buffer */ 79 __u16 sock_ind; /* socket number */ 80 }; 81 82 enum hsmp_msg_type { 83 HSMP_RSVD = -1, 84 HSMP_SET = 0, 85 HSMP_GET = 1, 86 HSMP_SET_GET = 2, 87 }; 88 89 enum hsmp_proto_versions { 90 HSMP_PROTO_VER2 = 2, 91 HSMP_PROTO_VER3, 92 HSMP_PROTO_VER4, 93 HSMP_PROTO_VER5, 94 HSMP_PROTO_VER6, 95 HSMP_PROTO_VER7 96 }; 97 98 struct hsmp_msg_desc { 99 int num_args; 100 int response_sz; 101 enum hsmp_msg_type type; 102 }; 103 104 /* 105 * User may use these comments as reference, please find the 106 * supported list of messages and message definition in the 107 * HSMP chapter of respective family/model PPR. 108 * 109 * Not supported messages would return -ENOMSG. 110 */ 111 static const struct hsmp_msg_desc hsmp_msg_desc_table[] 112 __attribute__((unused)) = { 113 /* RESERVED */ 114 {0, 0, HSMP_RSVD}, 115 116 /* 117 * HSMP_TEST, num_args = 1, response_sz = 1 118 * input: args[0] = xx 119 * output: args[0] = xx + 1 120 */ 121 {1, 1, HSMP_GET}, 122 123 /* 124 * HSMP_GET_SMU_VER, num_args = 0, response_sz = 1 125 * output: args[0] = smu fw ver 126 */ 127 {0, 1, HSMP_GET}, 128 129 /* 130 * HSMP_GET_PROTO_VER, num_args = 0, response_sz = 1 131 * output: args[0] = proto version 132 */ 133 {0, 1, HSMP_GET}, 134 135 /* 136 * HSMP_GET_SOCKET_POWER, num_args = 0, response_sz = 1 137 * output: args[0] = socket power in mWatts 138 */ 139 {0, 1, HSMP_GET}, 140 141 /* 142 * HSMP_SET_SOCKET_POWER_LIMIT, num_args = 1, response_sz = 0 143 * input: args[0] = power limit value in mWatts 144 */ 145 {1, 0, HSMP_SET}, 146 147 /* 148 * HSMP_GET_SOCKET_POWER_LIMIT, num_args = 0, response_sz = 1 149 * output: args[0] = socket power limit value in mWatts 150 */ 151 {0, 1, HSMP_GET}, 152 153 /* 154 * HSMP_GET_SOCKET_POWER_LIMIT_MAX, num_args = 0, response_sz = 1 155 * output: args[0] = maximuam socket power limit in mWatts 156 */ 157 {0, 1, HSMP_GET}, 158 159 /* 160 * HSMP_SET_BOOST_LIMIT, num_args = 1, response_sz = 0 161 * input: args[0] = apic id[31:16] + boost limit value in MHz[15:0] 162 */ 163 {1, 0, HSMP_SET}, 164 165 /* 166 * HSMP_SET_BOOST_LIMIT_SOCKET, num_args = 1, response_sz = 0 167 * input: args[0] = boost limit value in MHz 168 */ 169 {1, 0, HSMP_SET}, 170 171 /* 172 * HSMP_GET_BOOST_LIMIT, num_args = 1, response_sz = 1 173 * input: args[0] = apic id 174 * output: args[0] = boost limit value in MHz 175 */ 176 {1, 1, HSMP_GET}, 177 178 /* 179 * HSMP_GET_PROC_HOT, num_args = 0, response_sz = 1 180 * output: args[0] = proc hot status 181 */ 182 {0, 1, HSMP_GET}, 183 184 /* 185 * HSMP_SET_XGMI_LINK_WIDTH, num_args = 1, response_sz = 0/1 186 * input: args[0] = set/get XGMI Link width[31] (0 = set, 1 = get) + 187 * min link width[15:8] + max link width[7:0] 188 * Link width encoding: 0 = x4, 1 = x8, 2 = x16. 189 * On SET, max must be >= min. On GET, [15:0] are reserved. 190 * output: args[0] = reserved[31:16] + min link width[15:8] + 191 * max link width[7:0] 192 */ 193 {1, 1, HSMP_SET_GET}, 194 195 /* 196 * HSMP_SET_DF_PSTATE (APBDisable), num_args = 1, response_sz = 0/1 197 * input: args[0] = set APB_DISABLE / get APB state[31] 198 * (0 = set & lock DF P-state, 1 = get) + 199 * reserved[30:8] + 200 * DF P-state[7:0] (0..2; reserved on GET) 201 * output: args[0] = reserved[31:9] + 202 * APB state[8] (1 = disabled, 0 = enabled) + 203 * locked DF P-state[7:0] if [8] = 1, else reserved 204 */ 205 {1, 1, HSMP_SET_GET}, 206 207 /* HSMP_SET_AUTO_DF_PSTATE, num_args = 0, response_sz = 0 */ 208 {0, 0, HSMP_SET}, 209 210 /* 211 * HSMP_GET_FCLK_MCLK, num_args = 0, response_sz = 2 212 * output: args[0] = fclk in MHz, args[1] = mclk in MHz 213 */ 214 {0, 2, HSMP_GET}, 215 216 /* 217 * HSMP_GET_CCLK_THROTTLE_LIMIT, num_args = 0, response_sz = 1 218 * output: args[0] = core clock in MHz 219 */ 220 {0, 1, HSMP_GET}, 221 222 /* 223 * HSMP_GET_C0_PERCENT, num_args = 0, response_sz = 1 224 * output: args[0] = average c0 residency 225 */ 226 {0, 1, HSMP_GET}, 227 228 /* 229 * HSMP_SET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 0 230 * input: args[0] = nbioid[23:16] + max dpm level[15:8] + min dpm level[7:0] 231 */ 232 {1, 0, HSMP_SET}, 233 234 /* 235 * HSMP_GET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 1 236 * input: args[0] = nbioid[23:16] 237 * output: args[0] = max dpm level[15:8] + min dpm level[7:0] 238 */ 239 {1, 1, HSMP_GET}, 240 241 /* 242 * HSMP_GET_DDR_BANDWIDTH, num_args = 0, response_sz = 1 243 * output: args[0] = max bw in Gbps[31:20] + utilised bw in Gbps[19:8] + 244 * bw in percentage[7:0] 245 */ 246 {0, 1, HSMP_GET}, 247 248 /* 249 * HSMP_GET_TEMP_MONITOR, num_args = 0, response_sz = 1 250 * output: args[0] = temperature in degree celsius. [15:8] integer part + 251 * [7:5] fractional part 252 */ 253 {0, 1, HSMP_GET}, 254 255 /* 256 * HSMP_GET_DIMM_TEMP_RANGE, num_args = 1, response_sz = 1 257 * input: args[0] = DIMM address[7:0] 258 * output: args[0] = refresh rate[3] + temperature range[2:0] 259 */ 260 {1, 1, HSMP_GET}, 261 262 /* 263 * HSMP_GET_DIMM_POWER, num_args = 1, response_sz = 1 264 * input: args[0] = DIMM address[7:0] 265 * output: args[0] = DIMM power in mW[31:17] + update rate in ms[16:8] + 266 * DIMM address[7:0] 267 */ 268 {1, 1, HSMP_GET}, 269 270 /* 271 * HSMP_GET_DIMM_THERMAL, num_args = 1, response_sz = 1 272 * input: args[0] = DIMM address[7:0] 273 * output: args[0] = temperature in degree celsius[31:21] + update rate in ms[16:8] + 274 * DIMM address[7:0] 275 */ 276 {1, 1, HSMP_GET}, 277 278 /* 279 * HSMP_GET_SOCKET_FREQ_LIMIT, num_args = 0, response_sz = 1 280 * output: args[0] = frequency in MHz[31:16] + frequency source[15:0] 281 */ 282 {0, 1, HSMP_GET}, 283 284 /* 285 * HSMP_GET_CCLK_CORE_LIMIT, num_args = 1, response_sz = 1 286 * input: args[0] = apic id [31:0] 287 * output: args[0] = frequency in MHz[31:0] 288 */ 289 {1, 1, HSMP_GET}, 290 291 /* 292 * HSMP_GET_RAILS_SVI, num_args = 0, response_sz = 1 293 * output: args[0] = power in mW[31:0] 294 */ 295 {0, 1, HSMP_GET}, 296 297 /* 298 * HSMP_GET_SOCKET_FMAX_FMIN, num_args = 0, response_sz = 1 299 * output: args[0] = fmax in MHz[31:16] + fmin in MHz[15:0] 300 */ 301 {0, 1, HSMP_GET}, 302 303 /* 304 * HSMP_GET_IOLINK_BANDWITH, num_args = 1, response_sz = 1 305 * input: args[0] = link id[15:8] + bw type[2:0] 306 * output: args[0] = io bandwidth in Mbps[31:0] 307 */ 308 {1, 1, HSMP_GET}, 309 310 /* 311 * HSMP_GET_XGMI_BANDWITH, num_args = 1, response_sz = 1 312 * input: args[0] = link id[15:8] + bw type[2:0] 313 * output: args[0] = xgmi bandwidth in Mbps[31:0] 314 */ 315 {1, 1, HSMP_GET}, 316 317 /* 318 * HSMP_SET_GMI3_WIDTH, num_args = 1, response_sz = 0 319 * input: args[0] = min link width[15:8] + max link width[7:0] 320 */ 321 {1, 0, HSMP_SET}, 322 323 /* 324 * HSMP_SET_PCI_RATE, num_args = 1, response_sz = 1 325 * input: args[0] = link rate control value 326 * output: args[0] = previous link rate control value 327 */ 328 {1, 1, HSMP_SET}, 329 330 /* 331 * HSMP_SET_POWER_MODE (PwrEfficiencyModeSelection), 332 * num_args = 1, response_sz = 1 333 * input: args[0] = set/get policy[31] (0 = set, 1 = get) + 334 * high util point[30:24] + 335 * low util point[23:17] + 336 * PPT limit[16:5] + 337 * reserved[4:3] + mode selection[2:0] 338 * [30:5] are valid only when [2:0] is a balanced core mode 339 * (4 or 5). [2:0] is reserved when getting (bit[31] = 1). 340 * output: args[0] same layout, [31] reserved, [2:0] = arbitrated 341 * current efficiency mode. 342 */ 343 {1, 1, HSMP_SET_GET}, 344 345 /* 346 * HSMP_SET_PSTATE_MAX_MIN (DfPstateRange), num_args = 1, response_sz = 0/1 347 * input: args[0] = set/get DF P-state range[31] (0 = set, 1 = get) + 348 * reserved[30:16] + 349 * min DF P-state[15:8] + max DF P-state[7:0] 350 * DF P-state encoding: 0 = DFP0 (high performance), 351 * 1 = DFP1, 2 = DFP2 (low performance). 352 * [15:0] are reserved when getting (args[0] bit[31] = 1). 353 * output: args[0] = reserved[31:16] + min DF P-state[15:8] + 354 * max DF P-state[7:0] 355 */ 356 {1, 1, HSMP_SET_GET}, 357 358 /* 359 * HSMP_GET_METRIC_TABLE_VER, num_args = 0, response_sz = 1 360 * output: args[0] = metrics table version 361 */ 362 {0, 1, HSMP_GET}, 363 364 /* 365 * HSMP_GET_METRIC_TABLE, num_args = 0, response_sz = 0 366 */ 367 {0, 0, HSMP_GET}, 368 369 /* 370 * HSMP_GET_METRIC_TABLE_DRAM_ADDR, num_args = 0, response_sz = 3 371 * output: args[0] = lower 32 bits of the address 372 * output: args[1] = upper 32 bits of the address 373 * output: args[2] = DRAM region size in bytes 374 */ 375 {0, 3, HSMP_GET}, 376 377 /* 378 * HSMP_SET_XGMI_PSTATE_RANGE, num_args = 1, response_sz = 0 379 * input: args[0] = min xGMI p-state[15:8] + max xGMI p-state[7:0] 380 */ 381 {1, 0, HSMP_SET}, 382 383 /* 384 * HSMP_CPU_RAIL_ISO_FREQ_POLICY, num_args = 1, response_sz = 1 385 * input: args[0] = set/get policy[31] + 386 * disable/enable independent control[0] 387 * output: args[0] = current policy[0] 388 */ 389 {1, 1, HSMP_SET_GET}, 390 391 /* 392 * HSMP_DFC_ENABLE_CTRL, num_args = 1, response_sz = 1 393 * input: args[0] = set/get policy[31] + enable/disable DFC[0] 394 * output: args[0] = current policy[0] 395 */ 396 {1, 1, HSMP_SET_GET}, 397 398 /* 399 * HSMP_PC6_ENABLE (Pc6Enable), num_args = 1, response_sz = 0/1 400 * input: args[0] = set/get PC6 control[31] (0 = set, 1 = get) + 401 * reserved[30:1] + 402 * enable PC6[0] (0 = disable, 1 = enable; 403 * reserved on GET) 404 * output: args[0] = reserved[31:1] + current PC6 control[0] 405 * (last value configured via HSMP or APML) 406 */ 407 {1, 1, HSMP_SET_GET}, 408 409 /* 410 * HSMP_CC6_ENABLE (CC6Enable), num_args = 1, response_sz = 0/1 411 * Configures CC6 enable for all cores; changing the setting does 412 * not by itself transition cores in or out of CC6. 413 * input: args[0] = set/get CC6 control[31] (0 = set, 1 = get) + 414 * reserved[30:1] + 415 * enable CC6[0] (0 = disable, 1 = enable; 416 * reserved on GET) 417 * output: args[0] = reserved[31:1] + current CC6 control[0] 418 * (last value configured via HSMP or APML) 419 */ 420 {1, 1, HSMP_SET_GET}, 421 422 /* RESERVED(0x2B-0x2F) */ 423 {0, 0, HSMP_RSVD}, 424 {0, 0, HSMP_RSVD}, 425 {0, 0, HSMP_RSVD}, 426 {0, 0, HSMP_RSVD}, 427 {0, 0, HSMP_RSVD}, 428 429 /* 430 * HSMP_GET_RAPL_UNITS, response_sz = 1 431 * output: args[0] = tu value[19:16] + esu value[12:8] 432 */ 433 {0, 1, HSMP_GET}, 434 435 /* 436 * HSMP_GET_RAPL_CORE_COUNTER, num_args = 1, response_sz = 1 437 * input: args[0] = apic id[15:0] 438 * output: args[0] = lower 32 bits of energy 439 * output: args[1] = upper 32 bits of energy 440 */ 441 {1, 2, HSMP_GET}, 442 443 /* 444 * HSMP_GET_RAPL_PACKAGE_COUNTER, num_args = 0, response_sz = 1 445 * output: args[0] = lower 32 bits of energy 446 * output: args[1] = upper 32 bits of energy 447 */ 448 {0, 2, HSMP_GET}, 449 450 /* 451 * HSMP_DIMM_SB_RD, num_args = 1, response_sz = 1 452 * input: args[0] = reg space[23] + reg offset[22:12] + 453 * device LID[11:8] + DIMM address[7:0] 454 * output: args[0] = read data byte[3:0] 455 */ 456 {1, 1, HSMP_GET}, 457 458 /* 459 * HSMP_READ_CCD_POWER, num_args = 1, response_sz = 1 460 * input: args[0] = apic id of core[15:0] 461 * output: args[0] = CCD power(mWatts)[31:0] 462 */ 463 {1, 1, HSMP_GET}, 464 465 /* 466 * HSMP_READ_TDELTA, num_args = 0, response_sz = 1 467 * output: args[0] = thermal behaviour[31:0] 468 */ 469 {0, 1, HSMP_GET}, 470 471 /* 472 * HSMP_GET_SVI3_VR_CTRL_TEMP, num_args = 1, response_sz = 1 473 * input: args[0] = SVI3 rail index[3:1] + read temperature[0] 474 * output: args[0] = SVI3 rail index[30:28] + 475 * rail temperature in degree C[27:0] 476 */ 477 {1, 1, HSMP_GET}, 478 479 /* 480 * HSMP_GET_ENABLED_HSMP_CMDS, num_args = 1, response_sz = 3 481 * input: args[0] = HSMP command mask[0] 482 * output: status of HSMP command = args[0], args[1], args[2] 483 */ 484 {1, 3, HSMP_GET}, 485 486 /* 487 * HSMP_SET_GET_FLOOR_LIMIT, num_args = 1, response_sz = 1 488 * input: args[0] = op[31:30] + reserved[29:28] + 489 * apic id[27:16] + floor frequency MHz[15:0] 490 * op encoding: 00 = set per-core floor, 491 * 01 = set all-cores floor (apic id reserved), 492 * 10 = get per-core floor, 493 * 11 = get per-core effective floor. 494 * Floor frequency field is reserved on GET (bit[31] = 1). 495 * output: args[0] = floor frequency MHz[15:0] 496 * (effective for op 11, configured for op 10; 497 * reserved on SET) 498 */ 499 {1, 1, HSMP_SET_GET}, 500 501 /* 502 * HSMP_DIMM_SB_WR, num_args = 1, response_sz = 0 503 * input: args[0] = write data[31:24] + reg space[23] + 504 * reg offset[22:12] + device LID[11:8] + 505 * DIMM address[7:0] 506 */ 507 {1, 0, HSMP_SET}, 508 509 /* 510 * HSMP_SDPS_LIMIT, num_args = 1, response_sz = 1 511 * input: args[0] = set/get SDPS limit[31] (0 = set, 1 = get) + 512 * SDPS limit[30:0] 513 * output: args[0] = SDPS limit[30:0] 514 */ 515 {1, 1, HSMP_SET_GET}, 516 517 /* 518 * HSMP_PQOS_TRAFFIC_PRIORITY, num_args = 1, response_sz = 1 519 * input: args[0] = op[31:30] + priority sel[27:26] + 520 * priority val[21:20] + input[19:0] 521 * output: args[0] = supported priorities or priority val[1:0] 522 */ 523 {1, 1, HSMP_SET_GET}, 524 525 /* 526 * HSMP_PQOS_FLOATING_BW, num_args = 1, response_sz = 2 527 * input: args[0] = op[31] + sub-op[30:29] + params[28:0] 528 * output: args[0] = discovery bits or floating/global memory BW (Gbps) 529 * output: args[1] = reserved or config (drop adj, sampling delay, 530 * hysteresis) 531 */ 532 {1, 2, HSMP_SET_GET}, 533 }; 534 535 /* Metrics table (supported only with proto version 6) */ 536 struct hsmp_metric_table { 537 __u32 accumulation_counter; 538 539 /* TEMPERATURE */ 540 __u32 max_socket_temperature; 541 __u32 max_vr_temperature; 542 __u32 max_hbm_temperature; 543 __u64 max_socket_temperature_acc; 544 __u64 max_vr_temperature_acc; 545 __u64 max_hbm_temperature_acc; 546 547 /* POWER */ 548 __u32 socket_power_limit; 549 __u32 max_socket_power_limit; 550 __u32 socket_power; 551 552 /* ENERGY */ 553 __u64 timestamp; 554 __u64 socket_energy_acc; 555 __u64 ccd_energy_acc; 556 __u64 xcd_energy_acc; 557 __u64 aid_energy_acc; 558 __u64 hbm_energy_acc; 559 560 /* FREQUENCY */ 561 __u32 cclk_frequency_limit; 562 __u32 gfxclk_frequency_limit; 563 __u32 fclk_frequency; 564 __u32 uclk_frequency; 565 __u32 socclk_frequency[4]; 566 __u32 vclk_frequency[4]; 567 __u32 dclk_frequency[4]; 568 __u32 lclk_frequency[4]; 569 __u64 gfxclk_frequency_acc[8]; 570 __u64 cclk_frequency_acc[96]; 571 572 /* FREQUENCY RANGE */ 573 __u32 max_cclk_frequency; 574 __u32 min_cclk_frequency; 575 __u32 max_gfxclk_frequency; 576 __u32 min_gfxclk_frequency; 577 __u32 fclk_frequency_table[4]; 578 __u32 uclk_frequency_table[4]; 579 __u32 socclk_frequency_table[4]; 580 __u32 vclk_frequency_table[4]; 581 __u32 dclk_frequency_table[4]; 582 __u32 lclk_frequency_table[4]; 583 __u32 max_lclk_dpm_range; 584 __u32 min_lclk_dpm_range; 585 586 /* XGMI */ 587 __u32 xgmi_width; 588 __u32 xgmi_bitrate; 589 __u64 xgmi_read_bandwidth_acc[8]; 590 __u64 xgmi_write_bandwidth_acc[8]; 591 592 /* ACTIVITY */ 593 __u32 socket_c0_residency; 594 __u32 socket_gfx_busy; 595 __u32 dram_bandwidth_utilization; 596 __u64 socket_c0_residency_acc; 597 __u64 socket_gfx_busy_acc; 598 __u64 dram_bandwidth_acc; 599 __u32 max_dram_bandwidth; 600 __u64 dram_bandwidth_utilization_acc; 601 __u64 pcie_bandwidth_acc[4]; 602 603 /* THROTTLERS */ 604 __u32 prochot_residency_acc; 605 __u32 ppt_residency_acc; 606 __u32 socket_thm_residency_acc; 607 __u32 vr_thm_residency_acc; 608 __u32 hbm_thm_residency_acc; 609 __u32 spare; 610 611 /* New items at the end to maintain driver compatibility */ 612 __u32 gfxclk_frequency[8]; 613 }; 614 615 /** 616 * struct hsmp_telemetry_data - Request descriptor for HSMP telemetry IOCTL 617 * @buf: Input. Userspace pointer (encoded as __u64 to keep the layout 618 * stable between 32-bit and 64-bit callers) to the destination 619 * buffer that receives the metric table. 620 * @size: Input. Size in bytes of the buffer pointed to by @buf, and the 621 * number of bytes copied out on success. Must be non-zero and no 622 * larger than the metric table size firmware reports for this 623 * socket; a larger value is rejected with -EINVAL rather than 624 * short-written. A smaller value returns the leading @size bytes 625 * of the snapshot. The kernel does not write this field back. 626 * @sock_ind: Input. Socket index from which the metric table is read. 627 * @reserved: Reserved for future use. Callers should set this to zero; 628 * future kernels may begin interpreting the field, so passing 629 * a non-zero value today is not forwards compatible. 630 * 631 * Placing @buf first lets all fields fall on their natural alignment under 632 * the surrounding #pragma pack(4), so the struct is a tight 16 bytes with 633 * the same wire layout on 32-bit and 64-bit userspace. 634 * 635 * The metric table layout depends on the HSMP protocol version reported by 636 * firmware, which userspace can read from the protocol_version sysfs 637 * attribute. Protocol version 6 uses struct hsmp_metric_table, so callers on 638 * that version pass sizeof(struct hsmp_metric_table). Later version metrics 639 * table layout is documented in the Public PPR. 640 */ 641 struct hsmp_telemetry_data { 642 __u64 buf; 643 __u32 size; 644 __u16 sock_ind; 645 __u16 reserved; 646 }; 647 648 /* Reset to default packing */ 649 #pragma pack() 650 651 /* Define unique ioctl command for hsmp msgs using generic _IOWR */ 652 #define HSMP_BASE_IOCTL_NR 0xF8 653 #define HSMP_IOCTL_CMD _IOWR(HSMP_BASE_IOCTL_NR, 0, struct hsmp_message) 654 655 /* 656 * Fetch the firmware metric (telemetry) table for a given socket via the 657 * HSMP character device. This avoids the PAGE_SIZE limitation of the 658 * sysfs binary attribute path for tables larger than one page (such as the 659 * ~13 KB table used by HSMP protocol version 7). 660 * 661 * The direction is _IOW because the kernel only reads the request struct; 662 * the table itself is written to the buffer that @buf points at. 663 */ 664 #define HSMP_IOCTL_GET_TELEMETRY_DATA \ 665 _IOW(HSMP_BASE_IOCTL_NR, 1, struct hsmp_telemetry_data) 666 667 #endif /*_ASM_X86_AMD_HSMP_H_*/ 668