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Searched refs:dpp (Results 1 – 25 of 32) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_cm.c43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
92 struct dcn10_dpp *dpp, in program_gamut_remap() argument
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
129 dpp->base.ctx, in program_gamut_remap()
139 dpp->base.ctx, in program_gamut_remap()
[all …]
H A Ddcn10_dpp_dscl.c44 dpp->tf_regs->reg
47 dpp->base.ctx
51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
124 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode()
158 struct dpp *dpp_base, in dpp1_power_on_dscl()
161 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl() local
163 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) { in dpp1_power_on_dscl()
168 if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) { in dpp1_power_on_dscl()
169 dpp->base.ctx->dc->optimized_required = true; in dpp1_power_on_dscl()
170 dpp->base.deferred_reg_writes.bits.disable_dscl = true; in dpp1_power_on_dscl()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp_cm.c34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 struct dpp *dpp_base) in dpp3_enable_cm_block()
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block() local
57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current()
62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current() local
78 struct dpp *dpp_base, in dpp3_program_gammcor_lut()
84 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_gammcor_lut() local
127 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 struct dpp *dpp_base) in dpp2_enable_cm_block()
53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block() local
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse()
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse() local
86 struct dpp *dpp_base, in dpp2_program_degamma_lut()
93 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_program_degamma_lut() local
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl()
[all …]
H A Ddcn20_dpp.c42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state()
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state() local
78 struct dpp *dpp_base, in dpp2_power_on_obuf()
81 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf() local
93 struct dpp *dpp_base, in dpp2_dummy_program_input_lut()
98 struct dpp *dpp_base, in dpp2_cnv_setup()
105 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c35 dpp->tf_regs->reg
38 dpp->base.ctx
42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
45 struct dpp *dpp_base, in dpp201_cnv_setup()
52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup() local
191 struct dpp *dpp, in dpp201_get_optimal_number_of_taps() argument
198 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && in dpp201_get_optimal_number_of_taps()
203 dpp->ctx->dc->debug.max_downscale_src_width != 0 && in dpp201_get_optimal_number_of_taps()
204 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp201_get_optimal_number_of_taps()
251 if (!dpp->ctx->dc->debug.always_scale) { in dpp201_get_optimal_number_of_taps()
[all …]
H A Ddcn201_dpp.h30 #define TO_DCN201_DPP(dpp)\ argument
31 container_of(dpp, struct dcn201_dpp, base)
58 struct dpp base;
/linux/drivers/gpu/drm/amd/display/dc/dpp/
H A DMakefile31 AMD_DAL_DPP_DCN10 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn10/,$(DPP_DCN10))
39 AMD_DAL_DPP_DCN20 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn20/,$(DPP_DCN20))
47 AMD_DAL_DPP_DCN201 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn201/,$(DPP_DCN201))
55 AMD_DAL_DPP_DCN30 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn30/,$(DPP_DCN30))
63 AMD_DAL_DPP_DCN32 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn32/,$(DPP_DCN32))
71 AMD_DAL_DPP_DCN35 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn35/,$(DPP_DCN35))
79 AMD_DAL_DPP_DCN401 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn401/,$(DPP_DCN401))
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c89 struct dpp *dpp = pool->dpps[i]; in dcn30_log_color_state() local
92 dpp->funcs->dpp_read_state(dpp, &s); in dcn30_log_color_state()
94 if (dpp->funcs->dpp_get_gamut_remap) { in dcn30_log_color_state()
95 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); in dcn30_log_color_state()
103 dpp->inst, in dcn30_log_color_state()
158 dc->caps.color.dpp.input_lut_shared, in dcn30_log_color_state()
159 dc->caps.color.dpp.icsc, in dcn30_log_color_state()
160 dc->caps.color.dpp.dgam_ram, in dcn30_log_color_state()
161 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn30_log_color_state()
162 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn30_log_color_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/
H A Ddcn35_dpp.h53 struct dpp *dpp_base,
62 void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);
64 void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c89 struct dpp *dpp = pool->dpps[i]; in dcn20_log_color_state() local
92 dpp->funcs->dpp_read_state(dpp, &s); in dcn20_log_color_state()
93 if (dpp->funcs->dpp_get_gamut_remap) { in dcn20_log_color_state()
94 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); in dcn20_log_color_state()
102 dpp->inst, in dcn20_log_color_state()
150 dc->caps.color.dpp.input_lut_shared, in dcn20_log_color_state()
151 dc->caps.color.dpp.icsc, in dcn20_log_color_state()
152 dc->caps.color.dpp.dgam_ram, in dcn20_log_color_state()
153 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn20_log_color_state()
154 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn20_log_color_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c288 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
290 dpp->funcs->dpp_reset(dpp); in dcn201_init_hw()
308 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
314 pipe_ctx->plane_res.dpp = dpp; in dcn201_init_hw()
315 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
316 hubp->mpcc_id = dpp->inst; in dcn201_init_hw()
381 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect()
564 pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes( in dcn201_set_cursor_attribute()
565 pipe_ctx->plane_res.dpp, attributes); in dcn201_set_cursor_attribute()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c752 .dpp = true,
805 static void dcn35_dpp_destroy(struct dpp **dpp) in dcn35_dpp_destroy() argument
807 kfree(TO_DCN20_DPP(*dpp)); in dcn35_dpp_destroy()
808 *dpp = NULL; in dcn35_dpp_destroy()
811 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn35_dpp_create()
813 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); in dcn35_dpp_create() local
814 bool success = (dpp != NULL); in dcn35_dpp_create()
826 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
830 dpp, in dcn35_dpp_create()
831 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c732 .dpp = true,
785 static void dcn35_dpp_destroy(struct dpp **dpp) in dcn35_dpp_destroy() argument
787 kfree(TO_DCN20_DPP(*dpp)); in dcn35_dpp_destroy()
788 *dpp = NULL; in dcn35_dpp_destroy()
791 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn35_dpp_create()
793 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL); in dcn35_dpp_create() local
794 bool success = (dpp != NULL); in dcn35_dpp_create()
806 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
810 dpp, in dcn35_dpp_create()
811 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c1738 struct dpp *dpp, uint32_t hw_mult) in hwss_add_dpp_set_hdr_multiplier() argument
1741 seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.dpp = dpp; in hwss_add_dpp_set_hdr_multiplier()
1946 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_setup_dpp() local
1952 if (dpp && dpp->funcs->dpp_setup) { in hwss_setup_dpp()
1954 dpp->funcs->dpp_setup(dpp, in hwss_setup_dpp()
1966 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_program_bias_and_scale() local
1971 if (dpp->funcs->dpp_program_bias_and_scale) in hwss_program_bias_and_scale()
1972 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); in hwss_program_bias_and_scale()
2405 struct dpp *dpp = params->dpp_set_hdr_multiplier_params.dpp; in hwss_dpp_set_hdr_multiplier() local
2408 if (dpp->funcs->dpp_set_hdr_multiplier) in hwss_dpp_set_hdr_multiplier()
[all …]
H A Ddc_resource.c984 if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp) in calculate_adjust_recout_for_visual_confirm()
988 *dpp_offset *= pipe_ctx->plane_res.dpp->inst; in calculate_adjust_recout_for_visual_confirm()
1583 if (pipe_ctx->plane_res.dpp != NULL) in resource_build_scaling_params()
1584 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( in resource_build_scaling_params()
1585 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); in resource_build_scaling_params()
1595 if (pipe_ctx->plane_res.dpp != NULL) in resource_build_scaling_params()
1596 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( in resource_build_scaling_params()
1597 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); in resource_build_scaling_params()
1610 if (pipe_ctx->plane_res.dpp != NULL) in resource_build_scaling_params()
1611 res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( in resource_build_scaling_params()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/
H A Dhw_sequencer.h46 struct dpp;
311 struct dpp *dpp; member
568 struct dpp *dpp; member
594 struct dpp *dpp; member
673 struct dpp *dpp; member
684 struct dpp *dpp; member
1673 struct dpp *dpp, uint32_t hw_mult);
1828 struct dpp *dpp,
1879 struct dpp *dpp);
1942 struct dpp *dpp,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c407 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_populate_mcm_luts()
611 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_set_mcm_luts()
1074 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn401_set_cursor_position() local
1219 …dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.heig… in dcn401_set_cursor_position()
2852 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp in dcn401_detect_pipe_changes()
2933 struct dpp *dpp, in dcn401_plane_atomic_power_down() argument
2949 hws->funcs.dpp_pg_control(hws, dpp->inst, false); in dcn401_plane_atomic_power_down()
2955 dpp->funcs->dpp_reset(dpp); in dcn401_plane_atomic_power_down()
2965 hws->funcs.dpp_root_clock_control(hws, dpp->inst, false); in dcn401_plane_atomic_power_down()
2973 const struct dpp *dpp = pipe->plane_res.dpp; in dcn401_update_cursor_offload_pipe() local
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c169 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( in ramp_up_dispclk_with_dpp()
170 pipe_ctx->plane_res.dpp, in ramp_up_dispclk_with_dpp()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_colorop.c115 if (adev->dm.dc->caps.color.dpp.hw_3d_lut) { in amdgpu_dm_initialize_default_pipeline()
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddmub_replay.c153 if (pipe_ctx->plane_res.dpp) in dmub_replay_copy_settings()
154 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst; in dmub_replay_copy_settings()
/linux/fs/nfsd/
H A Dvfs.h75 int nfsd_cross_mnt(struct svc_rqst *rqstp, struct dentry **dpp,
/linux/fs/xfs/scrub/
H A Dparent.c414 struct xfs_inode **dpp) in xchk_parent_iget() argument
448 *dpp = ip; in xchk_parent_iget()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c442 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mpc_shaper_3dlut()
479 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_mcm_luts()
528 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn32_set_input_transfer_func()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc.h272 struct dpp_color_caps dpp; member
802 bool dpp: 1; member
822 bool dpp : 1; /* Display pipes and planes */ member
2932 } dpp[MAX_PIPES]; member

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