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Searched refs:dpp (Results 1 – 25 of 66) sorted by relevance

123

/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_cm.c43 dpp->tf_regs->reg
46 dpp->base.ctx
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
92 struct dcn10_dpp *dpp, in program_gamut_remap() argument
118 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
120 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
129 dpp->base.ctx, in program_gamut_remap()
139 dpp->base.ctx, in program_gamut_remap()
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H A Ddcn10_dpp_dscl.c44 dpp->tf_regs->reg
47 dpp->base.ctx
51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
124 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode()
158 struct dpp *dpp_base, in dpp1_power_on_dscl()
161 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl() local
163 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) { in dpp1_power_on_dscl()
168 if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) { in dpp1_power_on_dscl()
169 dpp->base.ctx->dc->optimized_required = true; in dpp1_power_on_dscl()
170 dpp->base.deferred_reg_writes.bits.disable_dscl = true; in dpp1_power_on_dscl()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp_cm.c34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 struct dpp *dpp_base) in dpp3_enable_cm_block()
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_enable_cm_block() local
57 static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base) in dpp30_get_gamcor_current()
62 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_get_gamcor_current() local
78 struct dpp *dpp_base, in dpp3_program_gammcor_lut()
84 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_gammcor_lut() local
127 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut()
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H A Ddcn30_dpp.c34 dpp->tf_regs->reg
37 dpp->base.ctx
41 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44 void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp30_read_state()
46 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_read_state() local
87 void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state) in dpp30_read_reg_state()
89 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp30_read_reg_state() local
105 struct dpp *dpp_base, in dpp3_program_post_csc()
110 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp3_program_post_csc() local
150 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11; in dpp3_program_post_csc()
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H A Ddcn30_dpp.h30 #define TO_DCN30_DPP(dpp)\ argument
31 container_of(dpp, struct dcn3_dpp, base)
561 struct dpp base;
588 struct dpp *dpp_base, const struct pwl_params *params);
591 struct dpp *dpp_base,
594 void dpp30_read_state(struct dpp *dpp_base,
597 void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state);
600 struct dpp *dpp,
605 struct dpp *dpp_base,
613 struct dpp *dpp_base,
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/
H A Ddcn20_dpp_cm.c37 dpp->tf_regs->reg
43 dpp->base.ctx
47 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 struct dpp *dpp_base) in dpp2_enable_cm_block()
53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block() local
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse()
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse() local
86 struct dpp *dpp_base, in dpp2_program_degamma_lut()
93 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_program_degamma_lut() local
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl()
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H A Ddcn20_dpp.c42 dpp->tf_regs->reg
45 dpp->base.ctx
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state()
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state() local
78 struct dpp *dpp_base, in dpp2_power_on_obuf()
81 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf() local
93 struct dpp *dpp_base, in dpp2_dummy_program_input_lut()
98 struct dpp *dpp_base, in dpp2_cnv_setup()
105 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup() local
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c35 dpp->tf_regs->reg
38 dpp->base.ctx
42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
45 struct dpp *dpp_base, in dpp201_cnv_setup()
52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup() local
191 struct dpp *dpp, in dpp201_get_optimal_number_of_taps() argument
198 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && in dpp201_get_optimal_number_of_taps()
203 dpp->ctx->dc->debug.max_downscale_src_width != 0 && in dpp201_get_optimal_number_of_taps()
204 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp201_get_optimal_number_of_taps()
251 if (!dpp->ctx->dc->debug.always_scale) { in dpp201_get_optimal_number_of_taps()
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H A Ddcn201_dpp.h30 #define TO_DCN201_DPP(dpp)\ argument
31 container_of(dpp, struct dcn201_dpp, base)
58 struct dpp base;
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/
H A Ddcn401_dpp.c36 dpp->tf_regs->reg
39 dpp->base.ctx
43 dpp->tf_shift->field_name, dpp->tf_mask->field_name
45 void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp401_read_state()
47 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp401_read_state() local
56 struct dpp *dpp_base, in dpp401_dpp_setup()
63 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_dpp_setup() local
263 struct dcn401_dpp *dpp, in dpp401_construct() argument
270 dpp->base.ctx = ctx; in dpp401_construct()
272 dpp->base.inst = inst; in dpp401_construct()
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/linux/drivers/gpu/drm/amd/display/dc/dpp/
H A DMakefile31 AMD_DAL_DPP_DCN10 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn10/,$(DPP_DCN10))
39 AMD_DAL_DPP_DCN20 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn20/,$(DPP_DCN20))
47 AMD_DAL_DPP_DCN201 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn201/,$(DPP_DCN201))
55 AMD_DAL_DPP_DCN30 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn30/,$(DPP_DCN30))
63 AMD_DAL_DPP_DCN32 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn32/,$(DPP_DCN32))
71 AMD_DAL_DPP_DCN35 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn35/,$(DPP_DCN35))
79 AMD_DAL_DPP_DCN401 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn401/,$(DPP_DCN401))
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c624 static void dcn201_dpp_destroy(struct dpp **dpp) in dcn201_dpp_destroy() argument
626 kfree(TO_DCN201_DPP(*dpp)); in dcn201_dpp_destroy()
627 *dpp = NULL; in dcn201_dpp_destroy()
630 static struct dpp *dcn201_dpp_create( in dcn201_dpp_create()
634 struct dcn201_dpp *dpp = in dcn201_dpp_create() local
637 if (!dpp) in dcn201_dpp_create()
640 if (dpp201_construct(dpp, ctx, inst, in dcn201_dpp_create()
642 return &dpp->base; in dcn201_dpp_create()
644 kfree(dpp); in dcn201_dpp_create()
1024 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c91 struct dpp *dpp = pool->dpps[i]; in dcn30_log_color_state() local
94 dpp->funcs->dpp_read_state(dpp, &s); in dcn30_log_color_state()
96 if (dpp->funcs->dpp_get_gamut_remap) { in dcn30_log_color_state()
97 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); in dcn30_log_color_state()
105 dpp->inst, in dcn30_log_color_state()
160 dc->caps.color.dpp.input_lut_shared, in dcn30_log_color_state()
161 dc->caps.color.dpp.icsc, in dcn30_log_color_state()
162 dc->caps.color.dpp.dgam_ram, in dcn30_log_color_state()
163 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn30_log_color_state()
164 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn30_log_color_state()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c464 struct dpp *dpp = pool->dpps[i]; in dcn10_log_color_state() local
467 dpp->funcs->dpp_read_state(dpp, &s); in dcn10_log_color_state()
468 if (dpp->funcs->dpp_get_gamut_remap) { in dcn10_log_color_state()
469 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); in dcn10_log_color_state()
477 dpp->inst, in dcn10_log_color_state()
523 dc->caps.color.dpp.input_lut_shared, in dcn10_log_color_state()
524 dc->caps.color.dpp.icsc, in dcn10_log_color_state()
525 dc->caps.color.dpp.dgam_ram, in dcn10_log_color_state()
526 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn10_log_color_state()
527 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn10_log_color_state()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c566 static void dcn10_dpp_destroy(struct dpp **dpp) in dcn10_dpp_destroy() argument
568 kfree(TO_DCN10_DPP(*dpp)); in dcn10_dpp_destroy()
569 *dpp = NULL; in dcn10_dpp_destroy()
572 static struct dpp *dcn10_dpp_create( in dcn10_dpp_create()
576 struct dcn10_dpp *dpp = in dcn10_dpp_create() local
579 if (!dpp) in dcn10_dpp_create()
582 dpp1_construct(dpp, ctx, inst, in dcn10_dpp_create()
584 return &dpp->base; in dcn10_dpp_create()
1105 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn10_acquire_free_pipe_for_layer()
1366 dc->caps.color.dpp.dcn_arch = 1; in dcn10_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c483 if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp) in dcn35_dpp_root_clock_control()
695 struct dpp *dpp = dc->res_pool->dpps[i]; in dcn35_init_pipes() local
720 dpp->funcs->dpp_reset(dpp); in dcn35_init_pipes()
726 pipe_ctx->plane_res.dpp = dpp; in dcn35_init_pipes()
727 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn35_init_pipes()
728 hubp->mpcc_id = dpp->inst; in dcn35_init_pipes()
819 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn35_enable_plane() local
827 dpp->funcs->dpp_dppclk_control(dpp, false, true); in dcn35_enable_plane()
859 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn35_plane_atomic_disable() local
877 dpp->funcs->dpp_dppclk_control(dpp, false, false); in dcn35_plane_atomic_disable()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c711 static void dcn301_dpp_destroy(struct dpp **dpp) in dcn301_dpp_destroy() argument
713 kfree(TO_DCN20_DPP(*dpp)); in dcn301_dpp_destroy()
714 *dpp = NULL; in dcn301_dpp_destroy()
717 static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn301_dpp_create()
719 struct dcn3_dpp *dpp = in dcn301_dpp_create() local
722 if (!dpp) in dcn301_dpp_create()
725 if (dpp3_construct(dpp, ctx, inst, in dcn301_dpp_create()
727 return &dpp->base; in dcn301_dpp_create()
730 kfree(dpp); in dcn301_dpp_create()
1449 dc->caps.color.dpp.dcn_arch = 1; in dcn301_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c519 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn303_dpp_create()
521 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); in dcn303_dpp_create() local
523 if (!dpp) in dcn303_dpp_create()
526 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
527 return &dpp->base; in dcn303_dpp_create()
530 kfree(dpp); in dcn303_dpp_create()
1188 dc->caps.color.dpp.dcn_arch = 1; in dcn303_resource_construct()
1189 dc->caps.color.dpp.input_lut_shared = 0; in dcn303_resource_construct()
1190 dc->caps.color.dpp.icsc = 1; in dcn303_resource_construct()
1191 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn303_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c541 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn302_dpp_create()
543 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); in dcn302_dpp_create() local
545 if (!dpp) in dcn302_dpp_create()
548 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
549 return &dpp->base; in dcn302_dpp_create()
552 kfree(dpp); in dcn302_dpp_create()
1244 dc->caps.color.dpp.dcn_arch = 1; in dcn302_resource_construct()
1245 dc->caps.color.dpp.input_lut_shared = 0; in dcn302_resource_construct()
1246 dc->caps.color.dpp.icsc = 1; in dcn302_resource_construct()
1247 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn302_resource_construct()
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/linux/arch/sparc/vdso/
H A Dvma.c251 struct page *dp, **dpp = NULL; in init_vdso_image() local
291 dpp = kzalloc_objs(struct page *, dnpages); in init_vdso_image()
292 vvar_mapping.pages = dpp; in init_vdso_image()
294 if (!dpp) in init_vdso_image()
301 dpp[0] = dp; in init_vdso_image()
319 if (dpp != NULL) { in init_vdso_image()
321 if (dpp[i] != NULL) in init_vdso_image()
322 __free_page(dpp[i]); in init_vdso_image()
324 kfree(dpp); in init_vdso_image()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c90 struct dpp *dpp = pool->dpps[i]; in dcn20_log_color_state() local
93 dpp->funcs->dpp_read_state(dpp, &s); in dcn20_log_color_state()
94 if (dpp->funcs->dpp_get_gamut_remap) { in dcn20_log_color_state()
95 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); in dcn20_log_color_state()
103 dpp->inst, in dcn20_log_color_state()
151 dc->caps.color.dpp.input_lut_shared, in dcn20_log_color_state()
152 dc->caps.color.dpp.icsc, in dcn20_log_color_state()
153 dc->caps.color.dpp.dgam_ram, in dcn20_log_color_state()
154 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn20_log_color_state()
155 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn20_log_color_state()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c499 static struct dpp *dcn21_dpp_create( in dcn21_dpp_create()
503 struct dcn20_dpp *dpp = in dcn21_dpp_create() local
506 if (!dpp) in dcn21_dpp_create()
509 if (dpp2_construct(dpp, ctx, inst, in dcn21_dpp_create()
511 return &dpp->base; in dcn21_dpp_create()
514 kfree(dpp); in dcn21_dpp_create()
1426 dc->caps.color.dpp.dcn_arch = 1; in dcn21_resource_construct()
1427 dc->caps.color.dpp.input_lut_shared = 0; in dcn21_resource_construct()
1428 dc->caps.color.dpp.icsc = 1; in dcn21_resource_construct()
1429 dc->caps.color.dpp.dgam_ram = 1; in dcn21_resource_construct()
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c291 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
293 dpp->funcs->dpp_reset(dpp); in dcn201_init_hw()
311 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
317 pipe_ctx->plane_res.dpp = dpp; in dcn201_init_hw()
318 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
319 hubp->mpcc_id = dpp->inst; in dcn201_init_hw()
384 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect()
567 pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes( in dcn201_set_cursor_attribute()
568 pipe_ctx->plane_res.dpp, attributes); in dcn201_set_cursor_attribute()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/
H A Ddcn35_dpp.h53 struct dpp *dpp_base,
62 void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);
64 void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c903 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
905 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
906 *dpp = NULL; in dcn31_dpp_destroy()
909 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
913 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
916 if (!dpp) in dcn31_dpp_create()
919 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
921 return &dpp->base; in dcn31_dpp_create()
924 kfree(dpp); in dcn31_dpp_create()
1769 dc->caps.color.dpp.dcn_arch = 1; in dcn316_resource_construct()
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