| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 35 dpp->tf_regs->reg
38 dpp->base.ctx
42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
45 struct dpp *dpp_base, in dpp201_cnv_setup()
52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup() local
191 struct dpp *dpp, in dpp201_get_optimal_number_of_taps() argument
198 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && in dpp201_get_optimal_number_of_taps()
203 dpp->ctx->dc->debug.max_downscale_src_width != 0 && in dpp201_get_optimal_number_of_taps()
204 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp201_get_optimal_number_of_taps()
251 if (!dpp->ctx->dc->debug.always_scale) { in dpp201_get_optimal_number_of_taps()
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| H A D | dcn201_dpp.h | 30 #define TO_DCN201_DPP(dpp)\ argument
31 container_of(dpp, struct dcn201_dpp, base)
58 struct dpp base;
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| H A D | dcn401_dpp.c | 36 dpp->tf_regs->reg
39 dpp->base.ctx
43 dpp->tf_shift->field_name, dpp->tf_mask->field_name
45 void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s) in dpp401_read_state()
47 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base); in dpp401_read_state() local
56 struct dpp *dpp_base, in dpp401_dpp_setup()
63 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); in dpp401_dpp_setup() local
263 struct dcn401_dpp *dpp, in dpp401_construct() argument
270 dpp->base.ctx = ctx; in dpp401_construct()
272 dpp->base.inst = inst; in dpp401_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 625 static void dcn201_dpp_destroy(struct dpp **dpp) in dcn201_dpp_destroy() argument
627 kfree(TO_DCN201_DPP(*dpp)); in dcn201_dpp_destroy()
628 *dpp = NULL; in dcn201_dpp_destroy()
631 static struct dpp *dcn201_dpp_create( in dcn201_dpp_create()
635 struct dcn201_dpp *dpp = in dcn201_dpp_create() local
638 if (!dpp) in dcn201_dpp_create()
641 if (dpp201_construct(dpp, ctx, inst, in dcn201_dpp_create()
643 return &dpp->base; in dcn201_dpp_create()
645 kfree(dpp); in dcn201_dpp_create()
1057 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn201_acquire_free_pipe_for_layer()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 594 static void dcn10_dpp_destroy(struct dpp **dpp) in dcn10_dpp_destroy() argument
596 kfree(TO_DCN10_DPP(*dpp)); in dcn10_dpp_destroy()
597 *dpp = NULL; in dcn10_dpp_destroy()
600 static struct dpp *dcn10_dpp_create( in dcn10_dpp_create()
604 struct dcn10_dpp *dpp = in dcn10_dpp_create() local
607 if (!dpp) in dcn10_dpp_create()
610 dpp1_construct(dpp, ctx, inst, in dcn10_dpp_create()
612 return &dpp->base; in dcn10_dpp_create()
1141 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; in dcn10_acquire_free_pipe_for_layer()
1409 dc->caps.color.dpp.dcn_arch = 1; in dcn10_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 547 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn303_dpp_create()
549 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); in dcn303_dpp_create() local
551 if (!dpp) in dcn303_dpp_create()
554 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
555 return &dpp->base; in dcn303_dpp_create()
558 kfree(dpp); in dcn303_dpp_create()
1223 dc->caps.color.dpp.dcn_arch = 1; in dcn303_resource_construct()
1224 dc->caps.color.dpp.input_lut_shared = 0; in dcn303_resource_construct()
1225 dc->caps.color.dpp.icsc = 1; in dcn303_resource_construct()
1226 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 569 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn302_dpp_create()
571 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); in dcn302_dpp_create() local
573 if (!dpp) in dcn302_dpp_create()
576 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
577 return &dpp->base; in dcn302_dpp_create()
580 kfree(dpp); in dcn302_dpp_create()
1279 dc->caps.color.dpp.dcn_arch = 1; in dcn302_resource_construct()
1280 dc->caps.color.dpp.input_lut_shared = 0; in dcn302_resource_construct()
1281 dc->caps.color.dpp.icsc = 1; in dcn302_resource_construct()
1282 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 712 static void dcn301_dpp_destroy(struct dpp **dpp) in dcn301_dpp_destroy() argument
714 kfree(TO_DCN20_DPP(*dpp)); in dcn301_dpp_destroy()
715 *dpp = NULL; in dcn301_dpp_destroy()
718 static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn301_dpp_create()
720 struct dcn3_dpp *dpp = in dcn301_dpp_create() local
723 if (!dpp) in dcn301_dpp_create()
726 if (dpp3_construct(dpp, ctx, inst, in dcn301_dpp_create()
728 return &dpp->base; in dcn301_dpp_create()
731 kfree(dpp); in dcn301_dpp_create()
1485 dc->caps.color.dpp.dcn_arch = 1; in dcn301_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/ |
| H A D | dcn35_dpp.h | 53 struct dpp *dpp_base,
62 void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);
64 void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp.h | 30 #define TO_DCN30_DPP(dpp)\ argument
31 container_of(dpp, struct dcn3_dpp, base)
561 struct dpp base;
588 struct dpp *dpp_base, const struct pwl_params *params);
591 struct dpp *dpp_base,
594 void dpp30_read_state(struct dpp *dpp_base,
597 void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state);
600 struct dpp *dpp,
605 struct dpp *dpp_base,
613 struct dpp *dpp_base,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 519 static struct dpp *dcn21_dpp_create( in dcn21_dpp_create()
523 struct dcn20_dpp *dpp = in dcn21_dpp_create() local
526 if (!dpp) in dcn21_dpp_create()
529 if (dpp2_construct(dpp, ctx, inst, in dcn21_dpp_create()
531 return &dpp->base; in dcn21_dpp_create()
534 kfree(dpp); in dcn21_dpp_create()
1467 dc->caps.color.dpp.dcn_arch = 1; in dcn21_resource_construct()
1468 dc->caps.color.dpp.input_lut_shared = 0; in dcn21_resource_construct()
1469 dc->caps.color.dpp.icsc = 1; in dcn21_resource_construct()
1470 dc->caps.color.dpp.dgam_ram = 1; in dcn21_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 291 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
293 dpp->funcs->dpp_reset(dpp); in dcn201_init_hw()
311 struct dpp *dpp = res_pool->dpps[i]; in dcn201_init_hw() local
317 pipe_ctx->plane_res.dpp = dpp; in dcn201_init_hw()
318 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
319 hubp->mpcc_id = dpp->inst; in dcn201_init_hw()
384 int dpp_id = pipe_ctx->plane_res.dpp->inst; in dcn201_plane_atomic_disconnect()
567 pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes( in dcn201_set_cursor_attribute()
568 pipe_ctx->plane_res.dpp, attributes); in dcn201_set_cursor_attribute()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 929 .dpp = true,
963 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
965 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
966 *dpp = NULL; in dcn31_dpp_destroy()
969 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
973 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
976 if (!dpp) in dcn31_dpp_create()
979 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
981 return &dpp->base; in dcn31_dpp_create()
984 kfree(dpp); in dcn31_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 746 .dpp = true,
799 static void dcn35_dpp_destroy(struct dpp **dpp) in dcn35_dpp_destroy() argument
801 kfree(TO_DCN20_DPP(*dpp)); in dcn35_dpp_destroy()
802 *dpp = NULL; in dcn35_dpp_destroy()
805 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn35_dpp_create()
807 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); in dcn35_dpp_create() local
808 bool success = (dpp != NULL); in dcn35_dpp_create()
820 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
824 dpp, in dcn35_dpp_create()
825 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 766 .dpp = true,
819 static void dcn35_dpp_destroy(struct dpp **dpp) in dcn35_dpp_destroy() argument
821 kfree(TO_DCN20_DPP(*dpp)); in dcn35_dpp_destroy()
822 *dpp = NULL; in dcn35_dpp_destroy()
825 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn35_dpp_create()
827 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); in dcn35_dpp_create() local
828 bool success = (dpp != NULL); in dcn35_dpp_create()
840 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
844 dpp, in dcn35_dpp_create()
845 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 753 .dpp = true,
806 static void dcn35_dpp_destroy(struct dpp **dpp) in dcn35_dpp_destroy() argument
808 kfree(TO_DCN20_DPP(*dpp)); in dcn35_dpp_destroy()
809 *dpp = NULL; in dcn35_dpp_destroy()
812 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn35_dpp_create()
814 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); in dcn35_dpp_create() local
815 bool success = (dpp != NULL); in dcn35_dpp_create()
827 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
831 dpp, in dcn35_dpp_create()
832 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 850 block_sequence[*num_steps].params.control_cm_hist_params.dpp in hwss_build_fast_sequence()
851 = current_mpc_pipe->plane_res.dpp; in hwss_build_fast_sequence()
1753 struct dpp *dpp, uint32_t hw_mult) in hwss_add_dpp_set_hdr_multiplier() argument
1756 seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.dpp = dpp; in hwss_add_dpp_set_hdr_multiplier()
1961 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_setup_dpp() local
1967 if (dpp && dpp->funcs->dpp_setup) { in hwss_setup_dpp()
1969 dpp->funcs->dpp_setup(dpp, in hwss_setup_dpp()
1981 struct dpp *dpp = pipe_ctx->plane_res.dpp; in hwss_program_bias_and_scale() local
1986 if (dpp->funcs->dpp_program_bias_and_scale) in hwss_program_bias_and_scale()
1987 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); in hwss_program_bias_and_scale()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 919 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
921 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
922 *dpp = NULL; in dcn31_dpp_destroy()
925 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
929 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
932 if (!dpp) in dcn31_dpp_create()
935 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
937 return &dpp->base; in dcn31_dpp_create()
940 kfree(dpp); in dcn31_dpp_create()
1812 dc->caps.color.dpp.dcn_arch = 1; in dcn316_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 927 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
929 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
930 *dpp = NULL; in dcn31_dpp_destroy()
933 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
937 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
940 if (!dpp) in dcn31_dpp_create()
943 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
945 return &dpp->base; in dcn31_dpp_create()
948 kfree(dpp); in dcn31_dpp_create()
1966 dc->caps.color.dpp.dcn_arch = 1; in dcn31_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 926 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
928 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
929 *dpp = NULL; in dcn31_dpp_destroy()
932 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
936 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
939 if (!dpp) in dcn31_dpp_create()
942 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
944 return &dpp->base; in dcn31_dpp_create()
947 kfree(dpp); in dcn31_dpp_create()
1936 dc->caps.color.dpp.dcn_arch = 1; in dcn315_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 746 static void dcn30_dpp_destroy(struct dpp **dpp) in dcn30_dpp_destroy() argument
748 kfree(TO_DCN20_DPP(*dpp)); in dcn30_dpp_destroy()
749 *dpp = NULL; in dcn30_dpp_destroy()
752 static struct dpp *dcn30_dpp_create( in dcn30_dpp_create()
756 struct dcn3_dpp *dpp = in dcn30_dpp_create() local
759 if (!dpp) in dcn30_dpp_create()
762 if (dpp3_construct(dpp, ctx, inst, in dcn30_dpp_create()
764 return &dpp->base; in dcn30_dpp_create()
767 kfree(dpp); in dcn30_dpp_create()
1571 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 756 void dcn20_dpp_destroy(struct dpp **dpp) in dcn20_dpp_destroy() argument
758 kfree(TO_DCN20_DPP(*dpp)); in dcn20_dpp_destroy()
759 *dpp = NULL; in dcn20_dpp_destroy()
762 struct dpp *dcn20_dpp_create( in dcn20_dpp_create()
766 struct dcn20_dpp *dpp = in dcn20_dpp_create() local
769 if (!dpp) in dcn20_dpp_create()
772 if (dpp2_construct(dpp, ctx, inst, in dcn20_dpp_create()
774 return &dpp->base; in dcn20_dpp_create()
777 kfree(dpp); in dcn20_dpp_create()
1531 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 940 static void dcn321_dpp_destroy(struct dpp **dpp) in dcn321_dpp_destroy() argument
942 kfree(TO_DCN30_DPP(*dpp)); in dcn321_dpp_destroy()
943 *dpp = NULL; in dcn321_dpp_destroy()
946 static struct dpp *dcn321_dpp_create( in dcn321_dpp_create()
1780 dc->caps.color.dpp.dcn_arch = 1; in dcn321_resource_construct()
1781 dc->caps.color.dpp.input_lut_shared = 0; in dcn321_resource_construct()
1782 dc->caps.color.dpp.icsc = 1; in dcn321_resource_construct()
1783 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn321_resource_construct()
1784 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; in dcn321_resource_construct()
1785 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; in dcn321_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 391 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn401_set_mcm_luts()
973 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn401_set_cursor_position() local
1140 …dpp->funcs->set_cursor_position(dpp, &pos_cpy, ¶m, hubp->curs_attr.width, hubp->curs_attr.heig… in dcn401_set_cursor_position()
2331 hwss_add_dpp_program_cm_hist(seq_state, pipe_ctx->plane_res.dpp, in dcn401_program_pipe_sequence()
2801 if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp in dcn401_detect_pipe_changes()
2882 struct dpp *dpp, in dcn401_plane_atomic_power_down() argument
2896 hws->funcs.dpp_pg_control(hws, dpp->inst, false); in dcn401_plane_atomic_power_down()
2902 dpp->funcs->dpp_reset(dpp); in dcn401_plane_atomic_power_down()
2912 hws->funcs.dpp_root_clock_control(hws, dpp->inst, false); in dcn401_plane_atomic_power_down()
2920 const struct dpp *dpp = pipe->plane_res.dpp; in dcn401_update_cursor_offload_pipe() local
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 951 static void dcn32_dpp_destroy(struct dpp **dpp) in dcn32_dpp_destroy() argument
953 kfree(TO_DCN30_DPP(*dpp)); in dcn32_dpp_destroy()
954 *dpp = NULL; in dcn32_dpp_destroy()
957 static struct dpp *dcn32_dpp_create( in dcn32_dpp_create()
2287 dc->caps.color.dpp.dcn_arch = 1; in dcn32_resource_construct()
2288 dc->caps.color.dpp.input_lut_shared = 0; in dcn32_resource_construct()
2289 dc->caps.color.dpp.icsc = 1; in dcn32_resource_construct()
2290 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn32_resource_construct()
2291 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; in dcn32_resource_construct()
2292 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; in dcn32_resource_construct()
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