| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| H A D | dcn201_dpp.c | 35 dpp->tf_regs->reg
38 dpp->base.ctx
42 dpp->tf_shift->field_name, dpp->tf_mask->field_name
45 struct dpp *dpp_base, in dpp201_cnv_setup()
52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup() local
191 struct dpp *dpp, in dpp201_get_optimal_number_of_taps() argument
198 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && in dpp201_get_optimal_number_of_taps()
203 dpp->ctx->dc->debug.max_downscale_src_width != 0 && in dpp201_get_optimal_number_of_taps()
204 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp201_get_optimal_number_of_taps()
251 if (!dpp->ctx->dc->debug.always_scale) { in dpp201_get_optimal_number_of_taps()
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| H A D | dcn201_dpp.h | 30 #define TO_DCN201_DPP(dpp)\ argument
31 container_of(dpp, struct dcn201_dpp, base)
58 struct dpp base;
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn30/ |
| H A D | dcn30_hwseq.c | 92 struct dpp *dpp = pool->dpps[i]; in dcn30_log_color_state() local
95 dpp->funcs->dpp_read_state(dpp, &s); in dcn30_log_color_state()
97 if (dpp->funcs->dpp_get_gamut_remap) { in dcn30_log_color_state()
98 dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap); in dcn30_log_color_state()
106 dpp->inst, in dcn30_log_color_state()
161 dc->caps.color.dpp.input_lut_shared, in dcn30_log_color_state()
162 dc->caps.color.dpp.icsc, in dcn30_log_color_state()
163 dc->caps.color.dpp.dgam_ram, in dcn30_log_color_state()
164 dc->caps.color.dpp.dgam_rom_caps.srgb, in dcn30_log_color_state()
165 dc->caps.color.dpp.dgam_rom_caps.bt2020, in dcn30_log_color_state()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn50/ |
| H A D | dcn50_hwseq.c | 90 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dcn50_update_dchubp_dpp() local
97 dpp->funcs->dpp_dppclk_control(dpp, false, true); in dcn50_update_dchubp_dpp()
100 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz); in dcn50_update_dchubp_dpp()
151 dpp->funcs->dpp_setup(dpp, in dcn50_update_dchubp_dpp()
158 if (dpp->funcs->set_cursor_matrix) { in dcn50_update_dchubp_dpp()
159 dpp->funcs->set_cursor_matrix(dpp, in dcn50_update_dchubp_dpp()
163 if (dpp->funcs->dpp_program_bias_and_scale) { in dcn50_update_dchubp_dpp()
165 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); in dcn50_update_dchubp_dpp()
185 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler( in dcn50_update_dchubp_dpp()
186 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); in dcn50_update_dchubp_dpp()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_surface.c | 161 struct dpp *dpp = pipe_ctx->plane_res.dpp; in dc_plane_get_status() local
163 if (dpp && dpp->funcs->dpp_cm_hist_read) in dc_plane_get_status()
164 dpp->funcs->dpp_cm_hist_read(dpp, &pipe_ctx->plane_state->status.cm_hist); in dc_plane_get_status()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn35/ |
| H A D | dcn35_dpp.h | 53 struct dpp *dpp_base,
62 void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);
64 void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/ |
| H A D | dcn303_resource.c | 637 static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn303_dpp_create()
639 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); in dcn303_dpp_create() local
641 if (!dpp) in dcn303_dpp_create()
644 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn303_dpp_create()
645 return &dpp->base; in dcn303_dpp_create()
648 kfree(dpp); in dcn303_dpp_create()
1333 dc->caps.color.dpp.dcn_arch = 1; in dcn303_resource_construct()
1334 dc->caps.color.dpp.input_lut_shared = 0; in dcn303_resource_construct()
1335 dc->caps.color.dpp.icsc = 1; in dcn303_resource_construct()
1336 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn303_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/ |
| H A D | dcn302_resource.c | 659 static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn302_dpp_create()
661 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); in dcn302_dpp_create() local
663 if (!dpp) in dcn302_dpp_create()
666 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask)) in dcn302_dpp_create()
667 return &dpp->base; in dcn302_dpp_create()
670 kfree(dpp); in dcn302_dpp_create()
1389 dc->caps.color.dpp.dcn_arch = 1; in dcn302_resource_construct()
1390 dc->caps.color.dpp.input_lut_shared = 0; in dcn302_resource_construct()
1391 dc->caps.color.dpp.icsc = 1; in dcn302_resource_construct()
1392 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn302_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp.h | 30 #define TO_DCN30_DPP(dpp)\ argument
31 container_of(dpp, struct dcn3_dpp, base)
561 struct dpp base;
588 struct dpp *dpp_base, const struct pwl_params *params);
591 struct dpp *dpp_base,
594 void dpp30_read_state(struct dpp *dpp_base,
597 void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state);
600 struct dpp *dpp,
605 struct dpp *dpp_base,
613 struct dpp *dpp_base,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/ |
| H A D | dcn316_resource.c | 964 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
966 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
967 *dpp = NULL; in dcn31_dpp_destroy()
970 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
974 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
977 if (!dpp) in dcn31_dpp_create()
980 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
982 return &dpp->base; in dcn31_dpp_create()
985 kfree(dpp); in dcn31_dpp_create()
1942 dc->caps.color.dpp.dcn_arch = 1; in dcn316_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 973 .dpp = true,
1007 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
1009 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
1010 *dpp = NULL; in dcn31_dpp_destroy()
1013 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
1017 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
1020 if (!dpp) in dcn31_dpp_create()
1023 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
1025 return &dpp->base; in dcn31_dpp_create()
1028 kfree(dpp); in dcn31_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/ |
| H A D | dcn36_resource.c | 791 .dpp = true,
843 static void dcn35_dpp_destroy(struct dpp **dpp) in dcn35_dpp_destroy() argument
845 kfree(TO_DCN20_DPP(*dpp)); in dcn35_dpp_destroy()
846 *dpp = NULL; in dcn35_dpp_destroy()
849 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn35_dpp_create()
851 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); in dcn35_dpp_create() local
852 bool success = (dpp != NULL); in dcn35_dpp_create()
864 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
868 dpp, in dcn35_dpp_create()
869 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 804 .dpp = true,
856 static void dcn35_dpp_destroy(struct dpp **dpp) in dcn35_dpp_destroy() argument
858 kfree(TO_DCN20_DPP(*dpp)); in dcn35_dpp_destroy()
859 *dpp = NULL; in dcn35_dpp_destroy()
862 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn35_dpp_create()
864 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); in dcn35_dpp_create() local
865 bool success = (dpp != NULL); in dcn35_dpp_create()
877 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
881 dpp, in dcn35_dpp_create()
882 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 784 .dpp = true,
836 static void dcn35_dpp_destroy(struct dpp **dpp) in dcn35_dpp_destroy() argument
838 kfree(TO_DCN20_DPP(*dpp)); in dcn35_dpp_destroy()
839 *dpp = NULL; in dcn35_dpp_destroy()
842 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst) in dcn35_dpp_create()
844 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp); in dcn35_dpp_create() local
845 bool success = (dpp != NULL); in dcn35_dpp_create()
857 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, in dcn35_dpp_create()
861 dpp, in dcn35_dpp_create()
862 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp); in dcn35_dpp_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/ |
| H A D | dcn315_resource.c | 971 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
973 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
974 *dpp = NULL; in dcn31_dpp_destroy()
977 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
981 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
984 if (!dpp) in dcn31_dpp_create()
987 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
989 return &dpp->base; in dcn31_dpp_create()
992 kfree(dpp); in dcn31_dpp_create()
2068 dc->caps.color.dpp.dcn_arch = 1; in dcn315_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.c | 972 static void dcn31_dpp_destroy(struct dpp **dpp) in dcn31_dpp_destroy() argument
974 kfree(TO_DCN20_DPP(*dpp)); in dcn31_dpp_destroy()
975 *dpp = NULL; in dcn31_dpp_destroy()
978 static struct dpp *dcn31_dpp_create( in dcn31_dpp_create()
982 struct dcn3_dpp *dpp = in dcn31_dpp_create() local
985 if (!dpp) in dcn31_dpp_create()
988 if (dpp3_construct(dpp, ctx, inst, in dcn31_dpp_create()
990 return &dpp->base; in dcn31_dpp_create()
993 kfree(dpp); in dcn31_dpp_create()
2096 dc->caps.color.dpp.dcn_arch = 1; in dcn31_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 790 static void dcn30_dpp_destroy(struct dpp **dpp) in dcn30_dpp_destroy() argument
792 kfree(TO_DCN20_DPP(*dpp)); in dcn30_dpp_destroy()
793 *dpp = NULL; in dcn30_dpp_destroy()
796 static struct dpp *dcn30_dpp_create( in dcn30_dpp_create()
800 struct dcn3_dpp *dpp = in dcn30_dpp_create() local
803 if (!dpp) in dcn30_dpp_create()
806 if (dpp3_construct(dpp, ctx, inst, in dcn30_dpp_create()
808 return &dpp->base; in dcn30_dpp_create()
811 kfree(dpp); in dcn30_dpp_create()
1698 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/ |
| H A D | dcn321_resource.c | 978 static void dcn321_dpp_destroy(struct dpp **dpp) in dcn321_dpp_destroy() argument
980 kfree(TO_DCN30_DPP(*dpp)); in dcn321_dpp_destroy()
981 *dpp = NULL; in dcn321_dpp_destroy()
984 static struct dpp *dcn321_dpp_create( in dcn321_dpp_create()
1911 dc->caps.color.dpp.dcn_arch = 1; in dcn321_resource_construct()
1912 dc->caps.color.dpp.input_lut_shared = 0; in dcn321_resource_construct()
1913 dc->caps.color.dpp.icsc = 1; in dcn321_resource_construct()
1914 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn321_resource_construct()
1915 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; in dcn321_resource_construct()
1916 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; in dcn321_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42/ |
| H A D | dcn42_resource.c | 768 .dpp = true,
1016 static void dcn42_dpp_destroy(struct dpp **dpp) in dcn42_dpp_destroy() argument
1018 kfree(TO_DCN42_DPP(*dpp)); in dcn42_dpp_destroy()
1019 *dpp = NULL; in dcn42_dpp_destroy()
1022 static struct dpp *dcn42_dpp_create( in dcn42_dpp_create()
2055 dc->caps.color.dpp.dcn_arch = 1; in dcn42_resource_construct()
2056 dc->caps.color.dpp.input_lut_shared = 0; in dcn42_resource_construct()
2057 dc->caps.color.dpp.icsc = 1; in dcn42_resource_construct()
2058 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn42_resource_construct()
2059 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; in dcn42_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn60/ |
| H A D | dcn60_resource.c | 1159 static void dcn60_dpp_destroy(struct dpp **dpp) in dcn60_dpp_destroy() argument
1161 kfree(TO_DCN60_DPP(*dpp)); in dcn60_dpp_destroy()
1162 *dpp = NULL; in dcn60_dpp_destroy()
1165 static struct dpp *dcn60_dpp_create( in dcn60_dpp_create()
2042 dc->caps.color.dpp.dcn_arch = 1; in dcn60_resource_construct()
2043 dc->caps.color.dpp.input_lut_shared = 0; in dcn60_resource_construct()
2044 dc->caps.color.dpp.icsc = 1; in dcn60_resource_construct()
2045 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn60_resource_construct()
2046 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; in dcn60_resource_construct()
2047 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; in dcn60_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/ |
| H A D | dcn401_resource.c | 995 static void dcn401_dpp_destroy(struct dpp **dpp) in dcn401_dpp_destroy() argument
997 kfree(TO_DCN401_DPP(*dpp)); in dcn401_dpp_destroy()
998 *dpp = NULL; in dcn401_dpp_destroy()
1001 static struct dpp *dcn401_dpp_create( in dcn401_dpp_create()
2117 dc->caps.color.dpp.dcn_arch = 1; in dcn401_resource_construct()
2118 dc->caps.color.dpp.input_lut_shared = 0; in dcn401_resource_construct()
2119 dc->caps.color.dpp.icsc = 1; in dcn401_resource_construct()
2120 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn401_resource_construct()
2121 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; in dcn401_resource_construct()
2122 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; in dcn401_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn42b/ |
| H A D | dcn42b_resource.c | 821 .dpp = false,
1075 static void dcn42b_dpp_destroy(struct dpp **dpp) in dcn42b_dpp_destroy() argument
1077 kfree(TO_DCN42_DPP(*dpp)); in dcn42b_dpp_destroy()
1078 *dpp = NULL; in dcn42b_dpp_destroy()
1081 static struct dpp *dcn42b_dpp_create( in dcn42b_dpp_create()
2039 dc->caps.color.dpp.dcn_arch = 1; in dcn42b_resource_construct()
2040 dc->caps.color.dpp.input_lut_shared = 0; in dcn42b_resource_construct()
2041 dc->caps.color.dpp.icsc = 1; in dcn42b_resource_construct()
2042 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn42b_resource_construct()
2043 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; in dcn42b_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn60/ |
| H A D | dcn60_hwseq.c | 780 pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes( in dcn60_set_cursor_attribute()
781 pipe_ctx->plane_res.dpp, attributes); in dcn60_set_cursor_attribute()
789 const struct dpp *dpp = pipe->plane_res.dpp; in dcn60_update_cursor_offload_pipe() local
793 if (!top_pipe || !hubp || !dpp) in dcn60_update_cursor_offload_pipe()
817 p->CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable; in dcn60_update_cursor_offload_pipe()
818 p->CM_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode; in dcn60_update_cursor_offload_pipe()
819 p->CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE = dpp->att.cur0_ctl.bits.expansion_mode; in dcn60_update_cursor_offload_pipe()
820 p->CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN = dpp->att.cur0_ctl.bits.cur0_rom_en; in dcn60_update_cursor_offload_pipe()
825 dpp->att.fp_scale_bias_g_y.bits.fp_bias_g_y; in dcn60_update_cursor_offload_pipe()
827 dpp->att.fp_scale_bias_g_y.bits.fp_scale_g_y; in dcn60_update_cursor_offload_pipe()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.c | 990 static void dcn32_dpp_destroy(struct dpp **dpp) in dcn32_dpp_destroy() argument
992 kfree(TO_DCN30_DPP(*dpp)); in dcn32_dpp_destroy()
993 *dpp = NULL; in dcn32_dpp_destroy()
996 static struct dpp *dcn32_dpp_create( in dcn32_dpp_create()
2420 dc->caps.color.dpp.dcn_arch = 1; in dcn32_resource_construct()
2421 dc->caps.color.dpp.input_lut_shared = 0; in dcn32_resource_construct()
2422 dc->caps.color.dpp.icsc = 1; in dcn32_resource_construct()
2423 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr in dcn32_resource_construct()
2424 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; in dcn32_resource_construct()
2425 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; in dcn32_resource_construct()
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| /linux/fs/xfs/libxfs/ |
| H A D | xfs_dquot_buf.c | 477 struct xfs_inode **dpp) in xfs_dqinode_mkdir_parent() argument
484 return xfs_metadir_mkdir(mp->m_metadirip, "quota", dpp); in xfs_dqinode_mkdir_parent()
495 struct xfs_inode **dpp) in xfs_dqinode_load_parent() argument
505 dpp); in xfs_dqinode_load_parent()
|