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Searched refs:dpll_state (Results 1 – 7 of 7) sorted by relevance

/linux/include/linux/mfd/
H A Didt82p33_reg.h105 enum dpll_state { enum
H A DidtRC38xxx_reg.h156 enum dpll_state { enum
H A Didt8a340_reg.h738 enum dpll_state { enum
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c857 *status = d->dpll_state; in ice_dpll_lock_status_get()
2622 if (d->prev_dpll_state != d->dpll_state) { in ice_dpll_notify_changes()
2623 d->prev_dpll_state = d->dpll_state; in ice_dpll_notify_changes()
2767 &d->phase_offset, &d->dpll_state); in ice_dpll_update_state()
2772 d->dpll_state, d->prev_dpll_state, d->mode); in ice_dpll_update_state()
2781 if (d->dpll_state == DPLL_LOCK_STATUS_LOCKED || in ice_dpll_update_state()
2782 d->dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ) in ice_dpll_update_state()
2788 if (d->dpll_state == DPLL_LOCK_STATUS_HOLDOVER || in ice_dpll_update_state()
2789 d->dpll_state == DPLL_LOCK_STATUS_UNLOCKED) { in ice_dpll_update_state()
H A Dice_ptp_hw.h366 enum dpll_lock_status *dpll_state);
H A Dice_common.c5522 u8 *dpll_state, u8 *config, s64 *phase_offset, in ice_aq_get_cgu_dpll_status() argument
5536 *dpll_state = cmd->dpll_state; in ice_aq_get_cgu_dpll_status()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_types.h647 struct intel_dpll_state dpll_state[I915_NUM_PLLS]; member