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/linux/Documentation/driver-api/cxl/linux/example-configurations/
H A Dhb-interleave.rst46 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
50 The `ports:root0` section lays out how each of these downstream ports are
79 This chunk shows the available downstream ports associated with the CXL Host
80 Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
250 applies the interleave across the downstream ports :code:`port1` and
H A Dintra-hb-interleave.rst46 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
50 The `ports:root0` section lays out how each of these downstream ports are
79 This chunk shows the available downstream ports associated with the CXL Host
80 Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
234 applies the interleave across the downstream ports :code:`port1` and
H A Dsingle-device.rst46 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
50 The `ports:root0` section lays out how each of these downstream ports are
79 This chunk shows the available downstream ports associated with the CXL Host
80 Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
H A Dmulti-interleave.rst47 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
51 The `ports:root0` section lays out how each of these downstream ports are
80 This chunk shows the available downstream ports associated with the CXL Host
81 Bridge :code:`port1`. In this case, :code:`port1` has 3 available downstream
326 applies the interleave across the downstream ports :code:`port1` and
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2080a.dtsi141 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
149 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
157 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
165 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
/linux/drivers/thunderbolt/
H A Dtb.c615 bool downstream; in tb_consumed_dp_bandwidth() local
664 downstream = tb_port_path_direction_downstream(src_port, dst_port); in tb_consumed_dp_bandwidth()
666 if (downstream) in tb_consumed_dp_bandwidth()
678 bool downstream = tb_port_path_direction_downstream(src_port, dst_port); in tb_asym_supported() local
682 width = downstream ? TB_LINK_WIDTH_ASYM_RX : TB_LINK_WIDTH_ASYM_TX; in tb_asym_supported()
684 width = downstream ? TB_LINK_WIDTH_ASYM_TX : TB_LINK_WIDTH_ASYM_RX; in tb_asym_supported()
711 bool downstream = tb_port_path_direction_downstream(src_port, dst_port); in tb_maximum_bandwidth() local
740 if (downstream) { in tb_maximum_bandwidth()
773 if (downstream) { in tb_maximum_bandwidth()
1043 bool clx = false, clx_disabled = false, downstream; in tb_configure_asym() local
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H A Ddebugfs.c1795 struct tb_port *upstream, *downstream; in margining_switch_init() local
1804 downstream = tb_port_at(route, parent_sw); in margining_switch_init()
1806 margining_port_init(downstream); in margining_switch_init()
1812 struct tb_port *upstream, *downstream; in margining_switch_remove() local
1821 downstream = tb_port_at(route, parent_sw); in margining_switch_remove()
1824 margining_port_remove(downstream); in margining_switch_remove()
1830 struct tb_port *downstream; in margining_xdomain_init() local
1833 downstream = tb_port_at(xd->route, parent_sw); in margining_xdomain_init()
1835 margining_port_init(downstream); in margining_xdomain_init()
1841 struct tb_port *downstream; in margining_xdomain_remove() local
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/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-mux-ltc4306.txt24 - ltc,downstream-accelerators-enable: Enables the rise time accelerators
25 on the downstream port.
/linux/drivers/pci/pcie/
H A Daspm.c230 struct pci_dev *downstream; /* Downstream component, function 0 */ member
640 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_calc_l12_info()
738 struct pci_dev *child = link->downstream, *parent = link->pdev; in aspm_l1ss_init()
797 struct pci_dev *pdev = link->downstream; in pcie_aspm_override_default_link_state()
816 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_aspm_cap_init()
909 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_l1ss()
950 struct pci_dev *child = link->downstream, *parent = link->pdev; in pcie_config_aspm_link()
1007 pci_save_aspm_l1ss_state(link->downstream); in pcie_config_aspm_link()
1008 pci_update_aspm_saved_state(link->downstream); in pcie_config_aspm_link()
1072 link->downstream = pci_function_0(pdev->subordinate); in alloc_pcie_link_state()
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/linux/Documentation/driver-api/cxl/linux/
H A Dcxl-driver.rst104 only has downstream port connections.
110 contains one or more decoders used to route memory requests downstream ports,
133 * The root has a downstream port connection to a host bridge
137 * The host bridge has one or more downstream port connections to switch
145 upstream and downstream ports.
275 the *immediate downstream targets*, not the entire interleave set.
300 of `Switch Decoder` due to having downstream targets. ::
323 decoder and downstream target ports. Interleaving done within a switch decoder
324 is a multi-downstream-port interleave (or `Intra-Host-Bridge Interleave` for
328 among the *immediate downstream targets*, not the entire interleave set.
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-usb-lvstest16 Set "U1 timeout" for the downstream port where Link Layer
24 Set "U2 timeout" for the downstream port where Link Layer
/linux/arch/arm/boot/dts/st/
H A Dspear1310.dtsi91 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
108 ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */
125 ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */
H A Dspear1340.dtsi56 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm636.dtsi11 * According to the downstream DTS,
H A Dmsm8994-sony-xperia-kitakami.dtsi72 /* This is for getting crash logs using Android downstream kernels */
160 * specific downstream MDSS/backlight nodes in the active DTB.
162 * LK with the downstream DTB appended and then, only from there, load
H A Dmsm8998-oneplus-common.dtsi58 /* For getting crash logs using Android downstream kernels */
69 * The following memory regions on downstream are "dynamically allocated"
/linux/Documentation/admin-guide/perf/
H A Dhisi-pcie-pmu.rst9 all Endpoints downstream these Root Ports.
66 PMU could only monitor the performance of traffic downstream target Root
67 Ports or downstream target Endpoint. PCIe PMU driver support "port" and
/linux/Documentation/i2c/
H A Di2c-address-translators.rst14 ("upstream") port and N I2C master child ("downstream") ports, and
15 forwards transactions from upstream to the appropriate downstream port
/linux/drivers/gpu/drm/msm/
H A DNOTES77 the downstream android fbdev driver), bitfield sizes, etc. My current
85 parse logged register reads/writes (both from downstream android fbdev
/linux/arch/arm/boot/dts/synaptics/
H A Dberlin2cd-valve-steamlink.dts70 /* The SoC is connected to on-board USB hub that in turn has one downstream
/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_detection.c107 struct graphics_object_id downstream) in get_basic_signal_type() argument
109 if (downstream.type == OBJECT_TYPE_CONNECTOR) { in get_basic_signal_type()
110 switch (downstream.id) { in get_basic_signal_type()
153 } else if (downstream.type == OBJECT_TYPE_ENCODER) { in get_basic_signal_type()
154 switch (downstream.id) { in get_basic_signal_type()
/linux/arch/arm/boot/dts/arm/
H A Dversatile-pb.dts54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt189 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
291 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
395 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
491 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
590 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
/linux/Documentation/driver-api/cxl/platform/
H A Dcdat.rst94 Port Y ID : 0000 <- Second port, downstream port 0
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-inventec-transformers.dts320 aspeed,vhub-downstream-ports = <7>;

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