1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright 2023 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __DISPLAY_MODE_CORE_STRUCT_H__ 28 #define __DISPLAY_MODE_CORE_STRUCT_H__ 29 30 #include "display_mode_lib_defines.h" 31 #include "dml_top_display_cfg_types.h" 32 33 enum dml_project_id { 34 dml_project_invalid = 0, 35 dml_project_default = 1, 36 dml_project_dcn32 = dml_project_default, 37 dml_project_dcn321 = 2, 38 dml_project_dcn35 = 3, 39 dml_project_dcn351 = 4, 40 dml_project_dcn401 = 5, 41 }; 42 enum dml_prefetch_modes { 43 dml_prefetch_support_uclk_fclk_and_stutter_if_possible = 0, 44 dml_prefetch_support_uclk_fclk_and_stutter = 1, 45 dml_prefetch_support_fclk_and_stutter = 2, 46 dml_prefetch_support_stutter = 3, 47 dml_prefetch_support_none = 4 48 }; 49 enum dml_use_mall_for_pstate_change_mode { 50 dml_use_mall_pstate_change_disable = 0, 51 dml_use_mall_pstate_change_full_frame = 1, 52 dml_use_mall_pstate_change_sub_viewport = 2, 53 dml_use_mall_pstate_change_phantom_pipe = 3, 54 dml_use_mall_pstate_change_phantom_pipe_no_data_return = 4, 55 dml_use_mall_pstate_change_imall = 5 56 }; 57 enum dml_use_mall_for_static_screen_mode { 58 dml_use_mall_static_screen_disable = 0, 59 dml_use_mall_static_screen_enable = 1, 60 dml_use_mall_static_screen_optimize = 2 61 }; 62 enum dml_output_encoder_class { 63 dml_dp = 0, 64 dml_edp = 1, 65 dml_dp2p0 = 2, 66 dml_hdmi = 3, 67 dml_hdmifrl = 4, 68 dml_none = 5 69 }; 70 enum dml_output_link_dp_rate{ 71 dml_dp_rate_na = 0, 72 dml_dp_rate_hbr = 1, 73 dml_dp_rate_hbr2 = 2, 74 dml_dp_rate_hbr3 = 3, 75 dml_dp_rate_uhbr10 = 4, 76 dml_dp_rate_uhbr13p5 = 5, 77 dml_dp_rate_uhbr20 = 6 78 }; 79 enum dml_output_type_and_rate__type{ 80 dml_output_type_unknown = 0, 81 dml_output_type_dp = 1, 82 dml_output_type_edp = 2, 83 dml_output_type_dp2p0 = 3, 84 dml_output_type_hdmi = 4, 85 dml_output_type_hdmifrl = 5 86 }; 87 enum dml_output_type_and_rate__rate { 88 dml_output_rate_unknown = 0, 89 dml_output_rate_dp_rate_hbr = 1, 90 dml_output_rate_dp_rate_hbr2 = 2, 91 dml_output_rate_dp_rate_hbr3 = 3, 92 dml_output_rate_dp_rate_uhbr10 = 4, 93 dml_output_rate_dp_rate_uhbr13p5 = 5, 94 dml_output_rate_dp_rate_uhbr20 = 6, 95 dml_output_rate_hdmi_rate_3x3 = 7, 96 dml_output_rate_hdmi_rate_6x3 = 8, 97 dml_output_rate_hdmi_rate_6x4 = 9, 98 dml_output_rate_hdmi_rate_8x4 = 10, 99 dml_output_rate_hdmi_rate_10x4 = 11, 100 dml_output_rate_hdmi_rate_12x4 = 12 101 }; 102 enum dml_output_format_class { 103 dml_444 = 0, 104 dml_s422 = 1, 105 dml_n422 = 2, 106 dml_420 = 3 107 }; 108 enum dml_source_format_class { 109 dml_444_8 = 0, 110 dml_444_16 = 1, 111 dml_444_32 = 2, 112 dml_444_64 = 3, 113 dml_420_8 = 4, 114 dml_420_10 = 5, 115 dml_420_12 = 6, 116 dml_422_8 = 7, 117 dml_422_10 = 8, 118 dml_rgbe_alpha = 9, 119 dml_rgbe = 10, 120 dml_mono_8 = 11, 121 dml_mono_16 = 12 122 }; 123 enum dml_output_bpc_class { 124 dml_out_6 = 0, 125 dml_out_8 = 1, 126 dml_out_10 = 2, 127 dml_out_12 = 3, 128 dml_out_16 = 4 129 }; 130 enum dml_output_standard_class { 131 dml_std_cvt = 0, 132 dml_std_cea = 1, 133 dml_std_cvtr2 = 2 134 }; 135 enum dml_rotation_angle { 136 dml_rotation_0 = 0, 137 dml_rotation_90 = 1, 138 dml_rotation_180 = 2, 139 dml_rotation_270 = 3, 140 dml_rotation_0m = 4, 141 dml_rotation_90m = 5, 142 dml_rotation_180m = 6, 143 dml_rotation_270m = 7 144 }; 145 enum dml_swizzle_mode { 146 dml_sw_linear = 0, 147 dml_sw_256b_s = 1, 148 dml_sw_256b_d = 2, 149 dml_sw_256b_r = 3, 150 dml_sw_4kb_z = 4, 151 dml_sw_4kb_s = 5, 152 dml_sw_4kb_d = 6, 153 dml_sw_4kb_r = 7, 154 dml_sw_64kb_z = 8, 155 dml_sw_64kb_s = 9, 156 dml_sw_64kb_d = 10, 157 dml_sw_64kb_r = 11, 158 dml_sw_256kb_z = 12, 159 dml_sw_256kb_s = 13, 160 dml_sw_256kb_d = 14, 161 dml_sw_256kb_r = 15, 162 dml_sw_64kb_z_t = 16, 163 dml_sw_64kb_s_t = 17, 164 dml_sw_64kb_d_t = 18, 165 dml_sw_64kb_r_t = 19, 166 dml_sw_4kb_z_x = 20, 167 dml_sw_4kb_s_x = 21, 168 dml_sw_4kb_d_x = 22, 169 dml_sw_4kb_r_x = 23, 170 dml_sw_64kb_z_x = 24, 171 dml_sw_64kb_s_x = 25, 172 dml_sw_64kb_d_x = 26, 173 dml_sw_64kb_r_x = 27, 174 dml_sw_256kb_z_x = 28, 175 dml_sw_256kb_s_x = 29, 176 dml_sw_256kb_d_x = 30, 177 dml_sw_256kb_r_x = 31, 178 dml_sw_256b_2d = 32, 179 dml_sw_4kb_2d = 33, 180 dml_sw_64kb_2d = 34, 181 dml_sw_256kb_2d = 35 182 }; 183 enum dml_lb_depth { 184 dml_lb_6 = 0, 185 dml_lb_8 = 1, 186 dml_lb_10 = 2, 187 dml_lb_12 = 3, 188 dml_lb_16 = 4 189 }; 190 enum dml_voltage_state { 191 dml_vmin_lv = 0, 192 dml_vmin = 1, 193 dml_vmid = 2, 194 dml_vnom = 3, 195 dml_vmax = 4 196 }; 197 enum dml_source_macro_tile_size { 198 dml_4k_tile = 0, 199 dml_64k_tile = 1, 200 dml_256k_tile = 2 201 }; 202 enum dml_cursor_bpp { 203 dml_cur_2bit = 0, 204 dml_cur_32bit = 1, 205 dml_cur_64bit = 2 206 }; 207 enum dml_dram_clock_change_support { 208 dml_dram_clock_change_vactive = 0, 209 dml_dram_clock_change_vblank = 1, 210 dml_dram_clock_change_vblank_drr = 2, 211 dml_dram_clock_change_vactive_w_mall_full_frame = 3, 212 dml_dram_clock_change_vactive_w_mall_sub_vp = 4, 213 dml_dram_clock_change_vblank_w_mall_full_frame = 5, 214 dml_dram_clock_change_vblank_drr_w_mall_full_frame = 6, 215 dml_dram_clock_change_vblank_w_mall_sub_vp = 7, 216 dml_dram_clock_change_vblank_drr_w_mall_sub_vp = 8, 217 dml_dram_clock_change_unsupported = 9 218 }; 219 enum dml_fclock_change_support { 220 dml_fclock_change_vactive = 0, 221 dml_fclock_change_vblank = 1, 222 dml_fclock_change_unsupported = 2 223 }; 224 enum dml_dsc_enable { 225 dml_dsc_disable = 0, 226 dml_dsc_enable = 1, 227 dml_dsc_enable_if_necessary = 2 228 }; 229 enum dml_mpc_use_policy { 230 dml_mpc_disabled = 0, 231 dml_mpc_as_possible = 1, 232 dml_mpc_as_needed_for_voltage = 2, 233 dml_mpc_as_needed_for_pstate_and_voltage = 3, 234 dml_mpc_as_needed = 4, 235 dml_mpc_2to1 = 5 236 }; 237 enum dml_odm_use_policy { 238 dml_odm_use_policy_bypass = 0, 239 dml_odm_use_policy_combine_as_needed = 1, 240 dml_odm_use_policy_combine_2to1 = 2, 241 dml_odm_use_policy_combine_3to1 = 3, 242 dml_odm_use_policy_combine_4to1 = 4, 243 dml_odm_use_policy_split_1to2 = 5, 244 dml_odm_use_policy_mso_1to2 = 6, 245 dml_odm_use_policy_mso_1to4 = 7 246 }; 247 enum dml_odm_mode { 248 dml_odm_mode_bypass = 0, 249 dml_odm_mode_combine_2to1 = 1, 250 dml_odm_mode_combine_3to1 = 2, 251 dml_odm_mode_combine_4to1 = 3, 252 dml_odm_mode_split_1to2 = 4, 253 dml_odm_mode_mso_1to2 = 5, 254 dml_odm_mode_mso_1to4 = 6 255 }; 256 enum dml_writeback_configuration { 257 dml_whole_buffer_for_single_stream_no_interleave = 0, 258 dml_whole_buffer_for_single_stream_interleave = 1 259 }; 260 enum dml_immediate_flip_requirement { 261 dml_immediate_flip_not_required = 0, 262 dml_immediate_flip_required = 1, 263 dml_immediate_flip_if_possible = 2 264 }; 265 enum dml_unbounded_requesting_policy { 266 dml_unbounded_requesting_enable = 0, 267 dml_unbounded_requesting_edp_only = 1, 268 dml_unbounded_requesting_disable = 2 269 }; 270 enum dml_clk_cfg_policy { 271 dml_use_required_freq = 0, 272 dml_use_override_freq = 1, 273 dml_use_state_freq = 2 274 }; 275 276 277 struct soc_state_bounding_box_st { 278 dml_float_t socclk_mhz; 279 dml_float_t dscclk_mhz; 280 dml_float_t phyclk_mhz; 281 dml_float_t phyclk_d18_mhz; 282 dml_float_t phyclk_d32_mhz; 283 dml_float_t dtbclk_mhz; 284 dml_float_t fabricclk_mhz; 285 dml_float_t dcfclk_mhz; 286 dml_float_t dispclk_mhz; 287 dml_float_t dppclk_mhz; 288 dml_float_t dram_speed_mts; 289 dml_float_t urgent_latency_pixel_data_only_us; 290 dml_float_t urgent_latency_pixel_mixed_with_vm_data_us; 291 dml_float_t urgent_latency_vm_data_only_us; 292 dml_float_t writeback_latency_us; 293 dml_float_t urgent_latency_adjustment_fabric_clock_component_us; 294 dml_float_t urgent_latency_adjustment_fabric_clock_reference_mhz; 295 dml_float_t sr_exit_time_us; 296 dml_float_t sr_enter_plus_exit_time_us; 297 dml_float_t sr_exit_z8_time_us; 298 dml_float_t sr_enter_plus_exit_z8_time_us; 299 dml_float_t dram_clock_change_latency_us; 300 dml_float_t fclk_change_latency_us; 301 dml_float_t usr_retraining_latency_us; 302 dml_bool_t use_ideal_dram_bw_strobe; 303 dml_float_t g6_temp_read_blackout_us; 304 305 struct { 306 dml_uint_t urgent_ramp_uclk_cycles; 307 dml_uint_t trip_to_memory_uclk_cycles; 308 dml_uint_t meta_trip_to_memory_uclk_cycles; 309 dml_uint_t maximum_latency_when_urgent_uclk_cycles; 310 dml_uint_t average_latency_when_urgent_uclk_cycles; 311 dml_uint_t maximum_latency_when_non_urgent_uclk_cycles; 312 dml_uint_t average_latency_when_non_urgent_uclk_cycles; 313 } dml_dcn401_uclk_dpm_dependent_soc_qos_params; 314 }; 315 316 struct soc_bounding_box_st { 317 dml_float_t dprefclk_mhz; 318 dml_float_t xtalclk_mhz; 319 dml_float_t pcierefclk_mhz; 320 dml_float_t refclk_mhz; 321 dml_float_t amclk_mhz; 322 dml_uint_t max_outstanding_reqs; 323 dml_float_t pct_ideal_sdp_bw_after_urgent; 324 dml_float_t pct_ideal_fabric_bw_after_urgent; 325 dml_float_t pct_ideal_dram_bw_after_urgent_pixel_only; 326 dml_float_t pct_ideal_dram_bw_after_urgent_pixel_and_vm; 327 dml_float_t pct_ideal_dram_bw_after_urgent_vm_only; 328 dml_float_t pct_ideal_dram_bw_after_urgent_strobe; 329 dml_float_t max_avg_sdp_bw_use_normal_percent; 330 dml_float_t max_avg_fabric_bw_use_normal_percent; 331 dml_float_t max_avg_dram_bw_use_normal_percent; 332 dml_float_t max_avg_dram_bw_use_normal_strobe_percent; 333 334 dml_float_t svp_prefetch_pct_ideal_sdp_bw_after_urgent; 335 dml_float_t svp_prefetch_pct_ideal_fabric_bw_after_urgent; 336 dml_float_t svp_prefetch_pct_ideal_dram_bw_after_urgent_pixel_only; 337 dml_float_t svp_prefetch_pct_ideal_dram_bw_after_urgent_pixel_and_vm; 338 dml_float_t svp_prefetch_pct_ideal_dram_bw_after_urgent_vm_only; 339 dml_float_t svp_prefetch_max_avg_sdp_bw_use_normal_percent; 340 dml_float_t svp_prefetch_max_avg_fabric_bw_use_normal_percent; 341 dml_float_t svp_prefetch_max_avg_dram_bw_use_normal_percent; 342 343 dml_uint_t round_trip_ping_latency_dcfclk_cycles; 344 dml_uint_t urgent_out_of_order_return_per_channel_pixel_only_bytes; 345 dml_uint_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; 346 dml_uint_t urgent_out_of_order_return_per_channel_vm_only_bytes; 347 dml_uint_t num_chans; 348 dml_uint_t return_bus_width_bytes; 349 dml_uint_t dram_channel_width_bytes; 350 dml_uint_t fabric_datapath_to_dcn_data_return_bytes; 351 dml_uint_t hostvm_min_page_size_kbytes; 352 dml_uint_t gpuvm_min_page_size_kbytes; 353 dml_float_t phy_downspread_percent; 354 dml_float_t dcn_downspread_percent; 355 dml_float_t smn_latency_us; 356 dml_uint_t mall_allocated_for_dcn_mbytes; 357 dml_float_t dispclk_dppclk_vco_speed_mhz; 358 dml_bool_t do_urgent_latency_adjustment; 359 360 dml_uint_t mem_word_bytes; 361 dml_uint_t num_dcc_mcaches; 362 dml_uint_t mcache_size_bytes; 363 dml_uint_t mcache_line_size_bytes; 364 365 struct { 366 dml_bool_t UseNewDCN401SOCParameters; 367 dml_uint_t df_qos_response_time_fclk_cycles; 368 dml_uint_t max_round_trip_to_furthest_cs_fclk_cycles; 369 dml_uint_t mall_overhead_fclk_cycles; 370 dml_uint_t meta_trip_adder_fclk_cycles; 371 dml_uint_t average_transport_distance_fclk_cycles; 372 dml_float_t umc_urgent_ramp_latency_margin; 373 dml_float_t umc_max_latency_margin; 374 dml_float_t umc_average_latency_margin; 375 dml_float_t fabric_max_transport_latency_margin; 376 dml_float_t fabric_average_transport_latency_margin; 377 } dml_dcn401_soc_qos_params; 378 379 }; 380 381 struct ip_params_st { 382 dml_uint_t vblank_nom_default_us; 383 dml_uint_t rob_buffer_size_kbytes; 384 dml_uint_t config_return_buffer_size_in_kbytes; 385 dml_uint_t config_return_buffer_segment_size_in_kbytes; 386 dml_uint_t compressed_buffer_segment_size_in_kbytes; 387 dml_uint_t meta_fifo_size_in_kentries; 388 dml_uint_t zero_size_buffer_entries; 389 dml_uint_t dpte_buffer_size_in_pte_reqs_luma; 390 dml_uint_t dpte_buffer_size_in_pte_reqs_chroma; 391 dml_uint_t dcc_meta_buffer_size_bytes; 392 dml_bool_t gpuvm_enable; 393 dml_bool_t hostvm_enable; 394 dml_uint_t gpuvm_max_page_table_levels; 395 dml_uint_t hostvm_max_page_table_levels; 396 dml_uint_t pixel_chunk_size_kbytes; 397 dml_uint_t alpha_pixel_chunk_size_kbytes; 398 dml_uint_t min_pixel_chunk_size_bytes; 399 dml_uint_t meta_chunk_size_kbytes; 400 dml_uint_t min_meta_chunk_size_bytes; 401 dml_uint_t writeback_chunk_size_kbytes; 402 dml_uint_t line_buffer_size_bits; 403 dml_uint_t max_line_buffer_lines; 404 dml_uint_t writeback_interface_buffer_size_kbytes; 405 dml_uint_t max_num_dpp; 406 dml_uint_t max_num_otg; 407 dml_uint_t max_num_wb; 408 dml_uint_t max_dchub_pscl_bw_pix_per_clk; 409 dml_uint_t max_pscl_lb_bw_pix_per_clk; 410 dml_uint_t max_lb_vscl_bw_pix_per_clk; 411 dml_uint_t max_vscl_hscl_bw_pix_per_clk; 412 dml_float_t max_hscl_ratio; 413 dml_float_t max_vscl_ratio; 414 dml_uint_t max_hscl_taps; 415 dml_uint_t max_vscl_taps; 416 dml_uint_t num_dsc; 417 dml_uint_t maximum_dsc_bits_per_component; 418 dml_uint_t maximum_pixels_per_line_per_dsc_unit; 419 dml_bool_t dsc422_native_support; 420 dml_bool_t cursor_64bpp_support; 421 dml_float_t dispclk_ramp_margin_percent; 422 dml_uint_t dppclk_delay_subtotal; 423 dml_uint_t dppclk_delay_scl; 424 dml_uint_t dppclk_delay_scl_lb_only; 425 dml_uint_t dppclk_delay_cnvc_formatter; 426 dml_uint_t dppclk_delay_cnvc_cursor; 427 dml_uint_t cursor_buffer_size; 428 dml_uint_t cursor_chunk_size; 429 dml_uint_t dispclk_delay_subtotal; 430 dml_bool_t dynamic_metadata_vm_enabled; 431 dml_uint_t max_inter_dcn_tile_repeaters; 432 dml_uint_t max_num_hdmi_frl_outputs; 433 dml_uint_t max_num_dp2p0_outputs; 434 dml_uint_t max_num_dp2p0_streams; 435 dml_bool_t dcc_supported; 436 dml_bool_t ptoi_supported; 437 dml_float_t writeback_max_hscl_ratio; 438 dml_float_t writeback_max_vscl_ratio; 439 dml_float_t writeback_min_hscl_ratio; 440 dml_float_t writeback_min_vscl_ratio; 441 dml_uint_t writeback_max_hscl_taps; 442 dml_uint_t writeback_max_vscl_taps; 443 dml_uint_t writeback_line_buffer_buffer_size; 444 }; 445 446 struct DmlPipe { 447 dml_float_t Dppclk; 448 dml_float_t Dispclk; 449 dml_float_t PixelClock; 450 dml_float_t DCFClkDeepSleep; 451 dml_uint_t DPPPerSurface; 452 dml_bool_t ScalerEnabled; 453 enum dml_rotation_angle SourceScan; 454 dml_uint_t ViewportHeight; 455 dml_uint_t ViewportHeightChroma; 456 dml_uint_t BlockWidth256BytesY; 457 dml_uint_t BlockHeight256BytesY; 458 dml_uint_t BlockWidth256BytesC; 459 dml_uint_t BlockHeight256BytesC; 460 dml_uint_t BlockWidthY; 461 dml_uint_t BlockHeightY; 462 dml_uint_t BlockWidthC; 463 dml_uint_t BlockHeightC; 464 dml_uint_t InterlaceEnable; 465 dml_uint_t NumberOfCursors; 466 dml_uint_t VBlank; 467 dml_uint_t HTotal; 468 dml_uint_t HActive; 469 dml_bool_t DCCEnable; 470 enum dml_odm_mode ODMMode; 471 enum dml_source_format_class SourcePixelFormat; 472 enum dml_swizzle_mode SurfaceTiling; 473 dml_uint_t BytePerPixelY; 474 dml_uint_t BytePerPixelC; 475 dml_bool_t ProgressiveToInterlaceUnitInOPP; 476 dml_float_t VRatio; 477 dml_float_t VRatioChroma; 478 dml_uint_t VTaps; 479 dml_uint_t VTapsChroma; 480 dml_uint_t PitchY; 481 dml_uint_t DCCMetaPitchY; 482 dml_uint_t PitchC; 483 dml_uint_t DCCMetaPitchC; 484 dml_bool_t ViewportStationary; 485 dml_uint_t ViewportXStart; 486 dml_uint_t ViewportYStart; 487 dml_uint_t ViewportXStartC; 488 dml_uint_t ViewportYStartC; 489 dml_bool_t FORCE_ONE_ROW_FOR_FRAME; 490 dml_uint_t SwathHeightY; 491 dml_uint_t SwathHeightC; 492 }; 493 494 struct Watermarks { 495 dml_float_t UrgentWatermark; 496 dml_float_t WritebackUrgentWatermark; 497 dml_float_t DRAMClockChangeWatermark; 498 dml_float_t FCLKChangeWatermark; 499 dml_float_t WritebackDRAMClockChangeWatermark; 500 dml_float_t WritebackFCLKChangeWatermark; 501 dml_float_t StutterExitWatermark; 502 dml_float_t StutterEnterPlusExitWatermark; 503 dml_float_t Z8StutterExitWatermark; 504 dml_float_t Z8StutterEnterPlusExitWatermark; 505 dml_float_t USRRetrainingWatermark; 506 }; 507 508 struct SOCParametersList { 509 dml_float_t UrgentLatency; 510 dml_float_t ExtraLatency; 511 dml_float_t WritebackLatency; 512 dml_float_t DRAMClockChangeLatency; 513 dml_float_t FCLKChangeLatency; 514 dml_float_t SRExitTime; 515 dml_float_t SREnterPlusExitTime; 516 dml_float_t SRExitZ8Time; 517 dml_float_t SREnterPlusExitZ8Time; 518 dml_float_t USRRetrainingLatency; 519 dml_float_t SMNLatency; 520 }; 521 522 /// @brief Struct that represent Plane configration of a display cfg 523 struct dml_plane_cfg_st { 524 // 525 // Pipe/Surface Parameters 526 // 527 dml_bool_t GPUVMEnable; /// <brief Set if any pipe has GPUVM enable 528 dml_bool_t HostVMEnable; /// <brief Set if any pipe has HostVM enable 529 530 dml_uint_t GPUVMMaxPageTableLevels; /// <brief GPUVM level; max of all pipes' 531 dml_uint_t HostVMMaxPageTableLevels; /// <brief HostVM level; max of all pipes'; that is the number of non-cache HVM level 532 533 dml_uint_t GPUVMMinPageSizeKBytes[__DML_NUM_PLANES__]; 534 dml_bool_t ForceOneRowForFrame[__DML_NUM_PLANES__]; 535 dml_bool_t PTEBufferModeOverrideEn[__DML_NUM_PLANES__]; //< brief when override enable; the DML will only check the given pte buffer and will use the pte buffer mode as is 536 dml_bool_t PTEBufferMode[__DML_NUM_PLANES__]; 537 dml_uint_t ViewportWidth[__DML_NUM_PLANES__]; 538 dml_uint_t ViewportHeight[__DML_NUM_PLANES__]; 539 dml_uint_t ViewportWidthChroma[__DML_NUM_PLANES__]; 540 dml_uint_t ViewportHeightChroma[__DML_NUM_PLANES__]; 541 dml_uint_t ViewportXStart[__DML_NUM_PLANES__]; 542 dml_uint_t ViewportXStartC[__DML_NUM_PLANES__]; 543 dml_uint_t ViewportYStart[__DML_NUM_PLANES__]; 544 dml_uint_t ViewportYStartC[__DML_NUM_PLANES__]; 545 dml_bool_t ViewportStationary[__DML_NUM_PLANES__]; 546 547 dml_bool_t ScalerEnabled[__DML_NUM_PLANES__]; 548 dml_float_t HRatio[__DML_NUM_PLANES__]; 549 dml_float_t VRatio[__DML_NUM_PLANES__]; 550 dml_float_t HRatioChroma[__DML_NUM_PLANES__]; 551 dml_float_t VRatioChroma[__DML_NUM_PLANES__]; 552 dml_uint_t HTaps[__DML_NUM_PLANES__]; 553 dml_uint_t VTaps[__DML_NUM_PLANES__]; 554 dml_uint_t HTapsChroma[__DML_NUM_PLANES__]; 555 dml_uint_t VTapsChroma[__DML_NUM_PLANES__]; 556 dml_uint_t LBBitPerPixel[__DML_NUM_PLANES__]; 557 558 enum dml_rotation_angle SourceScan[__DML_NUM_PLANES__]; 559 dml_uint_t ScalerRecoutWidth[__DML_NUM_PLANES__]; 560 561 dml_bool_t DynamicMetadataEnable[__DML_NUM_PLANES__]; 562 dml_uint_t DynamicMetadataLinesBeforeActiveRequired[__DML_NUM_PLANES__]; 563 dml_uint_t DynamicMetadataTransmittedBytes[__DML_NUM_PLANES__]; 564 dml_uint_t DETSizeOverride[__DML_NUM_PLANES__]; /// <brief user can specify the desire DET buffer usage per-plane 565 566 dml_uint_t NumberOfCursors[__DML_NUM_PLANES__]; 567 dml_uint_t CursorWidth[__DML_NUM_PLANES__]; 568 dml_uint_t CursorBPP[__DML_NUM_PLANES__]; 569 570 dml_bool_t setup_for_tdlut[__DML_NUM_PLANES__]; 571 enum dml2_tdlut_addressing_mode tdlut_addressing_mode[__DML_NUM_PLANES__]; 572 enum dml2_tdlut_width_mode tdlut_width_mode[__DML_NUM_PLANES__]; 573 574 enum dml_use_mall_for_static_screen_mode UseMALLForStaticScreen[__DML_NUM_PLANES__]; 575 enum dml_use_mall_for_pstate_change_mode UseMALLForPStateChange[__DML_NUM_PLANES__]; 576 577 dml_uint_t BlendingAndTiming[__DML_NUM_PLANES__]; /// <brief From which timing group (like OTG) that this plane is getting its timing from. Mode check also need this info for example to check num OTG; encoder; dsc etc. 578 }; // dml_plane_cfg_st; 579 580 /// @brief Surface Parameters 581 struct dml_surface_cfg_st { 582 enum dml_swizzle_mode SurfaceTiling[__DML_NUM_PLANES__]; 583 enum dml_source_format_class SourcePixelFormat[__DML_NUM_PLANES__]; 584 dml_uint_t PitchY[__DML_NUM_PLANES__]; 585 dml_uint_t SurfaceWidthY[__DML_NUM_PLANES__]; 586 dml_uint_t SurfaceHeightY[__DML_NUM_PLANES__]; 587 dml_uint_t PitchC[__DML_NUM_PLANES__]; 588 dml_uint_t SurfaceWidthC[__DML_NUM_PLANES__]; 589 dml_uint_t SurfaceHeightC[__DML_NUM_PLANES__]; 590 591 dml_bool_t DCCEnable[__DML_NUM_PLANES__]; 592 dml_uint_t DCCMetaPitchY[__DML_NUM_PLANES__]; 593 dml_uint_t DCCMetaPitchC[__DML_NUM_PLANES__]; 594 595 dml_float_t DCCRateLuma[__DML_NUM_PLANES__]; 596 dml_float_t DCCRateChroma[__DML_NUM_PLANES__]; 597 dml_float_t DCCFractionOfZeroSizeRequestsLuma[__DML_NUM_PLANES__]; 598 dml_float_t DCCFractionOfZeroSizeRequestsChroma[__DML_NUM_PLANES__]; 599 }; // dml_surface_cfg_st 600 601 /// @brief structure that represents the timing configuration 602 struct dml_timing_cfg_st { 603 dml_uint_t HTotal[__DML_NUM_PLANES__]; 604 dml_uint_t VTotal[__DML_NUM_PLANES__]; 605 dml_uint_t HBlankEnd[__DML_NUM_PLANES__]; 606 dml_uint_t VBlankEnd[__DML_NUM_PLANES__]; 607 dml_uint_t RefreshRate[__DML_NUM_PLANES__]; 608 dml_uint_t VFrontPorch[__DML_NUM_PLANES__]; 609 dml_float_t PixelClock[__DML_NUM_PLANES__]; 610 dml_uint_t HActive[__DML_NUM_PLANES__]; 611 dml_uint_t VActive[__DML_NUM_PLANES__]; 612 dml_bool_t Interlace[__DML_NUM_PLANES__]; 613 dml_bool_t DRRDisplay[__DML_NUM_PLANES__]; 614 dml_uint_t VBlankNom[__DML_NUM_PLANES__]; 615 }; // dml_timing_cfg_st; 616 617 /// @brief structure that represents the output stream 618 struct dml_output_cfg_st { 619 // Output Setting 620 dml_uint_t DSCInputBitPerComponent[__DML_NUM_PLANES__]; 621 enum dml_output_format_class OutputFormat[__DML_NUM_PLANES__]; 622 enum dml_output_encoder_class OutputEncoder[__DML_NUM_PLANES__]; 623 dml_uint_t OutputMultistreamId[__DML_NUM_PLANES__]; 624 dml_bool_t OutputMultistreamEn[__DML_NUM_PLANES__]; 625 dml_float_t OutputBpp[__DML_NUM_PLANES__]; //< brief Use by mode_programming to specify a output bpp; user can use the output from mode_support (support.OutputBpp) 626 dml_float_t PixelClockBackEnd[__DML_NUM_PLANES__]; 627 enum dml_dsc_enable DSCEnable[__DML_NUM_PLANES__]; //< brief for mode support check; use to determine if dsc is required 628 dml_uint_t OutputLinkDPLanes[__DML_NUM_PLANES__]; 629 enum dml_output_link_dp_rate OutputLinkDPRate[__DML_NUM_PLANES__]; 630 dml_float_t ForcedOutputLinkBPP[__DML_NUM_PLANES__]; 631 dml_uint_t AudioSampleRate[__DML_NUM_PLANES__]; 632 dml_uint_t AudioSampleLayout[__DML_NUM_PLANES__]; 633 dml_bool_t OutputDisabled[__DML_NUM_PLANES__]; 634 dml_uint_t DSCSlices[__DML_NUM_PLANES__]; 635 }; // dml_timing_cfg_st; 636 637 /// @brief Writeback Setting 638 struct dml_writeback_cfg_st { 639 enum dml_source_format_class WritebackPixelFormat[__DML_NUM_PLANES__]; 640 dml_bool_t WritebackEnable[__DML_NUM_PLANES__]; 641 dml_uint_t ActiveWritebacksPerSurface[__DML_NUM_PLANES__]; 642 dml_uint_t WritebackDestinationWidth[__DML_NUM_PLANES__]; 643 dml_uint_t WritebackDestinationHeight[__DML_NUM_PLANES__]; 644 dml_uint_t WritebackSourceWidth[__DML_NUM_PLANES__]; 645 dml_uint_t WritebackSourceHeight[__DML_NUM_PLANES__]; 646 dml_uint_t WritebackHTaps[__DML_NUM_PLANES__]; 647 dml_uint_t WritebackVTaps[__DML_NUM_PLANES__]; 648 dml_float_t WritebackHRatio[__DML_NUM_PLANES__]; 649 dml_float_t WritebackVRatio[__DML_NUM_PLANES__]; 650 }; // dml_writeback_cfg_st; 651 652 /// @brief Hardware resource specific; mainly used by mode_programming when test/sw wants to do some specific setting 653 /// which are not the same as what the mode support stage derive. When call mode_support with mode_programm; the hw-specific 654 // resource will be set to what the mode_support layer recommends 655 struct dml_hw_resource_st { 656 enum dml_odm_mode ODMMode[__DML_NUM_PLANES__]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage 657 dml_uint_t DPPPerSurface[__DML_NUM_PLANES__]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 658 dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is enabled; used in mode_programming 659 dml_uint_t NumberOfDSCSlices[__DML_NUM_PLANES__]; /// <brief Indicate how many slices needed to support the given mode 660 dml_float_t DLGRefClkFreqMHz; /// <brief DLG Global Reference timer 661 }; 662 663 /// @brief To control the clk usage for model programming 664 struct dml_clk_cfg_st { 665 enum dml_clk_cfg_policy dcfclk_option; ///< brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq 666 enum dml_clk_cfg_policy dispclk_option; ///< brief Use for mode_program; user can select between use the min require clk req as calculated by DML or use the test-specific freq 667 enum dml_clk_cfg_policy dppclk_option[__DML_NUM_PLANES__]; 668 669 dml_float_t dcfclk_mhz; 670 dml_float_t dispclk_mhz; 671 dml_float_t dppclk_mhz[__DML_NUM_PLANES__]; 672 }; // dml_clk_cfg_st 673 674 /// @brief DML display configuration. 675 /// Describe how to display a surface in multi-plane setup and output to different output and writeback using the specified timgin 676 struct dml_display_cfg_st { 677 struct dml_surface_cfg_st surface; 678 struct dml_plane_cfg_st plane; 679 struct dml_timing_cfg_st timing; 680 struct dml_output_cfg_st output; 681 struct dml_writeback_cfg_st writeback; 682 unsigned int num_surfaces; 683 unsigned int num_timings; 684 685 struct dml_hw_resource_st hw; //< brief for mode programming 686 struct dml_clk_cfg_st clk_overrides; //< brief for mode programming clk override 687 }; // dml_display_cfg_st 688 689 /// @brief DML mode evaluation and programming policy 690 /// Those knobs that affect mode support and mode programming 691 struct dml_mode_eval_policy_st { 692 // ------------------- 693 // Policy 694 // ------------------- 695 enum dml_mpc_use_policy MPCCombineUse[__DML_NUM_PLANES__]; /// <brief MPC Combine mode as selected by the user; used in mode check stage 696 enum dml_odm_use_policy ODMUse[__DML_NUM_PLANES__]; /// <brief ODM mode as selected by the user; used in mode check stage 697 enum dml_unbounded_requesting_policy UseUnboundedRequesting; ///< brief Unbounded request mode preference 698 enum dml_immediate_flip_requirement ImmediateFlipRequirement[__DML_NUM_PLANES__]; /// <brief Is immediate flip a requirement for this plane. When host vm is present iflip is needed regardless 699 enum dml_prefetch_modes AllowForPStateChangeOrStutterInVBlank[__DML_NUM_PLANES__]; /// <brief To specify if the DML should calculate the values for support different pwr saving features (cstate; pstate; etc.) during vblank 700 701 enum dml_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; 702 bool UseOnlyMaxPrefetchModes; 703 dml_bool_t UseMinimumRequiredDCFCLK; //<brief When set the mode_check stage will figure the min DCFCLK freq to support the given display configuration. User can tell use the output DCFCLK for mode programming. 704 dml_bool_t DRAMClockChangeRequirementFinal; 705 dml_bool_t FCLKChangeRequirementFinal; 706 dml_bool_t USRRetrainingRequiredFinal; 707 dml_bool_t EnhancedPrefetchScheduleAccelerationFinal; 708 709 dml_bool_t NomDETInKByteOverrideEnable; //<brief Nomimal DET buffer size for a pipe. If this size fit the required 2 swathes; DML will use this DET size 710 dml_uint_t NomDETInKByteOverrideValue; 711 712 dml_bool_t DCCProgrammingAssumesScanDirectionUnknownFinal; 713 dml_bool_t SynchronizeTimingsFinal; 714 dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal; 715 dml_bool_t AssumeModeSupportAtMaxPwrStateEvenDRAMClockChangeNotSupported; //<brief if set; the mode support will say mode is supported even though the DRAM clock change is not support (assuming the soc will be stay in max power state) 716 dml_bool_t AssumeModeSupportAtMaxPwrStateEvenFClockChangeNotSupported; //<brief if set; the mode support will say mode is supported even though the Fabric clock change is not support (assuming the soc will be stay in max power state 717 }; 718 719 /// @brief Contains important information after the mode support steps. Also why a mode is not supported. 720 struct dml_mode_support_info_st { 721 //----------------- 722 // Mode Support Information 723 //----------------- 724 dml_bool_t ModeIsSupported; //<brief Is the mode support any voltage and combine setting 725 dml_bool_t ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming 726 dml_uint_t MaximumMPCCombine; //<brief If using MPC combine helps the power saving support; then this will be set to 1 727 dml_bool_t UnboundedRequestEnabled; 728 dml_uint_t CompressedBufferSizeInkByte; 729 730 /* Mode Support Reason */ 731 dml_bool_t WritebackLatencySupport; 732 dml_bool_t ScaleRatioAndTapsSupport; 733 dml_bool_t SourceFormatPixelAndScanSupport; 734 dml_bool_t MPCCombineMethodIncompatible; 735 dml_bool_t P2IWith420; 736 dml_bool_t DSCOnlyIfNecessaryWithBPP; 737 dml_bool_t DSC422NativeNotSupported; 738 dml_bool_t LinkRateDoesNotMatchDPVersion; 739 dml_bool_t LinkRateForMultistreamNotIndicated; 740 dml_bool_t BPPForMultistreamNotIndicated; 741 dml_bool_t MultistreamWithHDMIOreDP; 742 dml_bool_t MSOOrODMSplitWithNonDPLink; 743 dml_bool_t NotEnoughLanesForMSO; 744 dml_bool_t NumberOfOTGSupport; 745 dml_bool_t NumberOfHDMIFRLSupport; 746 dml_bool_t NumberOfDP2p0Support; 747 dml_bool_t NonsupportedDSCInputBPC; 748 dml_bool_t WritebackScaleRatioAndTapsSupport; 749 dml_bool_t CursorSupport; 750 dml_bool_t PitchSupport; 751 dml_bool_t ViewportExceedsSurface; 752 dml_bool_t ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified; 753 dml_bool_t ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe; 754 dml_bool_t InvalidCombinationOfMALLUseForPStateAndStaticScreen; 755 dml_bool_t InvalidCombinationOfMALLUseForPState; 756 dml_bool_t ExceededMALLSize; 757 dml_bool_t EnoughWritebackUnits; 758 759 dml_bool_t ExceededMultistreamSlots; 760 dml_bool_t ODMCombineTwoToOneSupportCheckOK; 761 dml_bool_t ODMCombineFourToOneSupportCheckOK; 762 dml_bool_t NotEnoughDSCUnits; 763 dml_bool_t NotEnoughDSCSlices; 764 dml_bool_t PixelsPerLinePerDSCUnitSupport; 765 dml_bool_t DSCCLKRequiredMoreThanSupported; 766 dml_bool_t DTBCLKRequiredMoreThanSupported; 767 dml_bool_t LinkCapacitySupport; 768 769 dml_bool_t ROBSupport[2]; 770 dml_bool_t PTEBufferSizeNotExceeded[2]; 771 dml_bool_t DCCMetaBufferSizeNotExceeded[2]; 772 dml_bool_t TotalVerticalActiveBandwidthSupport[2]; 773 enum dml_dram_clock_change_support DRAMClockChangeSupport[2]; 774 dml_float_t ActiveDRAMClockChangeLatencyMargin[__DML_NUM_PLANES__]; 775 dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__]; 776 enum dml_fclock_change_support FCLKChangeSupport[2]; 777 dml_bool_t USRRetrainingSupport[2]; 778 dml_bool_t VActiveBandwithSupport[2]; 779 dml_bool_t PrefetchSupported[2]; 780 dml_bool_t DynamicMetadataSupported[2]; 781 dml_bool_t VRatioInPrefetchSupported[2]; 782 dml_bool_t DISPCLK_DPPCLK_Support[2]; 783 dml_bool_t TotalAvailablePipesSupport[2]; 784 dml_bool_t ModeSupport[2]; 785 dml_bool_t ViewportSizeSupport[2]; 786 dml_bool_t ImmediateFlipSupportedForState[2]; 787 788 dml_bool_t NoTimeForPrefetch[2][__DML_NUM_PLANES__]; 789 dml_bool_t NoTimeForDynamicMetadata[2][__DML_NUM_PLANES__]; 790 791 dml_bool_t MPCCombineEnable[__DML_NUM_PLANES__]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting 792 enum dml_odm_mode ODMMode[__DML_NUM_PLANES__]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage 793 dml_uint_t DPPPerSurface[__DML_NUM_PLANES__]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 794 dml_bool_t DSCEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the DSC is actually required; used in mode_programming 795 dml_bool_t FECEnabled[__DML_NUM_PLANES__]; /// <brief Indicate if the FEC is actually required 796 dml_uint_t NumberOfDSCSlices[__DML_NUM_PLANES__]; /// <brief Indicate how many slices needed to support the given mode 797 798 dml_float_t OutputBpp[__DML_NUM_PLANES__]; 799 enum dml_output_type_and_rate__type OutputType[__DML_NUM_PLANES__]; 800 enum dml_output_type_and_rate__rate OutputRate[__DML_NUM_PLANES__]; 801 802 dml_float_t AlignedDCCMetaPitchY[__DML_NUM_PLANES__]; /// <brief Pitch value that is aligned to tiling setting 803 dml_float_t AlignedDCCMetaPitchC[__DML_NUM_PLANES__]; 804 dml_float_t AlignedYPitch[__DML_NUM_PLANES__]; 805 dml_float_t AlignedCPitch[__DML_NUM_PLANES__]; 806 dml_float_t MaxTotalVerticalActiveAvailableBandwidth[2]; /// <brief nominal bw available for display 807 }; // dml_mode_support_info_st 808 809 /// @brief Treat this as the intermediate values and outputs of mode check function. User can query the content of the struct to know more about the result of mode evaluation. 810 struct mode_support_st { 811 struct ip_params_st ip; 812 struct soc_bounding_box_st soc; 813 struct soc_state_bounding_box_st state; //<brief Per-state bbox values; only 1 state per compute 814 struct dml_mode_eval_policy_st policy; 815 816 dml_uint_t state_idx; //<brief The power state idx for the power state under this computation 817 dml_uint_t max_state_idx; //<brief The MAX power state idx 818 struct soc_state_bounding_box_st max_state; //<brief The MAX power state; some algo needs to know the max state info to determine if 819 struct dml_display_cfg_st cache_display_cfg; // <brief A copy of the current display cfg in consideration 820 821 // Physical info; only using for programming 822 dml_uint_t num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg 823 824 // Calculated Clocks 825 dml_float_t RequiredDISPCLK[2]; /// <brief Required DISPCLK; depends on pixel rate; odm mode etc. 826 dml_float_t RequiredDPPCLKThisState[__DML_NUM_PLANES__]; 827 dml_float_t DCFCLKState[2]; /// <brief recommended DCFCLK freq; calculated by DML. If UseMinimumRequiredDCFCLK is not set; then it will be just the state DCFCLK; else it will min DCFCLK for support 828 dml_float_t RequiredDISPCLKPerSurface[2][__DML_NUM_PLANES__]; 829 dml_float_t RequiredDPPCLKPerSurface[2][__DML_NUM_PLANES__]; 830 831 dml_float_t FabricClock; /// <brief Basically just the clock freq at the min (or given) state 832 dml_float_t DRAMSpeed; /// <brief Basically just the clock freq at the min (or given) state 833 dml_float_t SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 834 dml_float_t DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 835 dml_float_t GlobalDPPCLK; /// <brief the Max DPPCLK freq out of all pipes 836 837 // ---------------------------------- 838 // Mode Support Info and fail reason 839 // ---------------------------------- 840 struct dml_mode_support_info_st support; 841 842 // These are calculated before the ModeSupport and ModeProgram step 843 // They represent the bound for the return buffer sizing 844 dml_uint_t MaxTotalDETInKByte; 845 dml_uint_t NomDETInKByte; 846 dml_uint_t MinCompressedBufferSizeInKByte; 847 848 // Info obtained at the end of mode support calculations 849 // The reported info is at the "optimal" state and combine setting 850 dml_float_t ReturnBW; 851 dml_float_t ReturnDRAMBW; 852 dml_uint_t DETBufferSizeInKByte[__DML_NUM_PLANES__]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 853 dml_uint_t DETBufferSizeY[__DML_NUM_PLANES__]; 854 dml_uint_t DETBufferSizeC[__DML_NUM_PLANES__]; 855 dml_uint_t SwathHeightY[__DML_NUM_PLANES__]; 856 dml_uint_t SwathHeightC[__DML_NUM_PLANES__]; 857 858 // ---------------------------------- 859 // Intermediates/Informational 860 // ---------------------------------- 861 dml_uint_t TotImmediateFlipBytes; 862 dml_bool_t DCCEnabledInAnySurface; 863 dml_float_t WritebackRequiredDISPCLK; 864 dml_float_t TimeCalc; 865 dml_float_t TWait; 866 867 dml_uint_t SwathWidthYAllStates[2][__DML_NUM_PLANES__]; 868 dml_uint_t SwathWidthCAllStates[2][__DML_NUM_PLANES__]; 869 dml_uint_t SwathHeightYAllStates[2][__DML_NUM_PLANES__]; 870 dml_uint_t SwathHeightCAllStates[2][__DML_NUM_PLANES__]; 871 dml_uint_t SwathWidthYThisState[__DML_NUM_PLANES__]; 872 dml_uint_t SwathWidthCThisState[__DML_NUM_PLANES__]; 873 dml_uint_t SwathHeightYThisState[__DML_NUM_PLANES__]; 874 dml_uint_t SwathHeightCThisState[__DML_NUM_PLANES__]; 875 dml_uint_t DETBufferSizeInKByteAllStates[2][__DML_NUM_PLANES__]; 876 dml_uint_t DETBufferSizeYAllStates[2][__DML_NUM_PLANES__]; 877 dml_uint_t DETBufferSizeCAllStates[2][__DML_NUM_PLANES__]; 878 dml_bool_t UnboundedRequestEnabledAllStates[2]; 879 dml_uint_t CompressedBufferSizeInkByteAllStates[2]; 880 dml_bool_t UnboundedRequestEnabledThisState; 881 dml_uint_t CompressedBufferSizeInkByteThisState; 882 dml_uint_t DETBufferSizeInKByteThisState[__DML_NUM_PLANES__]; 883 dml_uint_t DETBufferSizeYThisState[__DML_NUM_PLANES__]; 884 dml_uint_t DETBufferSizeCThisState[__DML_NUM_PLANES__]; 885 dml_float_t VRatioPreY[2][__DML_NUM_PLANES__]; 886 dml_float_t VRatioPreC[2][__DML_NUM_PLANES__]; 887 dml_uint_t swath_width_luma_ub_all_states[2][__DML_NUM_PLANES__]; 888 dml_uint_t swath_width_chroma_ub_all_states[2][__DML_NUM_PLANES__]; 889 dml_uint_t swath_width_luma_ub_this_state[__DML_NUM_PLANES__]; 890 dml_uint_t swath_width_chroma_ub_this_state[__DML_NUM_PLANES__]; 891 dml_uint_t RequiredSlots[__DML_NUM_PLANES__]; 892 dml_uint_t PDEAndMetaPTEBytesPerFrame[2][__DML_NUM_PLANES__]; 893 dml_uint_t MetaRowBytes[2][__DML_NUM_PLANES__]; 894 dml_uint_t DPTEBytesPerRow[2][__DML_NUM_PLANES__]; 895 dml_uint_t PrefetchLinesY[2][__DML_NUM_PLANES__]; 896 dml_uint_t PrefetchLinesC[2][__DML_NUM_PLANES__]; 897 dml_uint_t MaxNumSwY[__DML_NUM_PLANES__]; /// <brief Max number of swath for prefetch 898 dml_uint_t MaxNumSwC[__DML_NUM_PLANES__]; /// <brief Max number of swath for prefetch 899 dml_uint_t PrefillY[__DML_NUM_PLANES__]; 900 dml_uint_t PrefillC[__DML_NUM_PLANES__]; 901 902 dml_uint_t PrefetchLinesYThisState[__DML_NUM_PLANES__]; 903 dml_uint_t PrefetchLinesCThisState[__DML_NUM_PLANES__]; 904 dml_uint_t DPTEBytesPerRowThisState[__DML_NUM_PLANES__]; 905 dml_uint_t PDEAndMetaPTEBytesPerFrameThisState[__DML_NUM_PLANES__]; 906 dml_uint_t MetaRowBytesThisState[__DML_NUM_PLANES__]; 907 dml_bool_t use_one_row_for_frame[2][__DML_NUM_PLANES__]; 908 dml_bool_t use_one_row_for_frame_flip[2][__DML_NUM_PLANES__]; 909 dml_bool_t use_one_row_for_frame_this_state[__DML_NUM_PLANES__]; 910 dml_bool_t use_one_row_for_frame_flip_this_state[__DML_NUM_PLANES__]; 911 912 dml_float_t LineTimesForPrefetch[__DML_NUM_PLANES__]; 913 dml_float_t LinesForMetaPTE[__DML_NUM_PLANES__]; 914 dml_float_t LinesForMetaAndDPTERow[__DML_NUM_PLANES__]; 915 dml_float_t SwathWidthYSingleDPP[__DML_NUM_PLANES__]; 916 dml_float_t SwathWidthCSingleDPP[__DML_NUM_PLANES__]; 917 dml_uint_t BytePerPixelY[__DML_NUM_PLANES__]; 918 dml_uint_t BytePerPixelC[__DML_NUM_PLANES__]; 919 dml_float_t BytePerPixelInDETY[__DML_NUM_PLANES__]; 920 dml_float_t BytePerPixelInDETC[__DML_NUM_PLANES__]; 921 922 dml_uint_t Read256BlockHeightY[__DML_NUM_PLANES__]; 923 dml_uint_t Read256BlockWidthY[__DML_NUM_PLANES__]; 924 dml_uint_t Read256BlockHeightC[__DML_NUM_PLANES__]; 925 dml_uint_t Read256BlockWidthC[__DML_NUM_PLANES__]; 926 dml_uint_t MacroTileHeightY[__DML_NUM_PLANES__]; 927 dml_uint_t MacroTileHeightC[__DML_NUM_PLANES__]; 928 dml_uint_t MacroTileWidthY[__DML_NUM_PLANES__]; 929 dml_uint_t MacroTileWidthC[__DML_NUM_PLANES__]; 930 dml_float_t PSCL_FACTOR[__DML_NUM_PLANES__]; 931 dml_float_t PSCL_FACTOR_CHROMA[__DML_NUM_PLANES__]; 932 dml_float_t MaximumSwathWidthLuma[__DML_NUM_PLANES__]; 933 dml_float_t MaximumSwathWidthChroma[__DML_NUM_PLANES__]; 934 dml_float_t Tno_bw[__DML_NUM_PLANES__]; 935 dml_float_t DestinationLinesToRequestVMInImmediateFlip[__DML_NUM_PLANES__]; 936 dml_float_t DestinationLinesToRequestRowInImmediateFlip[__DML_NUM_PLANES__]; 937 dml_float_t WritebackDelayTime[__DML_NUM_PLANES__]; 938 dml_uint_t dpte_group_bytes[__DML_NUM_PLANES__]; 939 dml_uint_t dpte_row_height[__DML_NUM_PLANES__]; 940 dml_uint_t dpte_row_height_chroma[__DML_NUM_PLANES__]; 941 dml_uint_t meta_row_height[__DML_NUM_PLANES__]; 942 dml_uint_t meta_row_height_chroma[__DML_NUM_PLANES__]; 943 dml_float_t UrgLatency; 944 dml_float_t UrgentBurstFactorCursor[2][__DML_NUM_PLANES__]; 945 dml_float_t UrgentBurstFactorCursorPre[__DML_NUM_PLANES__]; 946 dml_float_t UrgentBurstFactorLuma[2][__DML_NUM_PLANES__]; 947 dml_float_t UrgentBurstFactorLumaPre[__DML_NUM_PLANES__]; 948 dml_float_t UrgentBurstFactorChroma[2][__DML_NUM_PLANES__]; 949 dml_float_t UrgentBurstFactorChromaPre[__DML_NUM_PLANES__]; 950 dml_float_t MaximumSwathWidthInLineBufferLuma; 951 dml_float_t MaximumSwathWidthInLineBufferChroma; 952 dml_float_t ExtraLatency; 953 954 // Backend 955 dml_bool_t RequiresDSC[__DML_NUM_PLANES__]; 956 dml_bool_t RequiresFEC[__DML_NUM_PLANES__]; 957 dml_float_t OutputBppPerState[__DML_NUM_PLANES__]; 958 dml_uint_t DSCDelayPerState[__DML_NUM_PLANES__]; 959 enum dml_output_type_and_rate__type OutputTypePerState[__DML_NUM_PLANES__]; 960 enum dml_output_type_and_rate__rate OutputRatePerState[__DML_NUM_PLANES__]; 961 962 // Bandwidth Related Info 963 dml_float_t BandwidthAvailableForImmediateFlip; 964 dml_float_t ReadBandwidthLuma[__DML_NUM_PLANES__]; 965 dml_float_t ReadBandwidthChroma[__DML_NUM_PLANES__]; 966 dml_float_t WriteBandwidth[__DML_NUM_PLANES__]; 967 dml_float_t RequiredPrefetchPixelDataBWLuma[__DML_NUM_PLANES__]; 968 dml_float_t RequiredPrefetchPixelDataBWChroma[__DML_NUM_PLANES__]; 969 dml_float_t cursor_bw[__DML_NUM_PLANES__]; 970 dml_float_t cursor_bw_pre[__DML_NUM_PLANES__]; 971 dml_float_t prefetch_vmrow_bw[__DML_NUM_PLANES__]; 972 dml_float_t final_flip_bw[__DML_NUM_PLANES__]; 973 dml_float_t meta_row_bandwidth_this_state[__DML_NUM_PLANES__]; 974 dml_float_t dpte_row_bandwidth_this_state[__DML_NUM_PLANES__]; 975 dml_float_t ReturnBWPerState[2]; 976 dml_float_t ReturnDRAMBWPerState[2]; 977 dml_float_t meta_row_bandwidth[2][__DML_NUM_PLANES__]; 978 dml_float_t dpte_row_bandwidth[2][__DML_NUM_PLANES__]; 979 980 // Something that should be feedback to caller 981 enum dml_odm_mode ODMModePerState[__DML_NUM_PLANES__]; 982 enum dml_odm_mode ODMModeThisState[__DML_NUM_PLANES__]; 983 dml_uint_t SurfaceSizeInMALL[__DML_NUM_PLANES__]; 984 dml_uint_t NoOfDPP[2][__DML_NUM_PLANES__]; 985 dml_uint_t NoOfDPPThisState[__DML_NUM_PLANES__]; 986 dml_bool_t MPCCombine[2][__DML_NUM_PLANES__]; 987 dml_bool_t MPCCombineThisState[__DML_NUM_PLANES__]; 988 dml_float_t ProjectedDCFCLKDeepSleep[2]; 989 dml_float_t MinDPPCLKUsingSingleDPP[__DML_NUM_PLANES__]; 990 dml_bool_t SingleDPPViewportSizeSupportPerSurface[__DML_NUM_PLANES__]; 991 dml_bool_t ImmediateFlipSupportedForPipe[__DML_NUM_PLANES__]; 992 dml_bool_t NotUrgentLatencyHiding[__DML_NUM_PLANES__]; 993 dml_bool_t NotUrgentLatencyHidingPre[__DML_NUM_PLANES__]; 994 dml_bool_t PTEBufferSizeNotExceededPerState[__DML_NUM_PLANES__]; 995 dml_bool_t DCCMetaBufferSizeNotExceededPerState[__DML_NUM_PLANES__]; 996 dml_uint_t PrefetchMode[__DML_NUM_PLANES__]; 997 dml_uint_t TotalNumberOfActiveDPP[2]; 998 dml_uint_t TotalNumberOfSingleDPPSurfaces[2]; 999 dml_uint_t TotalNumberOfDCCActiveDPP[2]; 1000 1001 dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__]; 1002 1003 }; // mode_support_st 1004 1005 /// @brief A mega structure that houses various info for model programming step. 1006 struct mode_program_st { 1007 1008 //------------- 1009 // Intermediate/Informational 1010 //------------- 1011 dml_float_t UrgentLatency; 1012 dml_float_t UrgentLatencyWithUSRRetraining; 1013 dml_uint_t VInitPreFillY[__DML_NUM_PLANES__]; 1014 dml_uint_t VInitPreFillC[__DML_NUM_PLANES__]; 1015 dml_uint_t MaxNumSwathY[__DML_NUM_PLANES__]; 1016 dml_uint_t MaxNumSwathC[__DML_NUM_PLANES__]; 1017 1018 dml_float_t BytePerPixelDETY[__DML_NUM_PLANES__]; 1019 dml_float_t BytePerPixelDETC[__DML_NUM_PLANES__]; 1020 dml_uint_t BytePerPixelY[__DML_NUM_PLANES__]; 1021 dml_uint_t BytePerPixelC[__DML_NUM_PLANES__]; 1022 dml_uint_t SwathWidthY[__DML_NUM_PLANES__]; 1023 dml_uint_t SwathWidthC[__DML_NUM_PLANES__]; 1024 dml_uint_t SwathWidthSingleDPPY[__DML_NUM_PLANES__]; 1025 dml_uint_t SwathWidthSingleDPPC[__DML_NUM_PLANES__]; 1026 dml_float_t ReadBandwidthSurfaceLuma[__DML_NUM_PLANES__]; 1027 dml_float_t ReadBandwidthSurfaceChroma[__DML_NUM_PLANES__]; 1028 1029 dml_uint_t PixelPTEBytesPerRow[__DML_NUM_PLANES__]; 1030 dml_uint_t PDEAndMetaPTEBytesFrame[__DML_NUM_PLANES__]; 1031 dml_uint_t MetaRowByte[__DML_NUM_PLANES__]; 1032 dml_uint_t PrefetchSourceLinesY[__DML_NUM_PLANES__]; 1033 dml_float_t RequiredPrefetchPixDataBWLuma[__DML_NUM_PLANES__]; 1034 dml_float_t RequiredPrefetchPixDataBWChroma[__DML_NUM_PLANES__]; 1035 dml_uint_t PrefetchSourceLinesC[__DML_NUM_PLANES__]; 1036 dml_float_t PSCL_THROUGHPUT[__DML_NUM_PLANES__]; 1037 dml_float_t PSCL_THROUGHPUT_CHROMA[__DML_NUM_PLANES__]; 1038 dml_uint_t DSCDelay[__DML_NUM_PLANES__]; 1039 dml_float_t DPPCLKUsingSingleDPP[__DML_NUM_PLANES__]; 1040 1041 dml_uint_t MacroTileWidthY[__DML_NUM_PLANES__]; 1042 dml_uint_t MacroTileWidthC[__DML_NUM_PLANES__]; 1043 dml_uint_t BlockHeight256BytesY[__DML_NUM_PLANES__]; 1044 dml_uint_t BlockHeight256BytesC[__DML_NUM_PLANES__]; 1045 dml_uint_t BlockWidth256BytesY[__DML_NUM_PLANES__]; 1046 dml_uint_t BlockWidth256BytesC[__DML_NUM_PLANES__]; 1047 1048 dml_uint_t BlockHeightY[__DML_NUM_PLANES__]; 1049 dml_uint_t BlockHeightC[__DML_NUM_PLANES__]; 1050 dml_uint_t BlockWidthY[__DML_NUM_PLANES__]; 1051 dml_uint_t BlockWidthC[__DML_NUM_PLANES__]; 1052 1053 dml_uint_t SurfaceSizeInTheMALL[__DML_NUM_PLANES__]; 1054 dml_float_t VRatioPrefetchY[__DML_NUM_PLANES__]; 1055 dml_float_t VRatioPrefetchC[__DML_NUM_PLANES__]; 1056 dml_float_t Tno_bw[__DML_NUM_PLANES__]; 1057 dml_float_t final_flip_bw[__DML_NUM_PLANES__]; 1058 dml_float_t prefetch_vmrow_bw[__DML_NUM_PLANES__]; 1059 dml_float_t cursor_bw[__DML_NUM_PLANES__]; 1060 dml_float_t cursor_bw_pre[__DML_NUM_PLANES__]; 1061 dml_float_t WritebackDelay[__DML_NUM_PLANES__]; 1062 dml_uint_t dpte_row_height[__DML_NUM_PLANES__]; 1063 dml_uint_t dpte_row_height_linear[__DML_NUM_PLANES__]; 1064 dml_uint_t meta_req_width[__DML_NUM_PLANES__]; 1065 dml_uint_t meta_req_height[__DML_NUM_PLANES__]; 1066 dml_uint_t meta_row_width[__DML_NUM_PLANES__]; 1067 dml_uint_t meta_row_height[__DML_NUM_PLANES__]; 1068 dml_uint_t dpte_row_width_luma_ub[__DML_NUM_PLANES__]; 1069 dml_uint_t dpte_row_width_chroma_ub[__DML_NUM_PLANES__]; 1070 dml_uint_t dpte_row_height_chroma[__DML_NUM_PLANES__]; 1071 dml_uint_t dpte_row_height_linear_chroma[__DML_NUM_PLANES__]; 1072 dml_uint_t meta_req_width_chroma[__DML_NUM_PLANES__]; 1073 dml_uint_t meta_req_height_chroma[__DML_NUM_PLANES__]; 1074 dml_uint_t meta_row_width_chroma[__DML_NUM_PLANES__]; 1075 dml_uint_t meta_row_height_chroma[__DML_NUM_PLANES__]; 1076 dml_uint_t vm_group_bytes[__DML_NUM_PLANES__]; 1077 dml_uint_t dpte_group_bytes[__DML_NUM_PLANES__]; 1078 dml_float_t meta_row_bw[__DML_NUM_PLANES__]; 1079 dml_float_t dpte_row_bw[__DML_NUM_PLANES__]; 1080 dml_float_t UrgBurstFactorCursor[__DML_NUM_PLANES__]; 1081 dml_float_t UrgBurstFactorCursorPre[__DML_NUM_PLANES__]; 1082 dml_float_t UrgBurstFactorLuma[__DML_NUM_PLANES__]; 1083 dml_float_t UrgBurstFactorLumaPre[__DML_NUM_PLANES__]; 1084 dml_float_t UrgBurstFactorChroma[__DML_NUM_PLANES__]; 1085 dml_float_t UrgBurstFactorChromaPre[__DML_NUM_PLANES__]; 1086 1087 dml_uint_t swath_width_luma_ub[__DML_NUM_PLANES__]; 1088 dml_uint_t swath_width_chroma_ub[__DML_NUM_PLANES__]; 1089 dml_uint_t PixelPTEReqWidthY[__DML_NUM_PLANES__]; 1090 dml_uint_t PixelPTEReqHeightY[__DML_NUM_PLANES__]; 1091 dml_uint_t PTERequestSizeY[__DML_NUM_PLANES__]; 1092 dml_uint_t PixelPTEReqWidthC[__DML_NUM_PLANES__]; 1093 dml_uint_t PixelPTEReqHeightC[__DML_NUM_PLANES__]; 1094 dml_uint_t PTERequestSizeC[__DML_NUM_PLANES__]; 1095 1096 dml_float_t Tdmdl_vm[__DML_NUM_PLANES__]; 1097 dml_float_t Tdmdl[__DML_NUM_PLANES__]; 1098 dml_float_t TSetup[__DML_NUM_PLANES__]; 1099 dml_uint_t dpde0_bytes_per_frame_ub_l[__DML_NUM_PLANES__]; 1100 dml_uint_t meta_pte_bytes_per_frame_ub_l[__DML_NUM_PLANES__]; 1101 dml_uint_t dpde0_bytes_per_frame_ub_c[__DML_NUM_PLANES__]; 1102 dml_uint_t meta_pte_bytes_per_frame_ub_c[__DML_NUM_PLANES__]; 1103 1104 dml_bool_t UnboundedRequestEnabled; 1105 dml_uint_t compbuf_reserved_space_64b; 1106 dml_uint_t compbuf_reserved_space_zs; 1107 dml_uint_t CompressedBufferSizeInkByte; 1108 1109 dml_bool_t NoUrgentLatencyHiding[__DML_NUM_PLANES__]; 1110 dml_bool_t NoUrgentLatencyHidingPre[__DML_NUM_PLANES__]; 1111 dml_float_t UrgentExtraLatency; 1112 dml_bool_t PrefetchAndImmediateFlipSupported; 1113 dml_float_t TotalDataReadBandwidth; 1114 dml_float_t BandwidthAvailableForImmediateFlip; 1115 dml_bool_t NotEnoughTimeForDynamicMetadata[__DML_NUM_PLANES__]; 1116 1117 dml_float_t ReadBandwidthLuma[__DML_NUM_PLANES__]; 1118 dml_float_t ReadBandwidthChroma[__DML_NUM_PLANES__]; 1119 1120 dml_float_t total_dcn_read_bw_with_flip; 1121 dml_float_t total_dcn_read_bw_with_flip_no_urgent_burst; 1122 dml_float_t TotalDataReadBandwidthNotIncludingMALLPrefetch; 1123 dml_float_t total_dcn_read_bw_with_flip_not_including_MALL_prefetch; 1124 dml_float_t non_urgent_total_dcn_read_bw_with_flip; 1125 dml_float_t non_urgent_total_dcn_read_bw_with_flip_not_including_MALL_prefetch; 1126 1127 dml_bool_t use_one_row_for_frame[__DML_NUM_PLANES__]; 1128 dml_bool_t use_one_row_for_frame_flip[__DML_NUM_PLANES__]; 1129 1130 dml_float_t TCalc; 1131 dml_uint_t TotImmediateFlipBytes; 1132 1133 // ------------------- 1134 // Output 1135 // ------------------- 1136 dml_uint_t pipe_plane[__DML_NUM_PLANES__]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe 1137 dml_uint_t num_active_pipes; 1138 1139 dml_bool_t NoTimeToPrefetch[__DML_NUM_PLANES__]; /// <brief Prefetch schedule calculation result 1140 1141 // Support 1142 dml_uint_t PrefetchMode[__DML_NUM_PLANES__]; /// <brief prefetch mode used for prefetch support check in mode programming step 1143 dml_bool_t PrefetchModeSupported; /// <brief Is the prefetch mode (bandwidth and latency) supported 1144 dml_bool_t ImmediateFlipSupported; 1145 dml_bool_t ImmediateFlipSupportedForPipe[__DML_NUM_PLANES__]; 1146 1147 // Clock 1148 dml_float_t Dcfclk; 1149 dml_float_t Dispclk; /// <brief dispclk being used in mode programming 1150 dml_float_t Dppclk[__DML_NUM_PLANES__]; /// <brief dppclk being used in mode programming 1151 dml_float_t WritebackDISPCLK; 1152 dml_float_t GlobalDPPCLK; 1153 1154 //@ brief These "calculated" dispclk and dppclk clocks are calculated in the mode programming step. 1155 // Depends on the dml_clk_cfg_st option; these calculated values may not used in subsequent calculation. 1156 // Possible DV usage: Calculated values fetched by test once after mode_programming step and then possibly 1157 // use the values as min and adjust the actual freq used for the 2nd pass 1158 dml_float_t Dispclk_calculated; 1159 dml_float_t Dppclk_calculated[__DML_NUM_PLANES__]; 1160 1161 dml_float_t DSCCLK_calculated[__DML_NUM_PLANES__]; //< brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now 1162 dml_float_t DCFCLKDeepSleep; 1163 1164 // ARB reg 1165 dml_bool_t DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 1166 struct Watermarks Watermark; 1167 1168 // DCC compression control 1169 dml_uint_t DCCYMaxUncompressedBlock[__DML_NUM_PLANES__]; 1170 dml_uint_t DCCYMaxCompressedBlock[__DML_NUM_PLANES__]; 1171 dml_uint_t DCCYIndependentBlock[__DML_NUM_PLANES__]; 1172 dml_uint_t DCCCMaxUncompressedBlock[__DML_NUM_PLANES__]; 1173 dml_uint_t DCCCMaxCompressedBlock[__DML_NUM_PLANES__]; 1174 dml_uint_t DCCCIndependentBlock[__DML_NUM_PLANES__]; 1175 1176 // Stutter Efficiency 1177 dml_float_t StutterEfficiency; 1178 dml_float_t StutterEfficiencyNotIncludingVBlank; 1179 dml_uint_t NumberOfStutterBurstsPerFrame; 1180 dml_float_t Z8StutterEfficiency; 1181 dml_uint_t Z8NumberOfStutterBurstsPerFrame; 1182 dml_float_t Z8StutterEfficiencyNotIncludingVBlank; 1183 dml_float_t StutterPeriod; 1184 dml_float_t Z8StutterEfficiencyBestCase; 1185 dml_uint_t Z8NumberOfStutterBurstsPerFrameBestCase; 1186 dml_float_t Z8StutterEfficiencyNotIncludingVBlankBestCase; 1187 dml_float_t StutterPeriodBestCase; 1188 1189 // DLG TTU reg 1190 dml_float_t MIN_DST_Y_NEXT_START[__DML_NUM_PLANES__]; 1191 dml_bool_t VREADY_AT_OR_AFTER_VSYNC[__DML_NUM_PLANES__]; 1192 dml_uint_t DSTYAfterScaler[__DML_NUM_PLANES__]; 1193 dml_uint_t DSTXAfterScaler[__DML_NUM_PLANES__]; 1194 dml_float_t DestinationLinesForPrefetch[__DML_NUM_PLANES__]; 1195 dml_float_t DestinationLinesToRequestVMInVBlank[__DML_NUM_PLANES__]; 1196 dml_float_t DestinationLinesToRequestRowInVBlank[__DML_NUM_PLANES__]; 1197 dml_float_t DestinationLinesToRequestVMInImmediateFlip[__DML_NUM_PLANES__]; 1198 dml_float_t DestinationLinesToRequestRowInImmediateFlip[__DML_NUM_PLANES__]; 1199 dml_float_t MinTTUVBlank[__DML_NUM_PLANES__]; 1200 dml_float_t DisplayPipeLineDeliveryTimeLuma[__DML_NUM_PLANES__]; 1201 dml_float_t DisplayPipeLineDeliveryTimeChroma[__DML_NUM_PLANES__]; 1202 dml_float_t DisplayPipeLineDeliveryTimeLumaPrefetch[__DML_NUM_PLANES__]; 1203 dml_float_t DisplayPipeLineDeliveryTimeChromaPrefetch[__DML_NUM_PLANES__]; 1204 dml_float_t DisplayPipeRequestDeliveryTimeLuma[__DML_NUM_PLANES__]; 1205 dml_float_t DisplayPipeRequestDeliveryTimeChroma[__DML_NUM_PLANES__]; 1206 dml_float_t DisplayPipeRequestDeliveryTimeLumaPrefetch[__DML_NUM_PLANES__]; 1207 dml_float_t DisplayPipeRequestDeliveryTimeChromaPrefetch[__DML_NUM_PLANES__]; 1208 dml_float_t CursorRequestDeliveryTime[__DML_NUM_PLANES__]; 1209 dml_float_t CursorRequestDeliveryTimePrefetch[__DML_NUM_PLANES__]; 1210 1211 dml_float_t DST_Y_PER_PTE_ROW_NOM_L[__DML_NUM_PLANES__]; 1212 dml_float_t DST_Y_PER_PTE_ROW_NOM_C[__DML_NUM_PLANES__]; 1213 dml_float_t DST_Y_PER_META_ROW_NOM_L[__DML_NUM_PLANES__]; 1214 dml_float_t DST_Y_PER_META_ROW_NOM_C[__DML_NUM_PLANES__]; 1215 dml_float_t TimePerMetaChunkNominal[__DML_NUM_PLANES__]; 1216 dml_float_t TimePerChromaMetaChunkNominal[__DML_NUM_PLANES__]; 1217 dml_float_t TimePerMetaChunkVBlank[__DML_NUM_PLANES__]; 1218 dml_float_t TimePerChromaMetaChunkVBlank[__DML_NUM_PLANES__]; 1219 dml_float_t TimePerMetaChunkFlip[__DML_NUM_PLANES__]; 1220 dml_float_t TimePerChromaMetaChunkFlip[__DML_NUM_PLANES__]; 1221 dml_float_t time_per_pte_group_nom_luma[__DML_NUM_PLANES__]; 1222 dml_float_t time_per_pte_group_nom_chroma[__DML_NUM_PLANES__]; 1223 dml_float_t time_per_pte_group_vblank_luma[__DML_NUM_PLANES__]; 1224 dml_float_t time_per_pte_group_vblank_chroma[__DML_NUM_PLANES__]; 1225 dml_float_t time_per_pte_group_flip_luma[__DML_NUM_PLANES__]; 1226 dml_float_t time_per_pte_group_flip_chroma[__DML_NUM_PLANES__]; 1227 dml_float_t TimePerVMGroupVBlank[__DML_NUM_PLANES__]; 1228 dml_float_t TimePerVMGroupFlip[__DML_NUM_PLANES__]; 1229 dml_float_t TimePerVMRequestVBlank[__DML_NUM_PLANES__]; 1230 dml_float_t TimePerVMRequestFlip[__DML_NUM_PLANES__]; 1231 1232 dml_float_t FractionOfUrgentBandwidth; 1233 dml_float_t FractionOfUrgentBandwidthImmediateFlip; 1234 1235 // RQ registers 1236 dml_bool_t PTE_BUFFER_MODE[__DML_NUM_PLANES__]; 1237 dml_uint_t BIGK_FRAGMENT_SIZE[__DML_NUM_PLANES__]; 1238 1239 dml_uint_t SubViewportLinesNeededInMALL[__DML_NUM_PLANES__]; 1240 dml_bool_t UsesMALLForStaticScreen[__DML_NUM_PLANES__]; 1241 1242 // OTG 1243 dml_uint_t VStartupMin[__DML_NUM_PLANES__]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos. 1244 dml_uint_t VStartup[__DML_NUM_PLANES__]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank)) 1245 dml_uint_t VUpdateOffsetPix[__DML_NUM_PLANES__]; 1246 dml_uint_t VUpdateWidthPix[__DML_NUM_PLANES__]; 1247 dml_uint_t VReadyOffsetPix[__DML_NUM_PLANES__]; 1248 1249 // Latency and Support 1250 dml_float_t MaxActiveFCLKChangeLatencySupported; 1251 dml_bool_t USRRetrainingSupport; 1252 enum dml_fclock_change_support FCLKChangeSupport; 1253 enum dml_dram_clock_change_support DRAMClockChangeSupport; 1254 dml_float_t MaxActiveDRAMClockChangeLatencySupported[__DML_NUM_PLANES__]; 1255 dml_float_t WritebackAllowFCLKChangeEndPosition[__DML_NUM_PLANES__]; 1256 dml_float_t WritebackAllowDRAMClockChangeEndPosition[__DML_NUM_PLANES__]; 1257 1258 // buffer sizing 1259 dml_uint_t DETBufferSizeInKByte[__DML_NUM_PLANES__]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 1260 dml_uint_t DETBufferSizeY[__DML_NUM_PLANES__]; 1261 dml_uint_t DETBufferSizeC[__DML_NUM_PLANES__]; 1262 dml_uint_t SwathHeightY[__DML_NUM_PLANES__]; 1263 dml_uint_t SwathHeightC[__DML_NUM_PLANES__]; 1264 }; // mode_program_st 1265 1266 struct soc_states_st { 1267 dml_uint_t num_states; /// <brief num of soc pwr states 1268 struct soc_state_bounding_box_st state_array[__DML_MAX_STATE_ARRAY_SIZE__]; /// <brief fixed size array that holds states struct 1269 }; 1270 1271 struct UseMinimumDCFCLK_params_st { 1272 enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange; 1273 dml_bool_t *DRRDisplay; 1274 dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal; 1275 dml_uint_t MaxInterDCNTileRepeaters; 1276 dml_uint_t MaxPrefetchMode; 1277 dml_float_t DRAMClockChangeLatencyFinal; 1278 dml_float_t FCLKChangeLatency; 1279 dml_float_t SREnterPlusExitTime; 1280 dml_uint_t ReturnBusWidth; 1281 dml_uint_t RoundTripPingLatencyCycles; 1282 dml_uint_t ReorderingBytes; 1283 dml_uint_t PixelChunkSizeInKByte; 1284 dml_uint_t MetaChunkSize; 1285 dml_bool_t GPUVMEnable; 1286 dml_uint_t GPUVMMaxPageTableLevels; 1287 dml_bool_t HostVMEnable; 1288 dml_uint_t NumberOfActiveSurfaces; 1289 dml_uint_t HostVMMinPageSize; 1290 dml_uint_t HostVMMaxNonCachedPageTableLevels; 1291 dml_bool_t DynamicMetadataVMEnabled; 1292 dml_bool_t ImmediateFlipRequirement; 1293 dml_bool_t ProgressiveToInterlaceUnitInOPP; 1294 dml_float_t MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; 1295 dml_float_t PercentOfIdealSDPPortBWReceivedAfterUrgLatency; 1296 dml_uint_t *VTotal; 1297 dml_uint_t *VActive; 1298 dml_uint_t *DynamicMetadataTransmittedBytes; 1299 dml_uint_t *DynamicMetadataLinesBeforeActiveRequired; 1300 dml_bool_t *Interlace; 1301 dml_float_t (*RequiredDPPCLKPerSurface)[__DML_NUM_PLANES__]; 1302 dml_float_t *RequiredDISPCLK; 1303 dml_float_t UrgLatency; 1304 dml_uint_t (*NoOfDPP)[__DML_NUM_PLANES__]; 1305 dml_float_t *ProjectedDCFCLKDeepSleep; 1306 dml_uint_t (*MaximumVStartup)[__DML_NUM_PLANES__]; 1307 dml_uint_t *TotalNumberOfActiveDPP; 1308 dml_uint_t *TotalNumberOfDCCActiveDPP; 1309 dml_uint_t *dpte_group_bytes; 1310 dml_uint_t (*PrefetchLinesY)[__DML_NUM_PLANES__]; 1311 dml_uint_t (*PrefetchLinesC)[__DML_NUM_PLANES__]; 1312 dml_uint_t (*swath_width_luma_ub_all_states)[__DML_NUM_PLANES__]; 1313 dml_uint_t (*swath_width_chroma_ub_all_states)[__DML_NUM_PLANES__]; 1314 dml_uint_t *BytePerPixelY; 1315 dml_uint_t *BytePerPixelC; 1316 dml_uint_t *HTotal; 1317 dml_float_t *PixelClock; 1318 dml_uint_t (*PDEAndMetaPTEBytesPerFrame)[__DML_NUM_PLANES__]; 1319 dml_uint_t (*DPTEBytesPerRow)[__DML_NUM_PLANES__]; 1320 dml_uint_t (*MetaRowBytes)[__DML_NUM_PLANES__]; 1321 dml_bool_t *DynamicMetadataEnable; 1322 dml_float_t *ReadBandwidthLuma; 1323 dml_float_t *ReadBandwidthChroma; 1324 dml_float_t DCFCLKPerState; 1325 dml_float_t *DCFCLKState; 1326 }; 1327 1328 struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st { 1329 dml_bool_t USRRetrainingRequiredFinal; 1330 enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange; 1331 dml_uint_t *PrefetchMode; 1332 dml_uint_t NumberOfActiveSurfaces; 1333 dml_uint_t MaxLineBufferLines; 1334 dml_uint_t LineBufferSize; 1335 dml_uint_t WritebackInterfaceBufferSize; 1336 dml_float_t DCFCLK; 1337 dml_float_t ReturnBW; 1338 dml_bool_t SynchronizeTimingsFinal; 1339 dml_bool_t SynchronizeDRRDisplaysForUCLKPStateChangeFinal; 1340 dml_bool_t *DRRDisplay; 1341 dml_uint_t *dpte_group_bytes; 1342 dml_uint_t *meta_row_height; 1343 dml_uint_t *meta_row_height_chroma; 1344 struct SOCParametersList mmSOCParameters; 1345 dml_uint_t WritebackChunkSize; 1346 dml_float_t SOCCLK; 1347 dml_float_t DCFClkDeepSleep; 1348 dml_uint_t *DETBufferSizeY; 1349 dml_uint_t *DETBufferSizeC; 1350 dml_uint_t *SwathHeightY; 1351 dml_uint_t *SwathHeightC; 1352 dml_uint_t *LBBitPerPixel; 1353 dml_uint_t *SwathWidthY; 1354 dml_uint_t *SwathWidthC; 1355 dml_float_t *HRatio; 1356 dml_float_t *HRatioChroma; 1357 dml_uint_t *VTaps; 1358 dml_uint_t *VTapsChroma; 1359 dml_float_t *VRatio; 1360 dml_float_t *VRatioChroma; 1361 dml_uint_t *HTotal; 1362 dml_uint_t *VTotal; 1363 dml_uint_t *VActive; 1364 dml_float_t *PixelClock; 1365 dml_uint_t *BlendingAndTiming; 1366 dml_uint_t *DPPPerSurface; 1367 dml_float_t *BytePerPixelDETY; 1368 dml_float_t *BytePerPixelDETC; 1369 dml_uint_t *DSTXAfterScaler; 1370 dml_uint_t *DSTYAfterScaler; 1371 dml_bool_t *WritebackEnable; 1372 enum dml_source_format_class *WritebackPixelFormat; 1373 dml_uint_t *WritebackDestinationWidth; 1374 dml_uint_t *WritebackDestinationHeight; 1375 dml_uint_t *WritebackSourceHeight; 1376 dml_bool_t UnboundedRequestEnabled; 1377 dml_uint_t CompressedBufferSizeInkByte; 1378 1379 // Output 1380 struct Watermarks *Watermark; 1381 enum dml_dram_clock_change_support *DRAMClockChangeSupport; 1382 dml_float_t *MaxActiveDRAMClockChangeLatencySupported; 1383 dml_uint_t *SubViewportLinesNeededInMALL; 1384 enum dml_fclock_change_support *FCLKChangeSupport; 1385 dml_float_t *MaxActiveFCLKChangeLatencySupported; 1386 dml_bool_t *USRRetrainingSupport; 1387 dml_float_t *ActiveDRAMClockChangeLatencyMargin; 1388 }; 1389 1390 struct CalculateVMRowAndSwath_params_st { 1391 dml_uint_t NumberOfActiveSurfaces; 1392 struct DmlPipe *myPipe; 1393 dml_uint_t *SurfaceSizeInMALL; 1394 dml_uint_t PTEBufferSizeInRequestsLuma; 1395 dml_uint_t PTEBufferSizeInRequestsChroma; 1396 dml_uint_t DCCMetaBufferSizeBytes; 1397 enum dml_use_mall_for_static_screen_mode *UseMALLForStaticScreen; 1398 enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange; 1399 dml_uint_t MALLAllocatedForDCN; 1400 dml_uint_t *SwathWidthY; 1401 dml_uint_t *SwathWidthC; 1402 dml_bool_t GPUVMEnable; 1403 dml_bool_t HostVMEnable; 1404 dml_uint_t HostVMMaxNonCachedPageTableLevels; 1405 dml_uint_t GPUVMMaxPageTableLevels; 1406 dml_uint_t *GPUVMMinPageSizeKBytes; 1407 dml_uint_t HostVMMinPageSize; 1408 dml_bool_t *PTEBufferModeOverrideEn; 1409 dml_bool_t *PTEBufferModeOverrideVal; 1410 1411 // Output 1412 dml_bool_t *PTEBufferSizeNotExceeded; 1413 dml_bool_t *DCCMetaBufferSizeNotExceeded; 1414 dml_uint_t *dpte_row_width_luma_ub; 1415 dml_uint_t *dpte_row_width_chroma_ub; 1416 dml_uint_t *dpte_row_height_luma; 1417 dml_uint_t *dpte_row_height_chroma; 1418 dml_uint_t *dpte_row_height_linear_luma; // VBA_DELTA 1419 dml_uint_t *dpte_row_height_linear_chroma; // VBA_DELTA 1420 dml_uint_t *meta_req_width; 1421 dml_uint_t *meta_req_width_chroma; 1422 dml_uint_t *meta_req_height; 1423 dml_uint_t *meta_req_height_chroma; 1424 dml_uint_t *meta_row_width; 1425 dml_uint_t *meta_row_width_chroma; 1426 dml_uint_t *meta_row_height; 1427 dml_uint_t *meta_row_height_chroma; 1428 dml_uint_t *vm_group_bytes; 1429 dml_uint_t *dpte_group_bytes; 1430 dml_uint_t *PixelPTEReqWidthY; 1431 dml_uint_t *PixelPTEReqHeightY; 1432 dml_uint_t *PTERequestSizeY; 1433 dml_uint_t *PixelPTEReqWidthC; 1434 dml_uint_t *PixelPTEReqHeightC; 1435 dml_uint_t *PTERequestSizeC; 1436 dml_uint_t *dpde0_bytes_per_frame_ub_l; 1437 dml_uint_t *meta_pte_bytes_per_frame_ub_l; 1438 dml_uint_t *dpde0_bytes_per_frame_ub_c; 1439 dml_uint_t *meta_pte_bytes_per_frame_ub_c; 1440 dml_uint_t *PrefetchSourceLinesY; 1441 dml_uint_t *PrefetchSourceLinesC; 1442 dml_uint_t *VInitPreFillY; 1443 dml_uint_t *VInitPreFillC; 1444 dml_uint_t *MaxNumSwathY; 1445 dml_uint_t *MaxNumSwathC; 1446 dml_float_t *meta_row_bw; 1447 dml_float_t *dpte_row_bw; 1448 dml_uint_t *PixelPTEBytesPerRow; 1449 dml_uint_t *PDEAndMetaPTEBytesFrame; 1450 dml_uint_t *MetaRowByte; 1451 dml_bool_t *use_one_row_for_frame; 1452 dml_bool_t *use_one_row_for_frame_flip; 1453 dml_bool_t *UsesMALLForStaticScreen; 1454 dml_bool_t *PTE_BUFFER_MODE; 1455 dml_uint_t *BIGK_FRAGMENT_SIZE; 1456 }; 1457 1458 struct CalculateSwathAndDETConfiguration_params_st { 1459 dml_uint_t *DETSizeOverride; 1460 enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange; 1461 dml_uint_t ConfigReturnBufferSizeInKByte; 1462 dml_uint_t ROBBufferSizeInKByte; 1463 dml_uint_t MaxTotalDETInKByte; 1464 dml_uint_t MinCompressedBufferSizeInKByte; 1465 dml_uint_t PixelChunkSizeInKByte; 1466 dml_bool_t ForceSingleDPP; 1467 dml_uint_t NumberOfActiveSurfaces; 1468 dml_uint_t nomDETInKByte; 1469 enum dml_unbounded_requesting_policy UseUnboundedRequestingFinal; 1470 dml_uint_t ConfigReturnBufferSegmentSizeInkByte; 1471 dml_uint_t CompressedBufferSegmentSizeInkByteFinal; 1472 enum dml_output_encoder_class *Output; 1473 dml_float_t *ReadBandwidthLuma; 1474 dml_float_t *ReadBandwidthChroma; 1475 dml_float_t *MaximumSwathWidthLuma; 1476 dml_float_t *MaximumSwathWidthChroma; 1477 enum dml_rotation_angle *SourceScan; 1478 dml_bool_t *ViewportStationary; 1479 enum dml_source_format_class *SourcePixelFormat; 1480 enum dml_swizzle_mode *SurfaceTiling; 1481 dml_uint_t *ViewportWidth; 1482 dml_uint_t *ViewportHeight; 1483 dml_uint_t *ViewportXStart; 1484 dml_uint_t *ViewportYStart; 1485 dml_uint_t *ViewportXStartC; 1486 dml_uint_t *ViewportYStartC; 1487 dml_uint_t *SurfaceWidthY; 1488 dml_uint_t *SurfaceWidthC; 1489 dml_uint_t *SurfaceHeightY; 1490 dml_uint_t *SurfaceHeightC; 1491 dml_uint_t *Read256BytesBlockHeightY; 1492 dml_uint_t *Read256BytesBlockHeightC; 1493 dml_uint_t *Read256BytesBlockWidthY; 1494 dml_uint_t *Read256BytesBlockWidthC; 1495 enum dml_odm_mode *ODMMode; 1496 dml_uint_t *BlendingAndTiming; 1497 dml_uint_t *BytePerPixY; 1498 dml_uint_t *BytePerPixC; 1499 dml_float_t *BytePerPixDETY; 1500 dml_float_t *BytePerPixDETC; 1501 dml_uint_t *HActive; 1502 dml_float_t *HRatio; 1503 dml_float_t *HRatioChroma; 1504 dml_uint_t *DPPPerSurface; 1505 dml_uint_t *swath_width_luma_ub; 1506 dml_uint_t *swath_width_chroma_ub; 1507 dml_uint_t *SwathWidth; 1508 dml_uint_t *SwathWidthChroma; 1509 dml_uint_t *SwathHeightY; 1510 dml_uint_t *SwathHeightC; 1511 dml_uint_t *DETBufferSizeInKByte; 1512 dml_uint_t *DETBufferSizeY; 1513 dml_uint_t *DETBufferSizeC; 1514 dml_bool_t *UnboundedRequestEnabled; 1515 dml_uint_t *compbuf_reserved_space_64b; 1516 dml_uint_t *compbuf_reserved_space_zs; 1517 dml_uint_t *CompressedBufferSizeInkByte; 1518 dml_bool_t *ViewportSizeSupportPerSurface; 1519 dml_bool_t *ViewportSizeSupport; 1520 }; 1521 1522 struct CalculateStutterEfficiency_params_st { 1523 dml_uint_t CompressedBufferSizeInkByte; 1524 enum dml_use_mall_for_pstate_change_mode *UseMALLForPStateChange; 1525 dml_bool_t UnboundedRequestEnabled; 1526 dml_uint_t MetaFIFOSizeInKEntries; 1527 dml_uint_t ZeroSizeBufferEntries; 1528 dml_uint_t PixelChunkSizeInKByte; 1529 dml_uint_t NumberOfActiveSurfaces; 1530 dml_uint_t ROBBufferSizeInKByte; 1531 dml_float_t TotalDataReadBandwidth; 1532 dml_float_t DCFCLK; 1533 dml_float_t ReturnBW; 1534 dml_uint_t CompbufReservedSpace64B; 1535 dml_uint_t CompbufReservedSpaceZs; 1536 dml_float_t SRExitTime; 1537 dml_float_t SRExitZ8Time; 1538 dml_bool_t SynchronizeTimingsFinal; 1539 dml_uint_t *BlendingAndTiming; 1540 dml_float_t StutterEnterPlusExitWatermark; 1541 dml_float_t Z8StutterEnterPlusExitWatermark; 1542 dml_bool_t ProgressiveToInterlaceUnitInOPP; 1543 dml_bool_t *Interlace; 1544 dml_float_t *MinTTUVBlank; 1545 dml_uint_t *DPPPerSurface; 1546 dml_uint_t *DETBufferSizeY; 1547 dml_uint_t *BytePerPixelY; 1548 dml_float_t *BytePerPixelDETY; 1549 dml_uint_t *SwathWidthY; 1550 dml_uint_t *SwathHeightY; 1551 dml_uint_t *SwathHeightC; 1552 dml_float_t *NetDCCRateLuma; 1553 dml_float_t *NetDCCRateChroma; 1554 dml_float_t *DCCFractionOfZeroSizeRequestsLuma; 1555 dml_float_t *DCCFractionOfZeroSizeRequestsChroma; 1556 dml_uint_t *HTotal; 1557 dml_uint_t *VTotal; 1558 dml_float_t *PixelClock; 1559 dml_float_t *VRatio; 1560 enum dml_rotation_angle *SourceScan; 1561 dml_uint_t *BlockHeight256BytesY; 1562 dml_uint_t *BlockWidth256BytesY; 1563 dml_uint_t *BlockHeight256BytesC; 1564 dml_uint_t *BlockWidth256BytesC; 1565 dml_uint_t *DCCYMaxUncompressedBlock; 1566 dml_uint_t *DCCCMaxUncompressedBlock; 1567 dml_uint_t *VActive; 1568 dml_bool_t *DCCEnable; 1569 dml_bool_t *WritebackEnable; 1570 dml_float_t *ReadBandwidthSurfaceLuma; 1571 dml_float_t *ReadBandwidthSurfaceChroma; 1572 dml_float_t *meta_row_bw; 1573 dml_float_t *dpte_row_bw; 1574 dml_float_t *StutterEfficiencyNotIncludingVBlank; 1575 dml_float_t *StutterEfficiency; 1576 dml_uint_t *NumberOfStutterBurstsPerFrame; 1577 dml_float_t *Z8StutterEfficiencyNotIncludingVBlank; 1578 dml_float_t *Z8StutterEfficiency; 1579 dml_uint_t *Z8NumberOfStutterBurstsPerFrame; 1580 dml_float_t *StutterPeriod; 1581 dml_bool_t *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 1582 }; 1583 1584 struct CalculatePrefetchSchedule_params_st { 1585 dml_bool_t EnhancedPrefetchScheduleAccelerationFinal; 1586 dml_float_t HostVMInefficiencyFactor; 1587 struct DmlPipe *myPipe; 1588 dml_uint_t DSCDelay; 1589 dml_float_t DPPCLKDelaySubtotalPlusCNVCFormater; 1590 dml_float_t DPPCLKDelaySCL; 1591 dml_float_t DPPCLKDelaySCLLBOnly; 1592 dml_float_t DPPCLKDelayCNVCCursor; 1593 dml_float_t DISPCLKDelaySubtotal; 1594 dml_uint_t DPP_RECOUT_WIDTH; 1595 enum dml_output_format_class OutputFormat; 1596 dml_uint_t MaxInterDCNTileRepeaters; 1597 dml_uint_t VStartup; 1598 dml_uint_t MaxVStartup; 1599 dml_uint_t GPUVMPageTableLevels; 1600 dml_bool_t GPUVMEnable; 1601 dml_bool_t HostVMEnable; 1602 dml_uint_t HostVMMaxNonCachedPageTableLevels; 1603 dml_uint_t HostVMMinPageSize; 1604 dml_bool_t DynamicMetadataEnable; 1605 dml_bool_t DynamicMetadataVMEnabled; 1606 int DynamicMetadataLinesBeforeActiveRequired; 1607 dml_uint_t DynamicMetadataTransmittedBytes; 1608 dml_float_t UrgentLatency; 1609 dml_float_t UrgentExtraLatency; 1610 dml_float_t TCalc; 1611 dml_uint_t PDEAndMetaPTEBytesFrame; 1612 dml_uint_t MetaRowByte; 1613 dml_uint_t PixelPTEBytesPerRow; 1614 dml_float_t PrefetchSourceLinesY; 1615 dml_uint_t VInitPreFillY; 1616 dml_uint_t MaxNumSwathY; 1617 dml_float_t PrefetchSourceLinesC; 1618 dml_uint_t VInitPreFillC; 1619 dml_uint_t MaxNumSwathC; 1620 dml_uint_t swath_width_luma_ub; 1621 dml_uint_t swath_width_chroma_ub; 1622 dml_uint_t SwathHeightY; 1623 dml_uint_t SwathHeightC; 1624 dml_float_t TWait; 1625 dml_uint_t *DSTXAfterScaler; 1626 dml_uint_t *DSTYAfterScaler; 1627 dml_float_t *DestinationLinesForPrefetch; 1628 dml_float_t *DestinationLinesToRequestVMInVBlank; 1629 dml_float_t *DestinationLinesToRequestRowInVBlank; 1630 dml_float_t *VRatioPrefetchY; 1631 dml_float_t *VRatioPrefetchC; 1632 dml_float_t *RequiredPrefetchPixDataBWLuma; 1633 dml_float_t *RequiredPrefetchPixDataBWChroma; 1634 dml_bool_t *NotEnoughTimeForDynamicMetadata; 1635 dml_float_t *Tno_bw; 1636 dml_float_t *prefetch_vmrow_bw; 1637 dml_float_t *Tdmdl_vm; 1638 dml_float_t *Tdmdl; 1639 dml_float_t *TSetup; 1640 dml_uint_t *VUpdateOffsetPix; 1641 dml_uint_t *VUpdateWidthPix; 1642 dml_uint_t *VReadyOffsetPix; 1643 }; 1644 1645 struct dml_core_mode_support_locals_st { 1646 dml_bool_t dummy_boolean[2]; 1647 dml_uint_t dummy_integer[3]; 1648 dml_uint_t dummy_integer_array[22][__DML_NUM_PLANES__]; 1649 enum dml_odm_mode dummy_odm_mode[__DML_NUM_PLANES__]; 1650 dml_bool_t dummy_boolean_array[2][__DML_NUM_PLANES__]; 1651 dml_uint_t MaxVStartupAllPlanes[2]; 1652 dml_uint_t MaximumVStartup[2][__DML_NUM_PLANES__]; 1653 dml_uint_t DSTYAfterScaler[__DML_NUM_PLANES__]; 1654 dml_uint_t DSTXAfterScaler[__DML_NUM_PLANES__]; 1655 dml_uint_t NextPrefetchMode[__DML_NUM_PLANES__]; 1656 dml_uint_t MinPrefetchMode[__DML_NUM_PLANES__]; 1657 dml_uint_t MaxPrefetchMode[__DML_NUM_PLANES__]; 1658 dml_float_t dummy_single[3]; 1659 dml_float_t dummy_single_array[__DML_NUM_PLANES__]; 1660 struct Watermarks dummy_watermark; 1661 struct SOCParametersList mSOCParameters; 1662 struct DmlPipe myPipe; 1663 struct DmlPipe SurfParameters[__DML_NUM_PLANES__]; 1664 dml_uint_t TotalNumberOfActiveWriteback; 1665 dml_uint_t MaximumSwathWidthSupportLuma; 1666 dml_uint_t MaximumSwathWidthSupportChroma; 1667 dml_bool_t MPCCombineMethodAsNeededForPStateChangeAndVoltage; 1668 dml_bool_t MPCCombineMethodAsPossible; 1669 dml_bool_t TotalAvailablePipesSupportNoDSC; 1670 dml_uint_t NumberOfDPPNoDSC; 1671 enum dml_odm_mode ODMModeNoDSC; 1672 dml_float_t RequiredDISPCLKPerSurfaceNoDSC; 1673 dml_bool_t TotalAvailablePipesSupportDSC; 1674 dml_uint_t NumberOfDPPDSC; 1675 enum dml_odm_mode ODMModeDSC; 1676 dml_float_t RequiredDISPCLKPerSurfaceDSC; 1677 dml_bool_t NoChromaOrLinear; 1678 dml_float_t BWOfNonCombinedSurfaceOfMaximumBandwidth; 1679 dml_uint_t NumberOfNonCombinedSurfaceOfMaximumBandwidth; 1680 dml_uint_t TotalNumberOfActiveOTG; 1681 dml_uint_t TotalNumberOfActiveHDMIFRL; 1682 dml_uint_t TotalNumberOfActiveDP2p0; 1683 dml_uint_t TotalNumberOfActiveDP2p0Outputs; 1684 dml_uint_t TotalSlots; 1685 dml_uint_t DSCFormatFactor; 1686 dml_uint_t TotalDSCUnitsRequired; 1687 dml_uint_t ReorderingBytes; 1688 dml_bool_t ImmediateFlipRequiredFinal; 1689 dml_bool_t FullFrameMALLPStateMethod; 1690 dml_bool_t SubViewportMALLPStateMethod; 1691 dml_bool_t PhantomPipeMALLPStateMethod; 1692 dml_bool_t SubViewportMALLRefreshGreaterThan120Hz; 1693 dml_float_t MaxTotalVActiveRDBandwidth; 1694 dml_float_t VMDataOnlyReturnBWPerState; 1695 dml_float_t HostVMInefficiencyFactor; 1696 dml_uint_t NextMaxVStartup; 1697 dml_uint_t MaxVStartup; 1698 dml_bool_t AllPrefetchModeTested; 1699 dml_bool_t AnyLinesForVMOrRowTooLarge; 1700 dml_bool_t is_max_pwr_state; 1701 dml_bool_t is_max_dram_pwr_state; 1702 dml_bool_t dram_clock_change_support; 1703 dml_bool_t f_clock_change_support; 1704 }; 1705 1706 struct dml_core_mode_programming_locals_st { 1707 dml_uint_t DSCFormatFactor; 1708 dml_uint_t dummy_integer_array[2][__DML_NUM_PLANES__]; 1709 enum dml_output_encoder_class dummy_output_encoder_array[__DML_NUM_PLANES__]; 1710 dml_float_t dummy_single_array[2][__DML_NUM_PLANES__]; 1711 dml_uint_t dummy_long_array[4][__DML_NUM_PLANES__]; 1712 dml_bool_t dummy_boolean_array[2][__DML_NUM_PLANES__]; 1713 dml_bool_t dummy_boolean[1]; 1714 struct DmlPipe SurfaceParameters[__DML_NUM_PLANES__]; 1715 dml_uint_t ReorderBytes; 1716 dml_float_t VMDataOnlyReturnBW; 1717 dml_float_t HostVMInefficiencyFactor; 1718 dml_uint_t TotalDCCActiveDPP; 1719 dml_uint_t TotalActiveDPP; 1720 dml_uint_t VStartupLines; 1721 dml_uint_t MaxVStartupLines[__DML_NUM_PLANES__]; /// <brief more like vblank for the plane's OTG 1722 dml_uint_t MaxVStartupAllPlanes; 1723 dml_bool_t ImmediateFlipRequirementFinal; 1724 int iteration; 1725 dml_float_t MaxTotalRDBandwidth; 1726 dml_float_t MaxTotalRDBandwidthNoUrgentBurst; 1727 dml_bool_t DestinationLineTimesForPrefetchLessThan2; 1728 dml_bool_t VRatioPrefetchMoreThanMax; 1729 dml_float_t MaxTotalRDBandwidthNotIncludingMALLPrefetch; 1730 dml_uint_t NextPrefetchMode[__DML_NUM_PLANES__]; 1731 dml_uint_t MinPrefetchMode[__DML_NUM_PLANES__]; 1732 dml_uint_t MaxPrefetchMode[__DML_NUM_PLANES__]; 1733 dml_bool_t AllPrefetchModeTested; 1734 dml_float_t dummy_unit_vector[__DML_NUM_PLANES__]; 1735 dml_float_t NonUrgentMaxTotalRDBandwidth; 1736 dml_float_t NonUrgentMaxTotalRDBandwidthNotIncludingMALLPrefetch; 1737 dml_float_t dummy_single[2]; 1738 struct SOCParametersList mmSOCParameters; 1739 dml_float_t Tvstartup_margin; 1740 dml_float_t dlg_vblank_start; 1741 dml_float_t LSetup; 1742 dml_float_t blank_lines_remaining; 1743 dml_float_t old_MIN_DST_Y_NEXT_START; 1744 dml_float_t TotalWRBandwidth; 1745 dml_float_t WRBandwidth; 1746 struct Watermarks dummy_watermark; 1747 struct DmlPipe myPipe; 1748 }; 1749 1750 struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals_st { 1751 dml_float_t ActiveDRAMClockChangeLatencyMargin[__DML_NUM_PLANES__]; 1752 dml_float_t ActiveFCLKChangeLatencyMargin[__DML_NUM_PLANES__]; 1753 dml_float_t USRRetrainingLatencyMargin[__DML_NUM_PLANES__]; 1754 1755 dml_bool_t SynchronizedSurfaces[__DML_NUM_PLANES__][__DML_NUM_PLANES__]; 1756 dml_float_t EffectiveLBLatencyHidingY; 1757 dml_float_t EffectiveLBLatencyHidingC; 1758 dml_float_t LinesInDETY[__DML_NUM_PLANES__]; 1759 dml_float_t LinesInDETC[__DML_NUM_PLANES__]; 1760 dml_uint_t LinesInDETYRoundedDownToSwath[__DML_NUM_PLANES__]; 1761 dml_uint_t LinesInDETCRoundedDownToSwath[__DML_NUM_PLANES__]; 1762 dml_float_t FullDETBufferingTimeY; 1763 dml_float_t FullDETBufferingTimeC; 1764 dml_float_t WritebackDRAMClockChangeLatencyMargin; 1765 dml_float_t WritebackFCLKChangeLatencyMargin; 1766 dml_float_t WritebackLatencyHiding; 1767 1768 dml_uint_t TotalActiveWriteback; 1769 dml_uint_t LBLatencyHidingSourceLinesY[__DML_NUM_PLANES__]; 1770 dml_uint_t LBLatencyHidingSourceLinesC[__DML_NUM_PLANES__]; 1771 dml_float_t TotalPixelBW; 1772 dml_float_t EffectiveDETBufferSizeY; 1773 dml_float_t ActiveClockChangeLatencyHidingY; 1774 dml_float_t ActiveClockChangeLatencyHidingC; 1775 dml_float_t ActiveClockChangeLatencyHiding; 1776 dml_bool_t FoundCriticalSurface; 1777 dml_uint_t LastSurfaceWithoutMargin; 1778 dml_uint_t FCLKChangeSupportNumber; 1779 dml_uint_t DRAMClockChangeMethod; 1780 dml_uint_t DRAMClockChangeSupportNumber; 1781 dml_uint_t dst_y_pstate; 1782 dml_uint_t src_y_pstate_l; 1783 dml_uint_t src_y_pstate_c; 1784 dml_uint_t src_y_ahead_l; 1785 dml_uint_t src_y_ahead_c; 1786 dml_uint_t sub_vp_lines_l; 1787 dml_uint_t sub_vp_lines_c; 1788 }; 1789 1790 struct CalculateVMRowAndSwath_locals_st { 1791 dml_uint_t PTEBufferSizeInRequestsForLuma[__DML_NUM_PLANES__]; 1792 dml_uint_t PTEBufferSizeInRequestsForChroma[__DML_NUM_PLANES__]; 1793 dml_uint_t PDEAndMetaPTEBytesFrameY; 1794 dml_uint_t PDEAndMetaPTEBytesFrameC; 1795 dml_uint_t MetaRowByteY[__DML_NUM_PLANES__]; 1796 dml_uint_t MetaRowByteC[__DML_NUM_PLANES__]; 1797 dml_uint_t PixelPTEBytesPerRowY[__DML_NUM_PLANES__]; 1798 dml_uint_t PixelPTEBytesPerRowC[__DML_NUM_PLANES__]; 1799 dml_uint_t PixelPTEBytesPerRowStorageY[__DML_NUM_PLANES__]; 1800 dml_uint_t PixelPTEBytesPerRowStorageC[__DML_NUM_PLANES__]; 1801 dml_uint_t PixelPTEBytesPerRowY_one_row_per_frame[__DML_NUM_PLANES__]; 1802 dml_uint_t PixelPTEBytesPerRowC_one_row_per_frame[__DML_NUM_PLANES__]; 1803 dml_uint_t dpte_row_width_luma_ub_one_row_per_frame[__DML_NUM_PLANES__]; 1804 dml_uint_t dpte_row_height_luma_one_row_per_frame[__DML_NUM_PLANES__]; 1805 dml_uint_t dpte_row_width_chroma_ub_one_row_per_frame[__DML_NUM_PLANES__]; 1806 dml_uint_t dpte_row_height_chroma_one_row_per_frame[__DML_NUM_PLANES__]; 1807 dml_bool_t one_row_per_frame_fits_in_buffer[__DML_NUM_PLANES__]; 1808 1809 dml_uint_t HostVMDynamicLevels; 1810 }; 1811 1812 struct UseMinimumDCFCLK_locals_st { 1813 dml_uint_t dummy1; 1814 dml_uint_t dummy2; 1815 dml_uint_t dummy3; 1816 dml_float_t NormalEfficiency; 1817 dml_float_t TotalMaxPrefetchFlipDPTERowBandwidth[2]; 1818 1819 dml_float_t PixelDCFCLKCyclesRequiredInPrefetch[__DML_NUM_PLANES__]; 1820 dml_float_t PrefetchPixelLinesTime[__DML_NUM_PLANES__]; 1821 dml_float_t DCFCLKRequiredForPeakBandwidthPerSurface[__DML_NUM_PLANES__]; 1822 dml_float_t DynamicMetadataVMExtraLatency[__DML_NUM_PLANES__]; 1823 dml_float_t MinimumTWait; 1824 dml_float_t DPTEBandwidth; 1825 dml_float_t DCFCLKRequiredForAverageBandwidth; 1826 dml_uint_t ExtraLatencyBytes; 1827 dml_float_t ExtraLatencyCycles; 1828 dml_float_t DCFCLKRequiredForPeakBandwidth; 1829 dml_uint_t NoOfDPPState[__DML_NUM_PLANES__]; 1830 dml_float_t MinimumTvmPlus2Tr0; 1831 }; 1832 1833 struct CalculatePrefetchSchedule_locals_st { 1834 dml_bool_t MyError; 1835 dml_uint_t DPPCycles; 1836 dml_uint_t DISPCLKCycles; 1837 dml_float_t DSTTotalPixelsAfterScaler; 1838 dml_float_t LineTime; 1839 dml_float_t dst_y_prefetch_equ; 1840 dml_float_t prefetch_bw_oto; 1841 dml_float_t Tvm_oto; 1842 dml_float_t Tr0_oto; 1843 dml_float_t Tvm_oto_lines; 1844 dml_float_t Tr0_oto_lines; 1845 dml_float_t dst_y_prefetch_oto; 1846 dml_float_t TimeForFetchingMetaPTE; 1847 dml_float_t TimeForFetchingRowInVBlank; 1848 dml_float_t LinesToRequestPrefetchPixelData; 1849 dml_uint_t HostVMDynamicLevelsTrips; 1850 dml_float_t trip_to_mem; 1851 dml_float_t Tvm_trips; 1852 dml_float_t Tr0_trips; 1853 dml_float_t Tvm_trips_rounded; 1854 dml_float_t Tr0_trips_rounded; 1855 dml_float_t max_Tsw; 1856 dml_float_t Lsw_oto; 1857 dml_float_t Tpre_rounded; 1858 dml_float_t prefetch_bw_equ; 1859 dml_float_t Tvm_equ; 1860 dml_float_t Tr0_equ; 1861 dml_float_t Tdmbf; 1862 dml_float_t Tdmec; 1863 dml_float_t Tdmsks; 1864 dml_float_t prefetch_sw_bytes; 1865 dml_float_t prefetch_bw_pr; 1866 dml_float_t bytes_pp; 1867 dml_float_t dep_bytes; 1868 dml_float_t min_Lsw_oto; 1869 dml_float_t Tsw_est1; 1870 dml_float_t Tsw_est3; 1871 dml_float_t PrefetchBandwidth1; 1872 dml_float_t PrefetchBandwidth2; 1873 dml_float_t PrefetchBandwidth3; 1874 dml_float_t PrefetchBandwidth4; 1875 }; 1876 1877 /// @brief To minimize stack usage; function locals are instead placed into this scratch structure which is allocated per context 1878 struct display_mode_lib_scratch_st { 1879 // Scratch space for function locals 1880 struct dml_core_mode_support_locals_st dml_core_mode_support_locals; 1881 struct dml_core_mode_programming_locals_st dml_core_mode_programming_locals; 1882 struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals_st CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals; 1883 struct CalculateVMRowAndSwath_locals_st CalculateVMRowAndSwath_locals; 1884 struct UseMinimumDCFCLK_locals_st UseMinimumDCFCLK_locals; 1885 struct CalculatePrefetchSchedule_locals_st CalculatePrefetchSchedule_locals; 1886 1887 // Scratch space for function params 1888 struct CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params_st CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params; 1889 struct CalculateVMRowAndSwath_params_st CalculateVMRowAndSwath_params; 1890 struct UseMinimumDCFCLK_params_st UseMinimumDCFCLK_params; 1891 struct CalculateSwathAndDETConfiguration_params_st CalculateSwathAndDETConfiguration_params; 1892 struct CalculateStutterEfficiency_params_st CalculateStutterEfficiency_params; 1893 struct CalculatePrefetchSchedule_params_st CalculatePrefetchSchedule_params; 1894 }; 1895 1896 /// @brief Represent the overall soc/ip enviroment. It contains data structure represent the soc/ip characteristic and also structures that hold calculation output 1897 struct display_mode_lib_st { 1898 dml_uint_t project; 1899 1900 //@brief Mode evaluation and programming policy 1901 struct dml_mode_eval_policy_st policy; 1902 1903 //@brief IP/SOC characteristic 1904 struct ip_params_st ip; 1905 struct soc_bounding_box_st soc; 1906 struct soc_states_st states; 1907 1908 //@brief Mode Support and Mode programming struct 1909 // Used to hold input; intermediate and output of the calculations 1910 struct mode_support_st ms; // struct for mode support 1911 struct mode_program_st mp; // struct for mode programming 1912 1913 struct display_mode_lib_scratch_st scratch; 1914 }; 1915 1916 struct dml_mode_support_ex_params_st { 1917 struct display_mode_lib_st *mode_lib; 1918 const struct dml_display_cfg_st *in_display_cfg; 1919 dml_uint_t out_lowest_state_idx; 1920 struct dml_mode_support_info_st *out_evaluation_info; 1921 }; 1922 1923 typedef struct _vcs_dpi_dml_display_rq_regs_st dml_display_rq_regs_st; 1924 typedef struct _vcs_dpi_dml_display_dlg_regs_st dml_display_dlg_regs_st; 1925 typedef struct _vcs_dpi_dml_display_ttu_regs_st dml_display_ttu_regs_st; 1926 typedef struct _vcs_dpi_dml_display_arb_params_st dml_display_arb_params_st; 1927 typedef struct _vcs_dpi_dml_display_plane_rq_regs_st dml_display_plane_rq_regs_st; 1928 1929 struct _vcs_dpi_dml_display_dlg_regs_st { 1930 dml_uint_t refcyc_h_blank_end; 1931 dml_uint_t dlg_vblank_end; 1932 dml_uint_t min_dst_y_next_start; 1933 dml_uint_t refcyc_per_htotal; 1934 dml_uint_t refcyc_x_after_scaler; 1935 dml_uint_t dst_y_after_scaler; 1936 dml_uint_t dst_y_prefetch; 1937 dml_uint_t dst_y_per_vm_vblank; 1938 dml_uint_t dst_y_per_row_vblank; 1939 dml_uint_t dst_y_per_vm_flip; 1940 dml_uint_t dst_y_per_row_flip; 1941 dml_uint_t ref_freq_to_pix_freq; 1942 dml_uint_t vratio_prefetch; 1943 dml_uint_t vratio_prefetch_c; 1944 dml_uint_t refcyc_per_pte_group_vblank_l; 1945 dml_uint_t refcyc_per_pte_group_vblank_c; 1946 dml_uint_t refcyc_per_meta_chunk_vblank_l; 1947 dml_uint_t refcyc_per_meta_chunk_vblank_c; 1948 dml_uint_t refcyc_per_pte_group_flip_l; 1949 dml_uint_t refcyc_per_pte_group_flip_c; 1950 dml_uint_t refcyc_per_meta_chunk_flip_l; 1951 dml_uint_t refcyc_per_meta_chunk_flip_c; 1952 dml_uint_t dst_y_per_pte_row_nom_l; 1953 dml_uint_t dst_y_per_pte_row_nom_c; 1954 dml_uint_t refcyc_per_pte_group_nom_l; 1955 dml_uint_t refcyc_per_pte_group_nom_c; 1956 dml_uint_t dst_y_per_meta_row_nom_l; 1957 dml_uint_t dst_y_per_meta_row_nom_c; 1958 dml_uint_t refcyc_per_meta_chunk_nom_l; 1959 dml_uint_t refcyc_per_meta_chunk_nom_c; 1960 dml_uint_t refcyc_per_line_delivery_pre_l; 1961 dml_uint_t refcyc_per_line_delivery_pre_c; 1962 dml_uint_t refcyc_per_line_delivery_l; 1963 dml_uint_t refcyc_per_line_delivery_c; 1964 dml_uint_t refcyc_per_vm_group_vblank; 1965 dml_uint_t refcyc_per_vm_group_flip; 1966 dml_uint_t refcyc_per_vm_req_vblank; 1967 dml_uint_t refcyc_per_vm_req_flip; 1968 dml_uint_t dst_y_offset_cur0; 1969 dml_uint_t chunk_hdl_adjust_cur0; 1970 dml_uint_t dst_y_offset_cur1; 1971 dml_uint_t chunk_hdl_adjust_cur1; 1972 dml_uint_t vready_after_vcount0; 1973 dml_uint_t dst_y_delta_drq_limit; 1974 dml_uint_t refcyc_per_vm_dmdata; 1975 dml_uint_t dmdata_dl_delta; 1976 }; 1977 1978 struct _vcs_dpi_dml_display_ttu_regs_st { 1979 dml_uint_t qos_level_low_wm; 1980 dml_uint_t qos_level_high_wm; 1981 dml_uint_t min_ttu_vblank; 1982 dml_uint_t qos_level_flip; 1983 dml_uint_t refcyc_per_req_delivery_l; 1984 dml_uint_t refcyc_per_req_delivery_c; 1985 dml_uint_t refcyc_per_req_delivery_cur0; 1986 dml_uint_t refcyc_per_req_delivery_cur1; 1987 dml_uint_t refcyc_per_req_delivery_pre_l; 1988 dml_uint_t refcyc_per_req_delivery_pre_c; 1989 dml_uint_t refcyc_per_req_delivery_pre_cur0; 1990 dml_uint_t refcyc_per_req_delivery_pre_cur1; 1991 dml_uint_t qos_level_fixed_l; 1992 dml_uint_t qos_level_fixed_c; 1993 dml_uint_t qos_level_fixed_cur0; 1994 dml_uint_t qos_level_fixed_cur1; 1995 dml_uint_t qos_ramp_disable_l; 1996 dml_uint_t qos_ramp_disable_c; 1997 dml_uint_t qos_ramp_disable_cur0; 1998 dml_uint_t qos_ramp_disable_cur1; 1999 }; 2000 2001 struct _vcs_dpi_dml_display_arb_params_st { 2002 dml_uint_t max_req_outstanding; 2003 dml_uint_t min_req_outstanding; 2004 dml_uint_t sat_level_us; 2005 dml_uint_t hvm_max_qos_commit_threshold; 2006 dml_uint_t hvm_min_req_outstand_commit_threshold; 2007 dml_uint_t compbuf_reserved_space_kbytes; 2008 }; 2009 2010 struct _vcs_dpi_dml_display_plane_rq_regs_st { 2011 dml_uint_t chunk_size; 2012 dml_uint_t min_chunk_size; 2013 dml_uint_t meta_chunk_size; 2014 dml_uint_t min_meta_chunk_size; 2015 dml_uint_t dpte_group_size; 2016 dml_uint_t mpte_group_size; 2017 dml_uint_t swath_height; 2018 dml_uint_t pte_row_height_linear; 2019 }; 2020 2021 struct _vcs_dpi_dml_display_rq_regs_st { 2022 dml_display_plane_rq_regs_st rq_regs_l; 2023 dml_display_plane_rq_regs_st rq_regs_c; 2024 dml_uint_t drq_expansion_mode; 2025 dml_uint_t prq_expansion_mode; 2026 dml_uint_t mrq_expansion_mode; 2027 dml_uint_t crq_expansion_mode; 2028 dml_uint_t plane1_base_address; 2029 }; 2030 2031 #endif 2032