| /linux/drivers/gpu/drm/radeon/ |
| H A D | rv740_dpm.c | 123 struct atom_clock_dividers dividers; in rv740_populate_sclk_value() local
136 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
140 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
142 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
147 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
148 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
159 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
198 struct atom_clock_dividers dividers; in rv740_populate_mclk_value() local
204 memory_clock, false, ÷rs); in rv740_populate_mclk_value()
208 ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in rv740_populate_mclk_value()
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| H A D | rv730_dpm.c | 42 struct atom_clock_dividers dividers; in rv730_populate_sclk_value() local
55 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
59 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
61 if (dividers.enable_post_div) in rv730_populate_sclk_value()
62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
63 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
72 if (dividers.enable_post_div) in rv730_populate_sclk_value()
77 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
78 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
79 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
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| H A D | rv6xx_dpm.c | 142 struct atom_clock_dividers dividers; in rv6xx_convert_clock_to_stepping() local
145 clock, false, ÷rs); in rv6xx_convert_clock_to_stepping()
149 if (dividers.enable_post_div) in rv6xx_convert_clock_to_stepping()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
526 struct atom_clock_dividers *dividers, in rv6xx_calculate_vco_frequency() argument
529 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
530 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
553 struct atom_clock_dividers dividers; in rv6xx_program_engine_spread_spectrum() local
560 …if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) == 0) { in rv6xx_program_engine_spread_spectrum()
561 vco_freq = rv6xx_calculate_vco_frequency(ref_clk, ÷rs, in rv6xx_program_engine_spread_spectrum()
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| H A D | rv770_dpm.c | 322 struct atom_clock_dividers *dividers, in rv770_calculate_fractional_mpll_feedback_divider() argument
334 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
335 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
404 struct atom_clock_dividers dividers; in rv770_populate_mclk_value() local
412 memory_clock, false, ÷rs); in rv770_populate_mclk_value()
416 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
421 ÷rs, &clkf, &clkfrac); in rv770_populate_mclk_value()
423 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
434 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
440 if (dividers.vco_mode) in rv770_populate_mclk_value()
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| H A D | cypress_dpm.c | 493 struct atom_clock_dividers dividers; in cypress_populate_mclk_value() local
500 memory_clock, strobe_mode, ÷rs); in cypress_populate_mclk_value()
508 dividers.post_div = 1; in cypress_populate_mclk_value()
511 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in cypress_populate_mclk_value()
518 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
519 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in cypress_populate_mclk_value()
520 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); in cypress_populate_mclk_value()
521 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); in cypress_populate_mclk_value()
524 if (dividers.vco_mode) in cypress_populate_mclk_value()
535 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
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| H A D | rs780_dpm.c | 78 struct atom_clock_dividers dividers; in rs780_initialize_dpm_power_state() local
83 default_state->sclk_low, false, ÷rs); in rs780_initialize_dpm_power_state()
87 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); in rs780_initialize_dpm_power_state()
88 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
91 if (dividers.enable_post_div) in rs780_initialize_dpm_power_state()
1032 struct atom_clock_dividers dividers; in rs780_dpm_force_performance_level() local
1043 ps->sclk_high, false, ÷rs); in rs780_dpm_force_performance_level()
1047 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1050 ps->sclk_low, false, ÷rs); in rs780_dpm_force_performance_level()
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| H A D | radeon_atombios.c | 2829 struct atom_clock_dividers *dividers) in radeon_atom_get_clock_dividers() argument
2836 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in radeon_atom_get_clock_dividers()
2849 dividers->post_div = args.v1.ucPostDiv; in radeon_atom_get_clock_dividers()
2850 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2851 dividers->enable_post_div = true; in radeon_atom_get_clock_dividers()
2863 dividers->post_div = args.v2.ucPostDiv; in radeon_atom_get_clock_dividers()
2864 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); in radeon_atom_get_clock_dividers()
2865 dividers->ref_div = args.v2.ucAction; in radeon_atom_get_clock_dividers()
2867 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? in radeon_atom_get_clock_dividers()
2869 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; in radeon_atom_get_clock_dividers()
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| H A D | ni_dpm.c | 2004 struct atom_clock_dividers dividers; in ni_calculate_sclk_params() local
2018 engine_clock, false, ÷rs); in ni_calculate_sclk_params()
2022 reference_divider = 1 + dividers.ref_div; in ni_calculate_sclk_params()
2025 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()
2030 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in ni_calculate_sclk_params()
2031 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in ni_calculate_sclk_params()
2042 u32 vco_freq = engine_clock * dividers.post_div; in ni_calculate_sclk_params()
2177 struct atom_clock_dividers dividers; in ni_populate_mclk_value() local
2184 memory_clock, strobe_mode, ÷rs); in ni_populate_mclk_value()
2192 dividers.post_div = 1; in ni_populate_mclk_value()
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| H A D | kv_dpm.c | 379 struct atom_clock_dividers dividers; in kv_set_divider_value() local
383 sclk, false, ÷rs); in kv_set_divider_value()
387 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
664 struct atom_clock_dividers dividers; in kv_populate_uvd_table() local
687 table->entries[i].vclk, false, ÷rs); in kv_populate_uvd_table()
690 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
693 table->entries[i].dclk, false, ÷rs); in kv_populate_uvd_table()
696 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
737 struct atom_clock_dividers dividers; in kv_populate_vce_table() local
755 table->entries[i].evclk, false, ÷rs); in kv_populate_vce_table()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | polaris10_smumgr.c | 895 struct pp_atomctrl_clock_dividers_ai dividers; in polaris10_calculate_sclk_params() local
904 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in polaris10_calculate_sclk_params()
906 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in polaris10_calculate_sclk_params()
907 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in polaris10_calculate_sclk_params()
908 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in polaris10_calculate_sclk_params()
909 sclk_setting->PllRange = dividers.ucSclkPllRange; in polaris10_calculate_sclk_params()
911 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in polaris10_calculate_sclk_params()
913 sclk_setting->SSc_En = dividers.ucSscEnable; in polaris10_calculate_sclk_params()
914 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in polaris10_calculate_sclk_params()
915 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; in polaris10_calculate_sclk_params()
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| H A D | vegam_smumgr.c | 724 struct pp_atomctrl_clock_dividers_ai dividers; in vegam_calculate_sclk_params() local
733 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in vegam_calculate_sclk_params()
735 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in vegam_calculate_sclk_params()
736 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in vegam_calculate_sclk_params()
737 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in vegam_calculate_sclk_params()
738 sclk_setting->PllRange = dividers.ucSclkPllRange; in vegam_calculate_sclk_params()
740 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in vegam_calculate_sclk_params()
742 sclk_setting->SSc_En = dividers.ucSscEnable; in vegam_calculate_sclk_params()
743 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in vegam_calculate_sclk_params()
744 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; in vegam_calculate_sclk_params()
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| H A D | fiji_smumgr.c | 859 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_calculate_sclk_params() local
871 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); in fiji_calculate_sclk_params()
879 ref_divider = 1 + dividers.uc_pll_ref_div; in fiji_calculate_sclk_params()
882 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in fiji_calculate_sclk_params()
886 SPLL_REF_DIV, dividers.uc_pll_ref_div); in fiji_calculate_sclk_params()
888 SPLL_PDIV_A, dividers.uc_pll_post_div); in fiji_calculate_sclk_params()
902 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in fiji_calculate_sclk_params()
931 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in fiji_calculate_sclk_params()
1303 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_populate_smc_acpi_level() local
1334 table->ACPILevel.SclkFrequency, ÷rs); in fiji_populate_smc_acpi_level()
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| H A D | tonga_smumgr.c | 542 pp_atomctrl_clock_dividers_vi dividers; in tonga_calculate_sclk_params() local
554 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in tonga_calculate_sclk_params()
562 reference_divider = 1 + dividers.uc_pll_ref_div; in tonga_calculate_sclk_params()
565 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in tonga_calculate_sclk_params()
569 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in tonga_calculate_sclk_params()
571 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in tonga_calculate_sclk_params()
585 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in tonga_calculate_sclk_params()
611 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in tonga_calculate_sclk_params()
1180 struct pp_atomctrl_clock_dividers_vi dividers; in tonga_populate_smc_acpi_level() local
1199 table->ACPILevel.SclkFrequency, ÷rs); in tonga_populate_smc_acpi_level()
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| H A D | ci_smumgr.c | 301 struct pp_atomctrl_clock_dividers_vi dividers; in ci_calculate_sclk_params() local
313 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); in ci_calculate_sclk_params()
321 ref_divider = 1 + dividers.uc_pll_ref_div; in ci_calculate_sclk_params()
324 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in ci_calculate_sclk_params()
328 SPLL_REF_DIV, dividers.uc_pll_ref_div); in ci_calculate_sclk_params()
330 SPLL_PDIV_A, dividers.uc_pll_post_div); in ci_calculate_sclk_params()
343 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in ci_calculate_sclk_params()
366 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in ci_calculate_sclk_params()
1390 struct pp_atomctrl_clock_dividers_vi dividers; in ci_populate_smc_acpi_level() local
1413 table->ACPILevel.SclkFrequency, ÷rs); in ci_populate_smc_acpi_level()
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| H A D | iceland_smumgr.c | 799 pp_atomctrl_clock_dividers_vi dividers; in iceland_calculate_sclk_params() local
811 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in iceland_calculate_sclk_params()
819 reference_divider = 1 + dividers.uc_pll_ref_div; in iceland_calculate_sclk_params()
822 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in iceland_calculate_sclk_params()
826 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in iceland_calculate_sclk_params()
828 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in iceland_calculate_sclk_params()
842 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in iceland_calculate_sclk_params()
868 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in iceland_calculate_sclk_params()
1427 struct pp_atomctrl_clock_dividers_vi dividers; in iceland_populate_smc_acpi_level() local
1451 table->ACPILevel.SclkFrequency, ÷rs); in iceland_populate_smc_acpi_level()
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| /linux/arch/arm/boot/dts/ti/omap/ |
| H A D | omap2420-clocks.dtsi | 79 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
262 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
266 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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| H A D | omap446x-clocks.dtsi | 15 ti,dividers = <8>, <16>, <32>;
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| /linux/drivers/clk/mstar/ |
| H A D | Kconfig | 15 Support for the MPLL PLL and dividers block present on
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu8_hwmgr.c | 440 pp_atomctrl_clock_dividers_kong dividers; in smu8_upload_pptable_to_smu() local
485 ÷rs); in smu8_upload_pptable_to_smu()
488 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
502 ÷rs); in smu8_upload_pptable_to_smu()
505 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
516 ÷rs); in smu8_upload_pptable_to_smu()
519 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
528 ÷rs); in smu8_upload_pptable_to_smu()
531 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
542 ÷rs); in smu8_upload_pptable_to_smu()
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| H A D | vega10_hwmgr.c | 1502 struct pp_atomfwctrl_clock_dividers_soc15 dividers; in vega10_populate_single_lclk_level() local
1507 lclock, ÷rs), in vega10_populate_single_lclk_level()
1511 *curr_lclk_did = dividers.ulDid; in vega10_populate_single_lclk_level()
1620 struct pp_atomfwctrl_clock_dividers_soc15 dividers; in vega10_populate_single_gfx_level() local
1649 gfx_clock, ÷rs), in vega10_populate_single_gfx_level()
1655 cpu_to_le32(dividers.ulPll_fb_mult); in vega10_populate_single_gfx_level()
1657 current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; in vega10_populate_single_gfx_level()
1659 cpu_to_le32(dividers.ulPll_ss_fbsmult); in vega10_populate_single_gfx_level()
1661 cpu_to_le16(dividers.usPll_ss_slew_frac); in vega10_populate_single_gfx_level()
1662 current_gfxclk_level->Did = (uint8_t)(dividers.ulDid); in vega10_populate_single_gfx_level()
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| /linux/drivers/iio/afe/ |
| H A D | Kconfig | 13 that handles voltage dividers, current sense shunts and
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| /linux/drivers/gpu/drm/amd/pm/legacy-dpm/ |
| H A D | kv_dpm.c | 655 struct atom_clock_dividers dividers; in kv_set_divider_value() local
659 sclk, false, ÷rs); in kv_set_divider_value()
663 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
896 struct atom_clock_dividers dividers; in kv_populate_uvd_table() local
919 table->entries[i].vclk, false, ÷rs); in kv_populate_uvd_table()
922 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
925 table->entries[i].dclk, false, ÷rs); in kv_populate_uvd_table()
928 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
969 struct atom_clock_dividers dividers; in kv_populate_vce_table() local
987 table->entries[i].evclk, false, ÷rs); in kv_populate_vce_table()
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| /linux/drivers/clk/ti/ |
| H A D | clock.h | 120 int *dividers; member
162 const int *dividers; member
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-iio-frequency-adf4350 | 8 that is used to compute the various dividers, is able to
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| H A D | sysfs-bus-iio-frequency-ad9523 | 28 functionality. All dividers are reset and the channels start
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