Home
last modified time | relevance | path

Searched refs:div_clks (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/clk/samsung/
H A Dclk-exynosautov920.c997 .div_clks = top_div_clks,
1127 .div_clks = cpucl0_div_clks,
1229 .div_clks = cpucl1_div_clks,
1331 .div_clks = cpucl2_div_clks,
1480 .div_clks = peric0_div_clks,
1620 .div_clks = peric1_div_clks,
1672 .div_clks = misc_div_clks,
1710 .div_clks = hsi0_div_clks,
1819 .div_clks = hsi2_div_clks,
1860 .div_clks = m2m_div_clks,
[all …]
H A Dclk-exynos850.c567 .div_clks = top_div_clks,
711 .div_clks = apm_div_clks,
994 .div_clks = aud_div_clks,
1097 .div_clks = cmgp_div_clks,
1299 .div_clks = cpucl0_div_clks,
1454 .div_clks = cpucl1_div_clks,
1562 .div_clks = g3d_div_clks,
1796 .div_clks = is_div_clks,
1905 .div_clks = mfcmscl_div_clks,
2086 .div_clks = peri_div_clks,
[all …]
H A Dclk-exynos5-subcmu.h14 const struct samsung_div_clock *div_clks; member
H A Dclk-artpec8.c370 .div_clks = cmu_cmu_div_clks,
406 .div_clks = cmu_bus_div_clks,
442 .div_clks = cmu_core_div_clks,
548 .div_clks = cmu_cpucl_div_clks,
778 .div_clks = cmu_fsys_div_clks,
980 .div_clks = cmu_peri_div_clks,
H A Dclk-exynos3250.c328 static const struct samsung_div_clock div_clks[] __initconst = { variable
804 .div_clks = div_clks,
805 .nr_div_clks = ARRAY_SIZE(div_clks),
926 .div_clks = dmc_div_clks,
1068 .div_clks = isp_div_clks,
H A Dclk-exynosautov9.c949 .div_clks = top_div_clks,
1011 .div_clks = busmc_div_clks,
1069 .div_clks = core_div_clks,
1148 .div_clks = dpum_div_clks,
1515 .div_clks = fsys1_div_clks,
1837 .div_clks = peric0_div_clks,
2092 .div_clks = peric1_div_clks,
H A Dclk-fsd.c307 .div_clks = cmu_div_clks,
670 .div_clks = peric_div_clks,
969 .div_clks = fsys0_div_clks,
1141 .div_clks = fsys1_div_clks,
1420 .div_clks = imem_div_clks,
1545 .div_clks = mfc_div_clks,
1749 .div_clks = cam_csi_div_clks,
H A Dclk-exynos5433.c813 .div_clks = top_div_clks,
896 .div_clks = cpif_div_clks,
1548 .div_clks = mif_div_clks,
1749 .div_clks = peric_div_clks,
2478 .div_clks = g2d_div_clks,
2902 .div_clks = disp_div_clks,
3074 .div_clks = aud_div_clks,
3208 .div_clks = bus##id##_div_clks, \
3359 .div_clks = g3d_div_clks,
3709 .div_clks = apollo_div_clks,
[all …]
H A Dclk-exynos7870.c728 .div_clks = mif_div_clks,
1006 .div_clks = dispaud_div_clks,
1243 .div_clks = g3d_div_clks,
1430 .div_clks = isp_div_clks,
1519 .div_clks = mfcmscl_div_clks,
H A Dclk-exynos5-subcmu.c109 samsung_clk_register_div(ctx, info->div_clks, info->nr_div_clks); in exynos5_subcmu_probe()
H A Dclk-exynos2200.c1921 .div_clks = top_div_clks,
2335 .div_clks = alive_div_clks,
2728 .div_clks = cmgp_div_clks,
2877 .div_clks = hsi0_div_clks,
2985 .div_clks = peric0_div_clks,
3201 .div_clks = peric1_div_clks,
3546 .div_clks = peric2_div_clks,
3868 .div_clks = vts_div_clks,
H A Dclk.c476 if (cmu->div_clks) in samsung_cmu_register_clocks()
477 samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks); in samsung_cmu_register_clocks()
H A Dclk-exynos7885.c347 .div_clks = top_div_clks,
675 .div_clks = core_div_clks,
H A Dclk-exynos5420.c1330 .div_clks = exynos5x_disp_div_clks,
1340 .div_clks = exynos5x_gsc_div_clks,
1358 .div_clks = exynos5x_mfc_div_clks,
1368 .div_clks = exynos5x_mscl_div_clks,
H A Dclk-gs101.c1431 .div_clks = top_div_clks,
1918 .div_clks = apm_div_clks,
2198 .div_clks = dpu_div_clks,
2666 .div_clks = hsi0_div_clks,
3730 .div_clks = misc_div_clks,
4338 .div_clks = peric0_div_clks,
4692 .div_clks = peric1_div_clks,
H A Dclk.h369 const struct samsung_div_clock *div_clks; member
H A Dclk-exynos4.c1274 .div_clks = exynos4_div_clks,
1287 .div_clks = exynos4210_div_clks,
1302 .div_clks = exynos4x12_div_clks,
H A Dclk-exynos990.c1164 .div_clks = top_div_clks,
1870 .div_clks = peric0_div_clks,
2468 .div_clks = peric1_div_clks,
H A Dclk-exynos8895.c1292 .div_clks = top_div_clks,
/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c823 static struct tegra_periph_init_data div_clks[] = { variable
919 for (i = 0; i < ARRAY_SIZE(div_clks); i++) { in div_clk_init()
922 data = div_clks + i; in div_clk_init()