Searched refs:div4 (Results 1 – 7 of 7) sorted by relevance
43 - clock-names: shall be "pll0_sysclk3", "div4.5"71 div4p5_clk: div4.5 {81 clock-names = "pll0_sysclk3", "div4.5";
122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \ argument124 UNIPHIER_CLK_DIV(parent, div4)
400 div4p5_clk: div4.5 {410 clock-names = "pll0_sysclk3", "div4.5";
316 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {325 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
370 dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {379 dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
43 divclk4: div4-clk {
551 #define div4(v) ((v)>>2) macro