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Searched refs:div1 (Results 1 – 25 of 25) sorted by relevance

/linux/arch/sh/lib/
H A Dudivsi3.S16 div1 r5,r4
18 div1 r5,r4; div1 r5,r4; div1 r5,r4
19 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
22 div1 r5,r4; rotcl r0
23 div1 r5,r4; rotcl r0
24 div1 r5,r4; rotcl r0
25 rts; div1 r5,r4
38 div1 r5,r4
44 div1 r5,r4
H A Dudivsi3_i4i-Os.S38 div1 r5,r4
40 div1 r5,r4
41 div1 r5,r4
43 div1 r5,r4
48 div1 r5,r4
50 div1 r5,r4
58 div1 r5,r4
60 div1 r5,r4; div1 r5,r4; div1 r5,r4
61 div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
65 div1 r5,r4
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H A Dudivsi3_i4i.S55 div1 r5,r0
57 div1 r5,r0
58 div1 r5,r0
60 div1 r5,r0
102 div1 r5,r0
109 div1 r5,r0
112 div1 r5,r0
115 div1 r5,r0
118 div1 r5,r0
120 div1 r5,r0
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H A Ddiv64.S26 div1 r6, r3
36 div1 r6, r1
H A Dudiv_qrnnd.S29 div1 r6,r0
/linux/drivers/clk/
H A Dclk-vt8500.c457 int div1, div2; in wm8750_find_pll_bits() local
463 for (div1 = 1; div1 >= 0; div1--) in wm8750_find_pll_bits()
466 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); in wm8750_find_pll_bits()
472 *filter = wm8750_get_filter(parent_rate, div1); in wm8750_find_pll_bits()
474 *divisor1 = div1; in wm8750_find_pll_bits()
482 *divisor1 = div1; in wm8750_find_pll_bits()
505 int div1, div2; in wm8850_find_pll_bits() local
511 for (div1 = 1; div1 >= 0; div1--) in wm8850_find_pll_bits()
515 ((div1 + 1) * (1 << div2)); in wm8850_find_pll_bits()
522 *divisor1 = div1; in wm8850_find_pll_bits()
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/linux/drivers/clk/uniphier/
H A Dclk-uniphier.h110 #define UNIPHIER_CLK_DIV2(parent, div0, div1) \ argument
112 UNIPHIER_CLK_DIV(parent, div1)
114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ argument
115 UNIPHIER_CLK_DIV2(parent, div0, div1), \
118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ argument
119 UNIPHIER_CLK_DIV2(parent, div0, div1), \
122 #define UNIPHIER_CLK_DIV5(parent, div0, div1, div2, div3, div4) \ argument
123 UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3), \
/linux/drivers/clk/samsung/
H A Dclk-cpu.c203 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
222 div1 = cfg_data->div1; in exynos_cpuclk_pre_rate_change()
224 div1 = readl(base + regs->div_cpu1) & in exynos_cpuclk_pre_rate_change()
265 writel(div1, base + regs->div_cpu1); in exynos_cpuclk_pre_rate_change()
330 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
347 div1 = cfg_data->div1; in exynos5433_cpuclk_pre_rate_change()
377 writel(div1, base + regs->div_cpu1); in exynos5433_cpuclk_pre_rate_change()
H A Dclk-cpu.h45 unsigned long div1; member
/linux/drivers/media/tuners/
H A Dmt2131.c89 u32 div1, num1, div2, num2; in mt2131_set_params() local
106 div1 = num1 / 8192; in mt2131_set_params()
137 b[3] = div1; in mt2131_set_params()
146 (int)div1, (int)num1, (int)div2, (int)num2); in mt2131_set_params()
H A Dmt2060.c196 u32 div1,num1,div2,num2; in mt2060_set_params() local
228 div1 = num1 / 64; in mt2060_set_params()
249 b[2] = div1; in mt2060_set_params()
256 dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2); in mt2060_set_params()
/linux/arch/mips/alchemy/common/
H A Dclock.c383 long div1, div2; in alchemy_calc_div() local
385 div1 = prate / rate; in alchemy_calc_div()
386 if ((prate / div1) > rate) in alchemy_calc_div()
387 div1++; in alchemy_calc_div()
390 if (div1 & 1) in alchemy_calc_div()
391 div1++; /* stay <=prate */ in alchemy_calc_div()
394 div2 = (div1 / scale) - 1; /* value to write to register */ in alchemy_calc_div()
401 div1 = ((div2 + 1) * scale); in alchemy_calc_div()
402 return div1; in alchemy_calc_div()
/linux/arch/microblaze/lib/
H A Dmodsi3.S39 div1: label
41 bgeid r5, div1
H A Ddivsi3.S39 div1: label
41 bgtid r5, div1
H A Dudivsi3.S53 div1: label
55 bgtid r5, div1
H A Dumodsi3.S55 div1: label
57 bgeid r5, div1
/linux/drivers/clk/sophgo/
H A Dclk-sg2044-pll.c173 unsigned int div1, div2; in sg2042_pll_compute_postdiv() local
178 for_each_pll_limit_range(div1, &limits[PLL_LIMIT_POSTDIV1]) { in sg2042_pll_compute_postdiv()
181 div1, div2); in sg2042_pll_compute_postdiv()
187 best_div1 = div1; in sg2042_pll_compute_postdiv()
/linux/drivers/clk/x86/
H A Dclk-cgu.c396 unsigned int div0, div1, exdiv; in lgm_clk_ddiv_recalc_rate() local
401 div1 = lgm_get_clk_val(ddiv->membase, ddiv->reg, in lgm_clk_ddiv_recalc_rate()
407 do_div(prate, div1); in lgm_clk_ddiv_recalc_rate()
/linux/drivers/media/dvb-frontends/
H A Dstb0899_algo.c1274 int div1, div2, rem1, rem2; in stb0899_dvbs2_get_srate() local
1276 div1 = config->btr_nco_bits / 2; in stb0899_dvbs2_get_srate()
1277 div2 = config->btr_nco_bits - div1 - 1; in stb0899_dvbs2_get_srate()
1285 intval1 = internal->master_clk / (1 << div1); in stb0899_dvbs2_get_srate()
1288 rem1 = internal->master_clk % (1 << div1); in stb0899_dvbs2_get_srate()
1291 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1)); in stb0899_dvbs2_get_srate()
/linux/drivers/comedi/drivers/
H A Dadl_pci9118.c532 unsigned int *div1, unsigned int *div2, in pci9118_calc_divisors() argument
538 *div1 = *tim2 / pacer->osc_base; /* convert timer (burst) */ in pci9118_calc_divisors()
540 *div2 = *div2 / *div1; /* major timer is c1*c2 */ in pci9118_calc_divisors()
544 *tim2 = *div1 * pacer->osc_base; /* real convert timer */ in pci9118_calc_divisors()
552 *tim1 = *div1 * *div2 * pacer->osc_base; in pci9118_calc_divisors()
/linux/drivers/i2c/busses/
H A Di2c-sprd.c338 u32 div1 = I2C_ADDR_DVD1_CALC(high, low); in sprd_i2c_set_clk() local
341 writel(div1, i2c_dev->base + ADDR_DVD1); in sprd_i2c_set_clk()
/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt41 "mult-div1" - contains the multiplier / divider register base address
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgf119.c290 u32 div1 = sor->asy.link == 3; in gf119_sor_clock() local
300 nvkm_mask(device, 0x612300 + soff, 0x00000707, (div2 << 8) | div1); in gf119_sor_clock()
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996-oneplus-common.dtsi34 div1_mclk: div1-clk {
H A Dapq8096-db820c.dts549 audio_mclk: clk-div1-state {