1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef DMUB_CMD_H
27 #define DMUB_CMD_H
28
29 #include <asm/byteorder.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
32 #include <linux/delay.h>
33
34 #include "atomfirmware.h"
35
36 //<DMUB_TYPES>==================================================================
37 /* Basic type definitions. */
38
39 #ifdef __forceinline
40 #undef __forceinline
41 #endif
42 #define __forceinline inline
43
44 /**
45 * Flag from driver to indicate that ABM should be disabled gradually
46 * by slowly reversing all backlight programming and pixel compensation.
47 */
48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
49
50 /**
51 * Flag from driver to indicate that ABM should be disabled immediately
52 * and undo all backlight programming and pixel compensation.
53 */
54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
55
56 /**
57 * Flag from driver to indicate that ABM should be disabled immediately
58 * and keep the current backlight programming and pixel compensation.
59 */
60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
61
62 /**
63 * Flag from driver to set the current ABM pipe index or ABM operating level.
64 */
65 #define SET_ABM_PIPE_NORMAL 1
66
67 /**
68 * Number of ambient light levels in ABM algorithm.
69 */
70 #define NUM_AMBI_LEVEL 5
71
72 /**
73 * Number of operating/aggression levels in ABM algorithm.
74 */
75 #define NUM_AGGR_LEVEL 4
76
77 /**
78 * Number of segments in the gamma curve.
79 */
80 #define NUM_POWER_FN_SEGS 8
81
82 /**
83 * Number of segments in the backlight curve.
84 */
85 #define NUM_BL_CURVE_SEGS 16
86
87 /**
88 * Maximum number of segments in ABM ACE curve.
89 */
90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64
91
92 /**
93 * Maximum number of bins in ABM histogram.
94 */
95 #define ABM_MAX_NUM_OF_HG_BINS 64
96
97 /* Maximum number of SubVP streams */
98 #define DMUB_MAX_SUBVP_STREAMS 2
99
100 /* Define max FPO streams as 4 for now. Current implementation today
101 * only supports 1, but could be more in the future. Reduce array
102 * size to ensure the command size remains less than 64 bytes if
103 * adding new fields.
104 */
105 #define DMUB_MAX_FPO_STREAMS 4
106
107 /* Define to ensure that the "common" members always appear in the same
108 * order in different structs for back compat purposes
109 */
110 #define COMMON_STREAM_STATIC_SUB_STATE \
111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \
112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \
113 struct dmub_fams2_cmd_drr_stream_static_state drr;
114
115 /* Maximum number of streams on any ASIC. */
116 #define DMUB_MAX_STREAMS 6
117
118 /* Maximum number of planes on any ASIC. */
119 #define DMUB_MAX_PLANES 6
120
121 /* Maximum number of phantom planes on any ASIC */
122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2)
123
124 /* Trace buffer offset for entry */
125 #define TRACE_BUFFER_ENTRY_OFFSET 16
126
127 /**
128 * Maximum number of dirty rects supported by FW.
129 */
130 #define DMUB_MAX_DIRTY_RECTS 3
131
132 /**
133 *
134 * PSR control version legacy
135 */
136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
137 /**
138 * PSR control version with multi edp support
139 */
140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
141
142 /**
143 *
144 * dirty rect cmd version legacy
145 */
146 #define DMUB_CMD_DIRTY_RECTS_VERSION_UNKNOWN 0x0
147 /**
148 * dirty rect cmd version with multi edp support
149 */
150 #define DMUB_CMD_DIRTY_RECTS_VERSION_1 0x1
151 /**
152 * dirty rect cmd version with external monitor support
153 */
154 #define DMUB_CMD_DIRTY_RECTS_VERSION_2 0x2
155
156 /**
157 *
158 * Cursor update cmd version legacy
159 */
160 #define DMUB_CMD_CURSOR_UPDATE_VERSION_UNKNOWN 0x0
161 /**
162 * Cursor update cmd version with multi edp support
163 */
164 #define DMUB_CMD_CURSOR_UPDATE_VERSION_1 0x1
165 /**
166 * Cursor update cmd version with external monitor support
167 */
168 #define DMUB_CMD_CURSOR_UPDATE_VERSION_2 0x2
169
170 /**
171 * ABM control version legacy
172 */
173 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
174
175 /**
176 * ABM control version with multi edp support
177 */
178 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
179
180 /**
181 * Physical framebuffer address location, 64-bit.
182 */
183 #ifndef PHYSICAL_ADDRESS_LOC
184 #define PHYSICAL_ADDRESS_LOC union large_integer
185 #endif
186
187 /**
188 * OS/FW agnostic memcpy
189 */
190 #ifndef dmub_memcpy
191 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
192 #endif
193
194 /**
195 * OS/FW agnostic memset
196 */
197 #ifndef dmub_memset
198 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
199 #endif
200
201 /**
202 * OS/FW agnostic memcmp
203 */
204 #ifndef dmub_memcmp
205 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes))
206 #endif
207
208 /**
209 * OS/FW agnostic udelay
210 */
211 #ifndef dmub_udelay
212 #define dmub_udelay(microseconds) udelay(microseconds)
213 #endif
214
215 #pragma pack(push, 1)
216 #define ABM_NUM_OF_ACE_SEGMENTS 5
217
218 /**
219 * Debug FW state offset
220 */
221 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300
222
223 union abm_flags {
224 struct {
225 /**
226 * @abm_enabled: Indicates if ABM is enabled.
227 */
228 unsigned int abm_enabled : 1;
229
230 /**
231 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled.
232 */
233 unsigned int disable_abm_requested : 1;
234
235 /**
236 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately.
237 */
238 unsigned int disable_abm_immediately : 1;
239
240 /**
241 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM
242 * to be disabled immediately and keep gain.
243 */
244 unsigned int disable_abm_immediate_keep_gain : 1;
245
246 /**
247 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled.
248 */
249 unsigned int fractional_pwm : 1;
250
251 /**
252 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment
253 * of user backlight level.
254 */
255 unsigned int abm_gradual_bl_change : 1;
256
257 /**
258 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady
259 */
260 unsigned int abm_new_frame : 1;
261
262 /**
263 * @vb_scaling_enabled: Indicates variBright Scaling Enable
264 */
265 unsigned int vb_scaling_enabled : 1;
266 } bitfields;
267
268 unsigned int u32All;
269 };
270
271 struct abm_save_restore {
272 /**
273 * @flags: Misc. ABM flags.
274 */
275 union abm_flags flags;
276
277 /**
278 * @pause: true: pause ABM and get state
279 * false: unpause ABM after setting state
280 */
281 uint32_t pause;
282
283 /**
284 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13)
285 */
286 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];
287
288 /**
289 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6)
290 */
291 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];
292
293 /**
294 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6)
295 */
296 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];
297
298
299 /**
300 * @knee_threshold: Current x-position of ACE knee (u0.16).
301 */
302 uint32_t knee_threshold;
303 /**
304 * @current_gain: Current backlight reduction (u16.16).
305 */
306 uint32_t current_gain;
307 /**
308 * @curr_bl_level: Current actual backlight level converging to target backlight level.
309 */
310 uint16_t curr_bl_level;
311
312 /**
313 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user.
314 */
315 uint16_t curr_user_bl_level;
316
317 };
318
319 /**
320 * union dmub_addr - DMUB physical/virtual 64-bit address.
321 */
322 union dmub_addr {
323 struct {
324 uint32_t low_part; /**< Lower 32 bits */
325 uint32_t high_part; /**< Upper 32 bits */
326 } u; /*<< Low/high bit access */
327 uint64_t quad_part; /*<< 64 bit address */
328 };
329
330 /* Flattened structure containing SOC BB parameters stored in the VBIOS
331 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters.
332 * This also prevents alighment issues when new parameters are added to the SoC BB.
333 * The following parameters should be added since these values can't be obtained elsewhere:
334 * -dml2_soc_power_management_parameters
335 * -dml2_soc_vmin_clock_limits
336 */
337 struct dmub_soc_bb_params {
338 uint32_t dram_clk_change_blackout_ns;
339 uint32_t dram_clk_change_read_only_ns;
340 uint32_t dram_clk_change_write_only_ns;
341 uint32_t fclk_change_blackout_ns;
342 uint32_t g7_ppt_blackout_ns;
343 uint32_t stutter_enter_plus_exit_latency_ns;
344 uint32_t stutter_exit_latency_ns;
345 uint32_t z8_stutter_enter_plus_exit_latency_ns;
346 uint32_t z8_stutter_exit_latency_ns;
347 uint32_t z8_min_idle_time_ns;
348 uint32_t type_b_dram_clk_change_blackout_ns;
349 uint32_t type_b_ppt_blackout_ns;
350 uint32_t vmin_limit_dispclk_khz;
351 uint32_t vmin_limit_dcfclk_khz;
352 uint32_t g7_temperature_read_blackout_ns;
353 };
354 #pragma pack(pop)
355
356 /**
357 * Dirty rect definition.
358 */
359 struct dmub_rect {
360 /**
361 * Dirty rect x offset.
362 */
363 uint32_t x;
364
365 /**
366 * Dirty rect y offset.
367 */
368 uint32_t y;
369
370 /**
371 * Dirty rect width.
372 */
373 uint32_t width;
374
375 /**
376 * Dirty rect height.
377 */
378 uint32_t height;
379 };
380
381 /**
382 * Flags that can be set by driver to change some PSR behaviour.
383 */
384 union dmub_psr_debug_flags {
385 /**
386 * Debug flags.
387 */
388 struct {
389 /**
390 * Enable visual confirm in FW.
391 */
392 uint32_t visual_confirm : 1;
393
394 /**
395 * Force all selective updates to bw full frame updates.
396 */
397 uint32_t force_full_frame_update : 1;
398
399 /**
400 * Use HW Lock Mgr object to do HW locking in FW.
401 */
402 uint32_t use_hw_lock_mgr : 1;
403
404 /**
405 * Use TPS3 signal when restore main link.
406 */
407 uint32_t force_wakeup_by_tps3 : 1;
408
409 /**
410 * Back to back flip, therefore cannot power down PHY
411 */
412 uint32_t back_to_back_flip : 1;
413
414 /**
415 * Enable visual confirm for IPS
416 */
417 uint32_t enable_ips_visual_confirm : 1;
418 } bitfields;
419
420 /**
421 * Union for debug flags.
422 */
423 uint32_t u32All;
424 };
425
426 /**
427 * Flags that can be set by driver to change some Replay behaviour.
428 */
429 union replay_debug_flags {
430 struct {
431 /**
432 * 0x1 (bit 0)
433 * Enable visual confirm in FW.
434 */
435 uint32_t visual_confirm : 1;
436
437 /**
438 * 0x2 (bit 1)
439 * @skip_crc: Set if need to skip CRC.
440 */
441 uint32_t skip_crc : 1;
442
443 /**
444 * 0x4 (bit 2)
445 * @force_link_power_on: Force disable ALPM control
446 */
447 uint32_t force_link_power_on : 1;
448
449 /**
450 * 0x8 (bit 3)
451 * @force_phy_power_on: Force phy power on
452 */
453 uint32_t force_phy_power_on : 1;
454
455 /**
456 * 0x10 (bit 4)
457 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync
458 */
459 uint32_t timing_resync_disabled : 1;
460
461 /**
462 * 0x20 (bit 5)
463 * @skip_crtc_disabled: CRTC disable skipped
464 */
465 uint32_t skip_crtc_disabled : 1;
466
467 /**
468 * 0x40 (bit 6)
469 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode
470 */
471 uint32_t force_defer_one_frame_update : 1;
472
473 /**
474 * 0x80 (bit 7)
475 * @disable_delay_alpm_on: Force disable delay alpm on
476 */
477 uint32_t disable_delay_alpm_on : 1;
478
479 /**
480 * 0x100 (bit 8)
481 * @disable_desync_error_check: Force disable desync error check
482 */
483 uint32_t disable_desync_error_check : 1;
484
485 /**
486 * 0x200 (bit 9)
487 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady
488 */
489 uint32_t force_self_update_when_abm_non_steady : 1;
490
491 /**
492 * 0x400 (bit 10)
493 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS
494 * If we enter IPS2, the Visual confirm bar will change to yellow
495 */
496 uint32_t enable_ips_visual_confirm : 1;
497
498 /**
499 * 0x800 (bit 11)
500 * @enable_ips_residency_profiling: Enable IPS residency profiling
501 */
502 uint32_t enable_ips_residency_profiling : 1;
503
504 /**
505 * 0x1000 (bit 12)
506 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check
507 */
508 uint32_t enable_coasting_vtotal_check : 1;
509 /**
510 * 0x2000 (bit 13)
511 * @enable_visual_confirm_debug: Enable Visual Confirm Debug
512 */
513 uint32_t enable_visual_confirm_debug : 1;
514
515 /**
516 * 0x4000 (bit 14)
517 * @debug_log_enabled: Debug Log Enabled
518 */
519 uint32_t debug_log_enabled : 1;
520
521 /**
522 * 0x8000 (bit 15)
523 * @enable_sub_feature_visual_confirm: Enable Sub Feature Visual Confirm
524 */
525 uint32_t enable_sub_feature_visual_confirm : 1;
526
527 uint32_t reserved : 16;
528 } bitfields;
529
530 uint32_t u32All;
531 };
532
533 /**
534 * Flags record error state.
535 */
536 union replay_visual_confirm_error_state_flags {
537 struct {
538 /**
539 * 0x1 (bit 0) - Desync Error flag.
540 */
541 uint32_t desync_error : 1;
542
543 /**
544 * 0x2 (bit 1) - State Transition Error flag.
545 */
546 uint32_t state_transition_error : 1;
547
548 /**
549 * 0x4 (bit 2) - Crc Error flag
550 */
551 uint32_t crc_error : 1;
552
553 /**
554 * 0x8 (bit 3) - Reserved
555 */
556 uint32_t reserved_3 : 1;
557
558 /**
559 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write.
560 * Added new debug flag to control DPCD.
561 */
562 uint32_t incorrect_vtotal_in_static_screen : 1;
563
564 /**
565 * 0x20 (bit 5) - No doubled Refresh Rate.
566 */
567 uint32_t no_double_rr : 1;
568
569 /**
570 * Reserved bit 6-7
571 */
572 uint32_t reserved_6_7 : 2;
573
574 /**
575 * Reserved bit 9-31
576 */
577 uint32_t reserved_9_31 : 24;
578 } bitfields;
579
580 uint32_t u32All;
581 };
582
583 union replay_hw_flags {
584 struct {
585 /**
586 * @allow_alpm_fw_standby_mode: To indicate whether the
587 * ALPM FW standby mode is allowed
588 */
589 uint32_t allow_alpm_fw_standby_mode : 1;
590
591 /*
592 * @dsc_enable_status: DSC enable status in driver
593 */
594 uint32_t dsc_enable_status : 1;
595
596 /**
597 * @fec_enable_status: receive fec enable/disable status from driver
598 */
599 uint32_t fec_enable_status : 1;
600
601 /*
602 * @smu_optimizations_en: SMU power optimization.
603 * Only when active display is Replay capable and display enters Replay.
604 * Trigger interrupt to SMU to powerup/down.
605 */
606 uint32_t smu_optimizations_en : 1;
607
608 /**
609 * @phy_power_state: Indicates current phy power state
610 */
611 uint32_t phy_power_state : 1;
612
613 /**
614 * @link_power_state: Indicates current link power state
615 */
616 uint32_t link_power_state : 1;
617 /**
618 * Use TPS3 signal when restore main link.
619 */
620 uint32_t force_wakeup_by_tps3 : 1;
621 /**
622 * @is_alpm_initialized: Indicates whether ALPM is initialized
623 */
624 uint32_t is_alpm_initialized : 1;
625
626 /**
627 * @alpm_mode: Indicates ALPM mode selected
628 */
629 uint32_t alpm_mode : 2;
630 } bitfields;
631
632 uint32_t u32All;
633 };
634
635 /**
636 * Flags that can be set by driver to change some Panel Replay behaviour.
637 */
638 union pr_debug_flags {
639 struct {
640 /**
641 * 0x1 (bit 0)
642 * Enable visual confirm in FW.
643 */
644 uint32_t visual_confirm : 1;
645
646 /**
647 * 0x2 (bit 1)
648 * @skip_crc: Set if need to skip CRC.
649 */
650 uint32_t skip_crc : 1;
651
652 /**
653 * 0x4 (bit 2)
654 * @force_link_power_on: Force disable ALPM control
655 */
656 uint32_t force_link_power_on : 1;
657
658 /**
659 * 0x8 (bit 3)
660 * @force_phy_power_on: Force phy power on
661 */
662 uint32_t force_phy_power_on : 1;
663
664 /**
665 * 0x10 (bit 4)
666 * @visual_confirm_rate_control: Enable Visual Confirm rate control detection
667 */
668 uint32_t visual_confirm_rate_control : 1;
669
670 /**
671 * 0x20 (bit 5)
672 * @force_full_frame_update: Force all selective updates to be full frame updates
673 */
674 uint32_t force_full_frame_update : 1;
675
676 /**
677 * 0x40 (bit 6)
678 * @force_dpg_on: Force DPG on
679 */
680 uint32_t force_dpg_on : 1;
681
682 /**
683 * 0x80 (bit 7)
684 * @force_hubp_on: Force Hubp on
685 */
686 uint32_t force_hubp_on : 1;
687
688 uint32_t reserved : 24;
689 } bitfields;
690
691 uint32_t u32All;
692 };
693
694 union pr_hw_flags {
695 struct {
696 /**
697 * @allow_alpm_fw_standby_mode: To indicate whether the
698 * ALPM FW standby mode is allowed
699 */
700 uint32_t allow_alpm_fw_standby_mode : 1;
701
702 /*
703 * @dsc_enable_status: DSC enable status in driver
704 */
705 uint32_t dsc_enable_status : 1;
706
707 /**
708 * @fec_enable_status: receive fec enable/disable status from driver
709 */
710 uint32_t fec_enable_status : 1;
711 /*
712 * @smu_optimizations_en: SMU power optimization.
713 * Only when active display is Replay capable and display enters Replay.
714 * Trigger interrupt to SMU to powerup/down.
715 */
716 uint32_t smu_optimizations_en : 1;
717 /**
718 * @link_power_state: Indicates current link power state
719 */
720 uint32_t link_power_state : 1;
721 /**
722 * Use TPS3 signal when restore main link.
723 */
724 uint32_t force_wakeup_by_tps3 : 1;
725 /**
726 * @is_alpm_initialized: Indicates whether ALPM is initialized
727 */
728 uint32_t is_alpm_initialized : 1;
729 /**
730 * @alpm_mode: Indicates ALPM mode selected
731 */
732 uint32_t alpm_mode : 2;
733 uint32_t reserved : 23;
734 } bitfields;
735
736 uint32_t u32All;
737 };
738
739 /**
740 * Definition of Panel Replay ML Activity Options
741 */
742 enum pr_ml_activity_option {
743 OPTION_DEFAULT = 0x00, // VESA Option Default (1C)
744 OPTION_1A = 0x01, // VESA Option 1A
745 OPTION_1B = 0x02, // VESA Option 1B
746 OPTION_1C = 0x03, // VESA Option 1C
747 };
748
749 union fw_assisted_mclk_switch_version {
750 struct {
751 uint8_t minor : 5;
752 uint8_t major : 3;
753 };
754 uint8_t ver;
755 };
756
757 /**
758 * DMUB feature capabilities.
759 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
760 */
761 struct dmub_feature_caps {
762 /**
763 * Max PSR version supported by FW.
764 */
765 uint8_t psr;
766 uint8_t fw_assisted_mclk_switch_ver;
767 uint8_t reserved[4];
768 uint8_t subvp_psr_support;
769 uint8_t gecc_enable;
770 uint8_t replay_supported;
771 uint8_t replay_reserved[3];
772 uint8_t abm_aux_backlight_support;
773 uint8_t lsdma_support_in_dmu;
774 };
775
776 struct dmub_visual_confirm_color {
777 /**
778 * Maximum 10 bits color value
779 */
780 uint16_t color_r_cr;
781 uint16_t color_g_y;
782 uint16_t color_b_cb;
783 uint16_t panel_inst;
784 };
785
786 /**
787 * struct dmub_cursor_offload_pipe_data_dcn30_v1 - DCN30+ per pipe data.
788 */
789 struct dmub_cursor_offload_pipe_data_dcn30_v1 {
790 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS;
791 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH;
792 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16;
793 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16;
794 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16;
795 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16;
796 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16;
797 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16;
798 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13;
799 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1;
800 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3;
801 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1;
802 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2;
803 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5;
804 uint32_t reserved0[4];
805 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1;
806 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3;
807 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1;
808 uint32_t CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1;
809 uint32_t CNVC_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24;
810 uint32_t CNVC_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24;
811 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS : 16;
812 uint32_t CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE, : 16;
813 uint32_t reserved1[5];
814 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8;
815 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8;
816 uint32_t reserved2[3];
817 };
818
819 /**
820 * struct dmub_cursor_offload_pipe_data_dcn401_v1 - DCN401 per pipe data.
821 */
822 struct dmub_cursor_offload_pipe_data_dcn401_v1 {
823 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS;
824 uint32_t CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH;
825 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_WIDTH : 16;
826 uint32_t CURSOR0_0_CURSOR_SIZE__CURSOR_HEIGHT : 16;
827 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_X_POSITION : 16;
828 uint32_t CURSOR0_0_CURSOR_POSITION__CURSOR_Y_POSITION : 16;
829 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_X : 16;
830 uint32_t CURSOR0_0_CURSOR_HOT_SPOT__CURSOR_HOT_SPOT_Y : 16;
831 uint32_t CURSOR0_0_CURSOR_DST_OFFSET__CURSOR_DST_X_OFFSET : 13;
832 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_ENABLE : 1;
833 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_MODE : 3;
834 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY : 1;
835 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_PITCH : 2;
836 uint32_t CURSOR0_0_CURSOR_CONTROL__CURSOR_LINES_PER_CHUNK : 5;
837 uint32_t reserved0[4];
838 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE : 1;
839 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_MODE : 3;
840 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE : 1;
841 uint32_t CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN : 1;
842 uint32_t CM_CUR0_CURSOR0_COLOR0__CUR0_COLOR0 : 24;
843 uint32_t CM_CUR0_CURSOR0_COLOR1__CUR0_COLOR1 : 24;
844 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_BIAS_G_Y : 16;
845 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_G_Y__CUR0_FP_SCALE_G_Y, : 16;
846 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_BIAS_RB_CRCB : 16;
847 uint32_t CM_CUR0_CURSOR0_FP_SCALE_BIAS_RB_CRCB__CUR0_FP_SCALE_RB_CRCB : 16;
848 uint32_t reserved1[4];
849 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET : 8;
850 uint32_t HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST : 8;
851 uint32_t HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR : 1;
852 uint32_t reserved2[3];
853 };
854
855 /**
856 * struct dmub_cursor_offload_pipe_data_v1 - Per pipe data for cursor offload.
857 */
858 struct dmub_cursor_offload_pipe_data_v1 {
859 union {
860 struct dmub_cursor_offload_pipe_data_dcn30_v1 dcn30; /**< DCN30 cursor data. */
861 struct dmub_cursor_offload_pipe_data_dcn401_v1 dcn401; /**< DCN401 cursor data. */
862 uint8_t payload[96]; /**< Guarantees the cursor pipe data size per-pipe. */
863 };
864 };
865
866 /**
867 * struct dmub_cursor_offload_payload_data_v1 - A payload of stream data.
868 */
869 struct dmub_cursor_offload_payload_data_v1 {
870 uint32_t write_idx_start; /**< Write index, updated before pipe_data is written. */
871 uint32_t write_idx_finish; /**< Write index, updated after pipe_data is written. */
872 uint32_t pipe_mask; /**< Mask of pipes to update. */
873 uint32_t reserved; /**< Reserved for future use. */
874 struct dmub_cursor_offload_pipe_data_v1 pipe_data[6]; /**< Per-pipe cursor data. */
875 };
876
877 /**
878 * struct dmub_cursor_offload_stream_v1 - Per-stream data for cursor offload.
879 */
880 struct dmub_cursor_offload_stream_v1 {
881 struct dmub_cursor_offload_payload_data_v1 payloads[4]; /**< A small buffer of cursor payloads. */
882 uint32_t write_idx; /**< The index of the last written payload. */
883 };
884
885 /**
886 * struct dmub_cursor_offload_v1 - Cursor offload feature state.
887 */
888 struct dmub_cursor_offload_v1 {
889 struct dmub_cursor_offload_stream_v1 offload_streams[6]; /**< Per-stream cursor offload data */
890 };
891
892 //==============================================================================
893 //</DMUB_TYPES>=================================================================
894 //==============================================================================
895 //< DMUB_META>==================================================================
896 //==============================================================================
897 #pragma pack(push, 1)
898
899 /* Magic value for identifying dmub_fw_meta_info */
900 #define DMUB_FW_META_MAGIC 0x444D5542
901
902 /* Offset from the end of the file to the dmub_fw_meta_info */
903 #define DMUB_FW_META_OFFSET 0x24
904
905 /**
906 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization
907 */
908 union dmub_fw_meta_feature_bits {
909 struct {
910 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */
911 uint32_t cursor_offload_v1_support: 1; /**< 1 supports cursor offload */
912 uint32_t reserved : 30;
913 } bits; /**< status bits */
914 uint32_t all; /**< 32-bit access to status bits */
915 };
916
917 /**
918 * struct dmub_fw_meta_info - metadata associated with fw binary
919 *
920 * NOTE: This should be considered a stable API. Fields should
921 * not be repurposed or reordered. New fields should be
922 * added instead to extend the structure.
923 *
924 * @magic_value: magic value identifying DMUB firmware meta info
925 * @fw_region_size: size of the firmware state region
926 * @trace_buffer_size: size of the tracebuffer region
927 * @fw_version: the firmware version information
928 * @dal_fw: 1 if the firmware is DAL
929 * @shared_state_size: size of the shared state region in bytes
930 * @shared_state_features: number of shared state features
931 */
932 struct dmub_fw_meta_info {
933 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
934 uint32_t fw_region_size; /**< size of the firmware state region */
935 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
936 uint32_t fw_version; /**< the firmware version information */
937 uint8_t dal_fw; /**< 1 if the firmware is DAL */
938 uint8_t reserved[3]; /**< padding bits */
939 uint32_t shared_state_size; /**< size of the shared state region in bytes */
940 uint16_t shared_state_features; /**< number of shared state features */
941 uint16_t reserved2; /**< padding bytes */
942 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */
943 };
944
945 /**
946 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
947 */
948 union dmub_fw_meta {
949 struct dmub_fw_meta_info info; /**< metadata info */
950 uint8_t reserved[64]; /**< padding bits */
951 };
952
953 #pragma pack(pop)
954
955 //==============================================================================
956 //< DMUB Trace Buffer>================================================================
957 //==============================================================================
958 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED)
959 /**
960 * dmub_trace_code_t - firmware trace code, 32-bits
961 */
962 typedef uint32_t dmub_trace_code_t;
963
964 /**
965 * struct dmcub_trace_buf_entry - Firmware trace entry
966 */
967 struct dmcub_trace_buf_entry {
968 dmub_trace_code_t trace_code; /**< trace code for the event */
969 uint32_t tick_count; /**< the tick count at time of trace */
970 uint32_t param0; /**< trace defined parameter 0 */
971 uint32_t param1; /**< trace defined parameter 1 */
972 };
973 #endif
974
975 //==============================================================================
976 //< DMUB_STATUS>================================================================
977 //==============================================================================
978
979 /**
980 * DMCUB scratch registers can be used to determine firmware status.
981 * Current scratch register usage is as follows:
982 *
983 * SCRATCH0: FW Boot Status register
984 * SCRATCH5: LVTMA Status Register
985 * SCRATCH15: FW Boot Options register
986 */
987
988 /**
989 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
990 */
991 union dmub_fw_boot_status {
992 struct {
993 uint32_t dal_fw : 1; /**< 1 if DAL FW */
994 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
995 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
996 uint32_t restore_required : 1; /**< 1 if driver should call restore */
997 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
998 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
999 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
1000 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
1001 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */
1002 } bits; /**< status bits */
1003 uint32_t all; /**< 32-bit access to status bits */
1004 };
1005
1006 /**
1007 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
1008 */
1009 enum dmub_fw_boot_status_bit {
1010 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
1011 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
1012 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
1013 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
1014 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
1015 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
1016 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
1017 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
1018 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */
1019 };
1020
1021 /* Register bit definition for SCRATCH5 */
1022 union dmub_lvtma_status {
1023 struct {
1024 uint32_t psp_ok : 1;
1025 uint32_t edp_on : 1;
1026 uint32_t reserved : 30;
1027 } bits;
1028 uint32_t all;
1029 };
1030
1031 enum dmub_lvtma_status_bit {
1032 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
1033 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
1034 };
1035
1036 enum dmub_ips_disable_type {
1037 DMUB_IPS_ENABLE = 0,
1038 DMUB_IPS_DISABLE_ALL = 1,
1039 DMUB_IPS_DISABLE_IPS1 = 2,
1040 DMUB_IPS_DISABLE_IPS2 = 3,
1041 DMUB_IPS_DISABLE_IPS2_Z10 = 4,
1042 DMUB_IPS_DISABLE_DYNAMIC = 5,
1043 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6,
1044 DMUB_IPS_DISABLE_Z8_RETENTION = 7,
1045 };
1046
1047 enum dmub_ips_rcg_disable_type {
1048 DMUB_IPS_RCG_ENABLE = 0,
1049 DMUB_IPS0_RCG_DISABLE = 1,
1050 DMUB_IPS1_RCG_DISABLE = 2,
1051 DMUB_IPS_RCG_DISABLE = 3
1052 };
1053
1054 enum dmub_ips_in_vpb_disable_type {
1055 DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour
1056 DMUB_IPS_VPB_DISABLE_ALL = 1,
1057 DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2,
1058 DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG
1059 };
1060
1061 #define DMUB_IPS1_ALLOW_MASK 0x00000001
1062 #define DMUB_IPS2_ALLOW_MASK 0x00000002
1063 #define DMUB_IPS1_COMMIT_MASK 0x00000004
1064 #define DMUB_IPS2_COMMIT_MASK 0x00000008
1065
1066 enum dmub_ips_comand_type {
1067 /**
1068 * Start/stop IPS residency measurements for a given IPS mode
1069 */
1070 DMUB_CMD__IPS_RESIDENCY_CNTL = 0,
1071 /**
1072 * Query IPS residency information for a given IPS mode
1073 */
1074 DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1,
1075 };
1076
1077 /**
1078 * enum dmub_cursor_offload_comand_type - Cursor offload subcommands.
1079 */
1080 enum dmub_cursor_offload_comand_type {
1081 /**
1082 * Initializes the cursor offload feature.
1083 */
1084 DMUB_CMD__CURSOR_OFFLOAD_INIT = 0,
1085 /**
1086 * Enables cursor offloading for a stream and updates the timing parameters.
1087 */
1088 DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE = 1,
1089 /**
1090 * Disables cursor offloading for a given stream.
1091 */
1092 DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE = 2,
1093 /**
1094 * Programs the latest data for a given stream.
1095 */
1096 DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM = 3,
1097 };
1098
1099 /**
1100 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
1101 */
1102 union dmub_fw_boot_options {
1103 struct {
1104 uint32_t pemu_env : 1; /**< 1 if PEMU */
1105 uint32_t fpga_env : 1; /**< 1 if FPGA */
1106 uint32_t optimized_init : 1; /**< 1 if optimized init */
1107 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
1108 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
1109 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
1110 uint32_t z10_disable: 1; /**< 1 to disable z10 */
1111 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
1112 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
1113 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
1114 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */
1115 /**< 1 if all root clock gating is enabled and low power memory is enabled*/
1116 uint32_t power_optimization: 1;
1117 uint32_t diag_env: 1; /* 1 if diagnostic environment */
1118 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
1119 uint32_t usb4_cm_version: 1; /**< 1 CM support */
1120 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
1121 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/
1122 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/
1123 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */
1124 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/
1125 uint32_t ips_disable: 3; /* options to disable ips support*/
1126 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */
1127 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */
1128 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */
1129 uint32_t override_hbr3_pll_vco: 1; /**< 1 to override the hbr3 pll vco to 0 */
1130 uint32_t disable_dpia_bw_allocation: 1; /**< 1 to disable the USB4 DPIA BW allocation */
1131 uint32_t bootcrc_en_at_preos: 1; /**< 1 to run the boot time crc during warm/cold boot*/
1132 uint32_t bootcrc_en_at_S0i3: 1; /**< 1 to run the boot time crc during S0i3 boot*/
1133 uint32_t bootcrc_boot_mode: 1; /**< 1 for S0i3 resume and 0 for Warm/cold boot*/
1134 uint32_t reserved : 1; /**< reserved */
1135 } bits; /**< boot bits */
1136 uint32_t all; /**< 32-bit access to bits */
1137 };
1138
1139 enum dmub_fw_boot_options_bit {
1140 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
1141 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
1142 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
1143 };
1144
1145 //==============================================================================
1146 //< DMUB_SHARED_STATE>==========================================================
1147 //==============================================================================
1148
1149 /**
1150 * Shared firmware state between driver and firmware for lockless communication
1151 * in situations where the inbox/outbox may be unavailable.
1152 *
1153 * Each structure *must* be at most 256-bytes in size. The layout allocation is
1154 * described below:
1155 *
1156 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]...
1157 */
1158
1159 /**
1160 * enum dmub_shared_state_feature_id - List of shared state features.
1161 */
1162 enum dmub_shared_state_feature_id {
1163 DMUB_SHARED_SHARE_FEATURE__INVALID = 0,
1164 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1,
1165 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2,
1166 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3,
1167 DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1 = 4,
1168 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */
1169 };
1170
1171 /**
1172 * struct dmub_shared_state_ips_fw - Firmware signals for IPS.
1173 */
1174 union dmub_shared_state_ips_fw_signals {
1175 struct {
1176 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */
1177 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */
1178 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */
1179 uint32_t detection_required : 1; /**< 1 if detection is required */
1180 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */
1181 uint32_t reserved_bits : 27; /**< Reversed */
1182 } bits;
1183 uint32_t all;
1184 };
1185
1186 /**
1187 * struct dmub_shared_state_ips_signals - Firmware signals for IPS.
1188 */
1189 union dmub_shared_state_ips_driver_signals {
1190 struct {
1191 uint32_t allow_pg : 1; /**< 1 if PG is allowed */
1192 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */
1193 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */
1194 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */
1195 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */
1196 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */
1197 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */
1198 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */
1199 uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */
1200 uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */
1201 uint32_t reserved_bits : 22; /**< Reversed bits */
1202 } bits;
1203 uint32_t all;
1204 };
1205
1206 /**
1207 * IPS FW Version
1208 */
1209 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1
1210
1211 struct dmub_shared_state_debug_setup {
1212 union {
1213 struct {
1214 uint32_t exclude_points[62];
1215 } profile_mode;
1216 };
1217 };
1218
1219 /**
1220 * struct dmub_shared_state_ips_fw - Firmware state for IPS.
1221 */
1222 struct dmub_shared_state_ips_fw {
1223 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */
1224 uint32_t rcg_entry_count; /**< Entry counter for RCG */
1225 uint32_t rcg_exit_count; /**< Exit counter for RCG */
1226 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */
1227 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */
1228 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */
1229 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */
1230 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */
1231 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */
1232 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */
1233 }; /* 248-bytes, fixed */
1234
1235 /**
1236 * IPS Driver Version
1237 */
1238 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1
1239
1240 /**
1241 * struct dmub_shared_state_ips_driver - Driver state for IPS.
1242 */
1243 struct dmub_shared_state_ips_driver {
1244 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */
1245 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */
1246 }; /* 248-bytes, fixed */
1247
1248 /**
1249 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload.
1250 */
1251 struct dmub_shared_state_cursor_offload_stream_v1 {
1252 uint32_t last_write_idx; /**< Last write index */
1253 uint8_t reserved[28]; /**< Reserved bytes. */
1254 }; /* 32-bytes, fixed */
1255
1256 /**
1257 * struct dmub_shared_state_cursor_offload_v1 - Header metadata for cursor offload.
1258 */
1259 struct dmub_shared_state_cursor_offload_v1 {
1260 struct dmub_shared_state_cursor_offload_stream_v1 offload_streams[6]; /**< stream state, 32-bytes each */
1261 uint8_t reserved[56]; /**< reserved for future use */
1262 }; /* 248-bytes, fixed */
1263
1264 /**
1265 * enum dmub_shared_state_feature_common - Generic payload.
1266 */
1267 struct dmub_shared_state_feature_common {
1268 uint32_t padding[62];
1269 }; /* 248-bytes, fixed */
1270
1271 /**
1272 * enum dmub_shared_state_feature_header - Feature description.
1273 */
1274 struct dmub_shared_state_feature_header {
1275 uint16_t id; /**< Feature ID */
1276 uint16_t version; /**< Feature version */
1277 uint32_t reserved; /**< Reserved bytes. */
1278 }; /* 8 bytes, fixed */
1279
1280 /**
1281 * struct dmub_shared_state_feature_block - Feature block.
1282 */
1283 struct dmub_shared_state_feature_block {
1284 struct dmub_shared_state_feature_header header; /**< Shared state header. */
1285 union dmub_shared_feature_state_union {
1286 struct dmub_shared_state_feature_common common; /**< Generic data */
1287 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */
1288 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */
1289 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */
1290 struct dmub_shared_state_cursor_offload_v1 cursor_offload_v1; /**< Cursor offload */
1291 } data; /**< Shared state data. */
1292 }; /* 256-bytes, fixed */
1293
1294 /**
1295 * Shared state size in bytes.
1296 */
1297 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \
1298 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block))
1299
1300 //==============================================================================
1301 //</DMUB_STATUS>================================================================
1302 //==============================================================================
1303 //< DMUB_VBIOS>=================================================================
1304 //==============================================================================
1305
1306 /*
1307 * enum dmub_cmd_vbios_type - VBIOS commands.
1308 *
1309 * Command IDs should be treated as stable ABI.
1310 * Do not reuse or modify IDs.
1311 */
1312 enum dmub_cmd_vbios_type {
1313 /**
1314 * Configures the DIG encoder.
1315 */
1316 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
1317 /**
1318 * Controls the PHY.
1319 */
1320 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
1321 /**
1322 * Sets the pixel clock/symbol clock.
1323 */
1324 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
1325 /**
1326 * Enables or disables power gating.
1327 */
1328 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
1329 /**
1330 * Controls embedded panels.
1331 */
1332 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
1333 /**
1334 * Query DP alt status on a transmitter.
1335 */
1336 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26,
1337 /**
1338 * Control PHY FSM
1339 */
1340 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29,
1341 /**
1342 * Controls domain power gating
1343 */
1344 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,
1345 };
1346
1347 //==============================================================================
1348 //</DMUB_VBIOS>=================================================================
1349 //==============================================================================
1350 //< DMUB_GPINT>=================================================================
1351 //==============================================================================
1352
1353 /**
1354 * The shifts and masks below may alternatively be used to format and read
1355 * the command register bits.
1356 */
1357
1358 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
1359 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
1360
1361 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
1362 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
1363
1364 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
1365 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
1366
1367 /**
1368 * Command responses.
1369 */
1370
1371 /**
1372 * Return response for DMUB_GPINT__STOP_FW command.
1373 */
1374 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
1375
1376 /**
1377 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
1378 */
1379 union dmub_gpint_data_register {
1380 struct {
1381 uint32_t param : 16; /**< 16-bit parameter */
1382 uint32_t command_code : 12; /**< GPINT command */
1383 uint32_t status : 4; /**< Command status bit */
1384 } bits; /**< GPINT bit access */
1385 uint32_t all; /**< GPINT 32-bit access */
1386 };
1387
1388 /*
1389 * enum dmub_gpint_command - GPINT command to DMCUB FW
1390 *
1391 * Command IDs should be treated as stable ABI.
1392 * Do not reuse or modify IDs.
1393 */
1394 enum dmub_gpint_command {
1395 /**
1396 * Invalid command, ignored.
1397 */
1398 DMUB_GPINT__INVALID_COMMAND = 0,
1399 /**
1400 * DESC: Queries the firmware version.
1401 * RETURN: Firmware version.
1402 */
1403 DMUB_GPINT__GET_FW_VERSION = 1,
1404 /**
1405 * DESC: Halts the firmware.
1406 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
1407 */
1408 DMUB_GPINT__STOP_FW = 2,
1409 /**
1410 * DESC: Get PSR state from FW.
1411 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
1412 */
1413 DMUB_GPINT__GET_PSR_STATE = 7,
1414 /**
1415 * DESC: Notifies DMCUB of the currently active streams.
1416 * ARGS: Stream mask, 1 bit per active stream index.
1417 */
1418 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
1419 /**
1420 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
1421 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
1422 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
1423 * RETURN: PSR residency in milli-percent.
1424 */
1425 DMUB_GPINT__PSR_RESIDENCY = 9,
1426
1427 /**
1428 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
1429 */
1430 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
1431
1432 /**
1433 * DESC: Get REPLAY state from FW.
1434 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
1435 */
1436 DMUB_GPINT__GET_REPLAY_STATE = 13,
1437
1438 /**
1439 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value.
1440 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
1441 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
1442 * RETURN: REPLAY residency in milli-percent.
1443 */
1444 DMUB_GPINT__REPLAY_RESIDENCY = 14,
1445
1446 /**
1447 * DESC: Copy bounding box to the host.
1448 * ARGS: Version of bounding box to copy
1449 * RETURN: Result of copying bounding box
1450 */
1451 DMUB_GPINT__BB_COPY = 96,
1452
1453 /**
1454 * DESC: Updates the host addresses bit48~bit63 for bounding box.
1455 * ARGS: The word3 for the 64 bit address
1456 */
1457 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97,
1458
1459 /**
1460 * DESC: Updates the host addresses bit32~bit47 for bounding box.
1461 * ARGS: The word2 for the 64 bit address
1462 */
1463 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98,
1464
1465 /**
1466 * DESC: Updates the host addresses bit16~bit31 for bounding box.
1467 * ARGS: The word1 for the 64 bit address
1468 */
1469 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99,
1470
1471 /**
1472 * DESC: Updates the host addresses bit0~bit15 for bounding box.
1473 * ARGS: The word0 for the 64 bit address
1474 */
1475 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100,
1476
1477 /**
1478 * DESC: Updates the trace buffer lower 32-bit mask.
1479 * ARGS: The new mask
1480 * RETURN: Lower 32-bit mask.
1481 */
1482 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,
1483
1484 /**
1485 * DESC: Updates the trace buffer mask bit0~bit15.
1486 * ARGS: The new mask
1487 * RETURN: Lower 32-bit mask.
1488 */
1489 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,
1490
1491 /**
1492 * DESC: Updates the trace buffer mask bit16~bit31.
1493 * ARGS: The new mask
1494 * RETURN: Lower 32-bit mask.
1495 */
1496 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,
1497
1498 /**
1499 * DESC: Updates the trace buffer mask bit32~bit47.
1500 * ARGS: The new mask
1501 * RETURN: Lower 32-bit mask.
1502 */
1503 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114,
1504
1505 /**
1506 * DESC: Updates the trace buffer mask bit48~bit63.
1507 * ARGS: The new mask
1508 * RETURN: Lower 32-bit mask.
1509 */
1510 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115,
1511
1512 /**
1513 * DESC: Read the trace buffer mask bi0~bit15.
1514 */
1515 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116,
1516
1517 /**
1518 * DESC: Read the trace buffer mask bit16~bit31.
1519 */
1520 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117,
1521
1522 /**
1523 * DESC: Read the trace buffer mask bi32~bit47.
1524 */
1525 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118,
1526
1527 /**
1528 * DESC: Updates the trace buffer mask bit32~bit63.
1529 */
1530 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119,
1531
1532 /**
1533 * DESC: Set IPS residency measurement
1534 * ARGS: 0 - Disable ips measurement
1535 * 1 - Enable ips measurement
1536 */
1537 DMUB_GPINT__IPS_RESIDENCY = 121,
1538
1539 /**
1540 * DESC: Enable measurements for various task duration
1541 * ARGS: 0 - Disable measurement
1542 * 1 - Enable measurement
1543 */
1544 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123,
1545
1546 /**
1547 * DESC: Gets IPS residency in microseconds
1548 * ARGS: 0 - Return IPS1 residency
1549 * 1 - Return IPS2 residency
1550 * 2 - Return IPS1_RCG residency
1551 * 3 - Return IPS1_ONO2_ON residency
1552 * RETURN: Total residency in microseconds - lower 32 bits
1553 */
1554 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124,
1555
1556 /**
1557 * DESC: Gets IPS1 histogram counts
1558 * ARGS: Bucket index
1559 * RETURN: Total count for the bucket
1560 */
1561 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125,
1562
1563 /**
1564 * DESC: Gets IPS2 histogram counts
1565 * ARGS: Bucket index
1566 * RETURN: Total count for the bucket
1567 */
1568 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126,
1569
1570 /**
1571 * DESC: Gets IPS residency
1572 * ARGS: 0 - Return IPS1 residency
1573 * 1 - Return IPS2 residency
1574 * 2 - Return IPS1_RCG residency
1575 * 3 - Return IPS1_ONO2_ON residency
1576 * RETURN: Total residency in milli-percent.
1577 */
1578 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127,
1579
1580 /**
1581 * DESC: Gets IPS1_RCG histogram counts
1582 * ARGS: Bucket index
1583 * RETURN: Total count for the bucket
1584 */
1585 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128,
1586
1587 /**
1588 * DESC: Gets IPS1_ONO2_ON histogram counts
1589 * ARGS: Bucket index
1590 * RETURN: Total count for the bucket
1591 */
1592 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129,
1593
1594 /**
1595 * DESC: Gets IPS entry counter during residency measurement
1596 * ARGS: 0 - Return IPS1 entry counts
1597 * 1 - Return IPS2 entry counts
1598 * 2 - Return IPS1_RCG entry counts
1599 * 3 - Return IPS2_ONO2_ON entry counts
1600 * RETURN: Entry counter for selected IPS mode
1601 */
1602 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130,
1603
1604 /**
1605 * DESC: Gets IPS inactive residency in microseconds
1606 * ARGS: 0 - Return IPS1_MAX residency
1607 * 1 - Return IPS2 residency
1608 * 2 - Return IPS1_RCG residency
1609 * 3 - Return IPS1_ONO2_ON residency
1610 * RETURN: Total inactive residency in microseconds - lower 32 bits
1611 */
1612 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131,
1613
1614 /**
1615 * DESC: Gets IPS inactive residency in microseconds
1616 * ARGS: 0 - Return IPS1_MAX residency
1617 * 1 - Return IPS2 residency
1618 * 2 - Return IPS1_RCG residency
1619 * 3 - Return IPS1_ONO2_ON residency
1620 * RETURN: Total inactive residency in microseconds - upper 32 bits
1621 */
1622 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132,
1623
1624 /**
1625 * DESC: Gets IPS residency in microseconds
1626 * ARGS: 0 - Return IPS1 residency
1627 * 1 - Return IPS2 residency
1628 * 2 - Return IPS1_RCG residency
1629 * 3 - Return IPS1_ONO2_ON residency
1630 * RETURN: Total residency in microseconds - upper 32 bits
1631 */
1632 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133,
1633 /**
1634 * DESC: Setup debug configs.
1635 */
1636 DMUB_GPINT__SETUP_DEBUG_MODE = 136,
1637 /**
1638 * DESC: Initiates IPS wake sequence.
1639 */
1640 DMUB_GPINT__IPS_DEBUG_WAKE = 137,
1641 /**
1642 * DESC: Do panel power off sequence
1643 * ARGS: 1 - Power off
1644 */
1645 DMUB_GPINT__PANEL_POWER_OFF_SEQ = 138,
1646 };
1647
1648 /**
1649 * INBOX0 generic command definition
1650 */
1651 union dmub_inbox0_cmd_common {
1652 struct {
1653 uint32_t command_code: 8; /**< INBOX0 command code */
1654 uint32_t param: 24; /**< 24-bit parameter */
1655 } bits;
1656 uint32_t all;
1657 };
1658
1659 /**
1660 * INBOX0 hw_lock command definition
1661 */
1662 union dmub_inbox0_cmd_lock_hw {
1663 struct {
1664 uint32_t command_code: 8;
1665
1666 /* NOTE: Must be have enough bits to match: enum hw_lock_client */
1667 uint32_t hw_lock_client: 2;
1668
1669 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
1670 uint32_t otg_inst: 3;
1671 uint32_t opp_inst: 3;
1672 uint32_t dig_inst: 3;
1673
1674 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
1675 uint32_t lock_pipe: 1;
1676 uint32_t lock_cursor: 1;
1677 uint32_t lock_dig: 1;
1678 uint32_t triple_buffer_lock: 1;
1679
1680 uint32_t lock: 1; /**< Lock */
1681 uint32_t should_release: 1; /**< Release */
1682 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */
1683 } bits;
1684 uint32_t all;
1685 };
1686
1687 union dmub_inbox0_data_register {
1688 union dmub_inbox0_cmd_common inbox0_cmd_common;
1689 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
1690 };
1691
1692 enum dmub_inbox0_command {
1693 /**
1694 * DESC: Invalid command, ignored.
1695 */
1696 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
1697 /**
1698 * DESC: Notification to acquire/release HW lock
1699 * ARGS:
1700 */
1701 DMUB_INBOX0_CMD__HW_LOCK = 1,
1702 };
1703 //==============================================================================
1704 //</DMUB_GPINT>=================================================================
1705 //==============================================================================
1706 //< DMUB_CMD>===================================================================
1707 //==============================================================================
1708
1709 /**
1710 * Size in bytes of each DMUB command.
1711 */
1712 #define DMUB_RB_CMD_SIZE 64
1713
1714 /**
1715 * Maximum number of items in the DMUB ringbuffer.
1716 */
1717 #define DMUB_RB_MAX_ENTRY 128
1718
1719 /**
1720 * Ringbuffer size in bytes.
1721 */
1722 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
1723
1724 /**
1725 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer.
1726 */
1727 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16
1728
1729 /**
1730 * Ringbuffer size in bytes.
1731 */
1732 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY)
1733
1734 /**
1735 * REG_SET mask for reg offload.
1736 */
1737 #define REG_SET_MASK 0xFFFF
1738
1739 /*
1740 * enum dmub_cmd_type - DMUB inbox command.
1741 *
1742 * Command IDs should be treated as stable ABI.
1743 * Do not reuse or modify IDs.
1744 */
1745 enum dmub_cmd_type {
1746 /**
1747 * Invalid command.
1748 */
1749 DMUB_CMD__NULL = 0,
1750 /**
1751 * Read modify write register sequence offload.
1752 */
1753 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
1754 /**
1755 * Field update register sequence offload.
1756 */
1757 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
1758 /**
1759 * Burst write sequence offload.
1760 */
1761 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
1762 /**
1763 * Reg wait sequence offload.
1764 */
1765 DMUB_CMD__REG_REG_WAIT = 4,
1766 /**
1767 * Workaround to avoid HUBP underflow during NV12 playback.
1768 */
1769 DMUB_CMD__PLAT_54186_WA = 5,
1770 /**
1771 * Command type used to query FW feature caps.
1772 */
1773 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
1774 /**
1775 * Command type used to get visual confirm color.
1776 */
1777 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
1778 /**
1779 * Command type used for all PSR commands.
1780 */
1781 DMUB_CMD__PSR = 64,
1782 /**
1783 * Command type used for all MALL commands.
1784 */
1785 DMUB_CMD__MALL = 65,
1786 /**
1787 * Command type used for all ABM commands.
1788 */
1789 DMUB_CMD__ABM = 66,
1790 /**
1791 * Command type used to update dirty rects in FW.
1792 */
1793 DMUB_CMD__UPDATE_DIRTY_RECT = 67,
1794 /**
1795 * Command type used to update cursor info in FW.
1796 */
1797 DMUB_CMD__UPDATE_CURSOR_INFO = 68,
1798 /**
1799 * Command type used for HW locking in FW.
1800 */
1801 DMUB_CMD__HW_LOCK = 69,
1802 /**
1803 * Command type used to access DP AUX.
1804 */
1805 DMUB_CMD__DP_AUX_ACCESS = 70,
1806 /**
1807 * Command type used for OUTBOX1 notification enable
1808 */
1809 DMUB_CMD__OUTBOX1_ENABLE = 71,
1810
1811 /**
1812 * Command type used for all idle optimization commands.
1813 */
1814 DMUB_CMD__IDLE_OPT = 72,
1815 /**
1816 * Command type used for all clock manager commands.
1817 */
1818 DMUB_CMD__CLK_MGR = 73,
1819 /**
1820 * Command type used for all panel control commands.
1821 */
1822 DMUB_CMD__PANEL_CNTL = 74,
1823
1824 /**
1825 * Command type used for all CAB commands.
1826 */
1827 DMUB_CMD__CAB_FOR_SS = 75,
1828
1829 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
1830
1831 /**
1832 * Command type used for interfacing with DPIA.
1833 */
1834 DMUB_CMD__DPIA = 77,
1835 /**
1836 * Command type used for EDID CEA parsing
1837 */
1838 DMUB_CMD__EDID_CEA = 79,
1839 /**
1840 * Command type used for getting usbc cable ID
1841 */
1842 DMUB_CMD_GET_USBC_CABLE_ID = 81,
1843 /**
1844 * Command type used to query HPD state.
1845 */
1846 DMUB_CMD__QUERY_HPD_STATE = 82,
1847 /**
1848 * Command type used for all VBIOS interface commands.
1849 */
1850 /**
1851 * Command type used for all REPLAY commands.
1852 */
1853 DMUB_CMD__REPLAY = 83,
1854
1855 /**
1856 * Command type used for all SECURE_DISPLAY commands.
1857 */
1858 DMUB_CMD__SECURE_DISPLAY = 85,
1859
1860 /**
1861 * Command type used to set DPIA HPD interrupt state
1862 */
1863 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
1864
1865 /**
1866 * Command type used for all PSP commands.
1867 */
1868 DMUB_CMD__PSP = 88,
1869
1870 /**
1871 * Command type used for all Fused IO commands.
1872 */
1873 DMUB_CMD__FUSED_IO = 89,
1874
1875 /**
1876 * Command type used for all LSDMA commands.
1877 */
1878 DMUB_CMD__LSDMA = 90,
1879
1880 /**
1881 * Command type use for all IPS commands.
1882 */
1883 DMUB_CMD__IPS = 91,
1884
1885 /**
1886 * Command type use for Cursor offload.
1887 */
1888 DMUB_CMD__CURSOR_OFFLOAD = 92,
1889
1890 /**
1891 * Command type used for all SMART_POWER_OLED commands.
1892 */
1893 DMUB_CMD__SMART_POWER_OLED = 93,
1894
1895 /**
1896 * Command type use for all Panel Replay commands.
1897 */
1898 DMUB_CMD__PR = 94,
1899
1900
1901 /**
1902 * Command type use for VBIOS shared commands.
1903 */
1904 DMUB_CMD__VBIOS = 128,
1905 };
1906
1907 /**
1908 * enum dmub_out_cmd_type - DMUB outbox commands.
1909 */
1910 enum dmub_out_cmd_type {
1911 /**
1912 * Invalid outbox command, ignored.
1913 */
1914 DMUB_OUT_CMD__NULL = 0,
1915 /**
1916 * Command type used for DP AUX Reply data notification
1917 */
1918 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
1919 /**
1920 * Command type used for DP HPD event notification
1921 */
1922 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
1923 /**
1924 * Command type used for SET_CONFIG Reply notification
1925 */
1926 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
1927 /**
1928 * Command type used for USB4 DPIA notification
1929 */
1930 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5,
1931 /**
1932 * Command type used for HPD redetect notification
1933 */
1934 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6,
1935 /**
1936 * Command type used for Fused IO notification
1937 */
1938 DMUB_OUT_CMD__FUSED_IO = 7,
1939 };
1940
1941 /* DMUB_CMD__DPIA command sub-types. */
1942 enum dmub_cmd_dpia_type {
1943 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
1944 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST
1945 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
1946 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3,
1947 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4,
1948 };
1949
1950 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */
1951 enum dmub_cmd_dpia_notification_type {
1952 DPIA_NOTIFY__BW_ALLOCATION = 0,
1953 };
1954
1955 #pragma pack(push, 1)
1956
1957 /**
1958 * struct dmub_cmd_header - Common command header fields.
1959 */
1960 struct dmub_cmd_header {
1961 unsigned int type : 8; /**< command type */
1962 unsigned int sub_type : 8; /**< command sub type */
1963 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
1964 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
1965 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */
1966 unsigned int reserved0 : 5; /**< reserved bits */
1967 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
1968 unsigned int reserved1 : 2; /**< reserved bits */
1969 };
1970
1971 /*
1972 * struct dmub_cmd_read_modify_write_sequence - Read modify write
1973 *
1974 * 60 payload bytes can hold up to 5 sets of read modify writes,
1975 * each take 3 dwords.
1976 *
1977 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
1978 *
1979 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
1980 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
1981 */
1982 struct dmub_cmd_read_modify_write_sequence {
1983 uint32_t addr; /**< register address */
1984 uint32_t modify_mask; /**< modify mask */
1985 uint32_t modify_value; /**< modify value */
1986 };
1987
1988 /**
1989 * Maximum number of ops in read modify write sequence.
1990 */
1991 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
1992
1993 /**
1994 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
1995 */
1996 struct dmub_rb_cmd_read_modify_write {
1997 struct dmub_cmd_header header; /**< command header */
1998 /**
1999 * Read modify write sequence.
2000 */
2001 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
2002 };
2003
2004 /*
2005 * Update a register with specified masks and values sequeunce
2006 *
2007 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
2008 *
2009 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
2010 *
2011 *
2012 * USE CASE:
2013 * 1. auto-increment register where additional read would update pointer and produce wrong result
2014 * 2. toggle a bit without read in the middle
2015 */
2016
2017 struct dmub_cmd_reg_field_update_sequence {
2018 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
2019 uint32_t modify_value; /**< value to update with */
2020 };
2021
2022 /**
2023 * Maximum number of ops in field update sequence.
2024 */
2025 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
2026
2027 /**
2028 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
2029 */
2030 struct dmub_rb_cmd_reg_field_update_sequence {
2031 struct dmub_cmd_header header; /**< command header */
2032 uint32_t addr; /**< register address */
2033 /**
2034 * Field update sequence.
2035 */
2036 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
2037 };
2038
2039
2040 /**
2041 * Maximum number of burst write values.
2042 */
2043 #define DMUB_BURST_WRITE_VALUES__MAX 14
2044
2045 /*
2046 * struct dmub_rb_cmd_burst_write - Burst write
2047 *
2048 * support use case such as writing out LUTs.
2049 *
2050 * 60 payload bytes can hold up to 14 values to write to given address
2051 *
2052 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
2053 */
2054 struct dmub_rb_cmd_burst_write {
2055 struct dmub_cmd_header header; /**< command header */
2056 uint32_t addr; /**< register start address */
2057 /**
2058 * Burst write register values.
2059 */
2060 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
2061 };
2062
2063 /**
2064 * struct dmub_rb_cmd_common - Common command header
2065 */
2066 struct dmub_rb_cmd_common {
2067 struct dmub_cmd_header header; /**< command header */
2068 /**
2069 * Padding to RB_CMD_SIZE
2070 */
2071 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
2072 };
2073
2074 /**
2075 * struct dmub_cmd_reg_wait_data - Register wait data
2076 */
2077 struct dmub_cmd_reg_wait_data {
2078 uint32_t addr; /**< Register address */
2079 uint32_t mask; /**< Mask for register bits */
2080 uint32_t condition_field_value; /**< Value to wait for */
2081 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
2082 };
2083
2084 /**
2085 * struct dmub_rb_cmd_reg_wait - Register wait command
2086 */
2087 struct dmub_rb_cmd_reg_wait {
2088 struct dmub_cmd_header header; /**< Command header */
2089 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
2090 };
2091
2092 /**
2093 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
2094 *
2095 * Reprograms surface parameters to avoid underflow.
2096 */
2097 struct dmub_cmd_PLAT_54186_wa {
2098 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
2099 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
2100 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
2101 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
2102 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
2103 struct {
2104 uint32_t hubp_inst : 4; /**< HUBP instance */
2105 uint32_t tmz_surface : 1; /**< TMZ enable or disable */
2106 uint32_t immediate :1; /**< Immediate flip */
2107 uint32_t vmid : 4; /**< VMID */
2108 uint32_t grph_stereo : 1; /**< 1 if stereo */
2109 uint32_t reserved : 21; /**< Reserved */
2110 } flip_params; /**< Pageflip parameters */
2111 uint32_t reserved[9]; /**< Reserved bits */
2112 };
2113
2114 /**
2115 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
2116 */
2117 struct dmub_rb_cmd_PLAT_54186_wa {
2118 struct dmub_cmd_header header; /**< Command header */
2119 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
2120 };
2121
2122 /**
2123 * enum dmub_cmd_mall_type - MALL commands
2124 */
2125 enum dmub_cmd_mall_type {
2126 /**
2127 * Allows display refresh from MALL.
2128 */
2129 DMUB_CMD__MALL_ACTION_ALLOW = 0,
2130 /**
2131 * Disallows display refresh from MALL.
2132 */
2133 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
2134 /**
2135 * Cursor copy for MALL.
2136 */
2137 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
2138 /**
2139 * Controls DF requests.
2140 */
2141 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
2142 };
2143
2144 /**
2145 * struct dmub_rb_cmd_mall - MALL command data.
2146 */
2147 struct dmub_rb_cmd_mall {
2148 struct dmub_cmd_header header; /**< Common command header */
2149 union dmub_addr cursor_copy_src; /**< Cursor copy address */
2150 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
2151 uint32_t tmr_delay; /**< Timer delay */
2152 uint32_t tmr_scale; /**< Timer scale */
2153 uint16_t cursor_width; /**< Cursor width in pixels */
2154 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
2155 uint16_t cursor_height; /**< Cursor height in pixels */
2156 uint8_t cursor_bpp; /**< Cursor bits per pixel */
2157 uint8_t debug_bits; /**< Debug bits */
2158
2159 uint8_t reserved1; /**< Reserved bits */
2160 uint8_t reserved2; /**< Reserved bits */
2161 };
2162
2163 /**
2164 * enum dmub_cmd_cab_type - CAB command data.
2165 */
2166 enum dmub_cmd_cab_type {
2167 /**
2168 * No idle optimizations (i.e. no CAB)
2169 */
2170 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
2171 /**
2172 * No DCN requests for memory
2173 */
2174 DMUB_CMD__CAB_NO_DCN_REQ = 1,
2175 /**
2176 * Fit surfaces in CAB (i.e. CAB enable)
2177 */
2178 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
2179 /**
2180 * Do not fit surfaces in CAB (i.e. no CAB)
2181 */
2182 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3,
2183 };
2184
2185 /**
2186 * struct dmub_rb_cmd_cab - CAB command data.
2187 */
2188 struct dmub_rb_cmd_cab_for_ss {
2189 struct dmub_cmd_header header;
2190 uint8_t cab_alloc_ways; /* total number of ways */
2191 uint8_t debug_bits; /* debug bits */
2192 };
2193
2194 /**
2195 * Enum for indicating which MCLK switch mode per pipe
2196 */
2197 enum mclk_switch_mode {
2198 NONE = 0,
2199 FPO = 1,
2200 SUBVP = 2,
2201 VBLANK = 3,
2202 };
2203
2204 /* Per pipe struct which stores the MCLK switch mode
2205 * data to be sent to DMUB.
2206 * Named "v2" for now -- once FPO and SUBVP are fully merged
2207 * the type name can be updated
2208 */
2209 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
2210 union {
2211 struct {
2212 uint32_t pix_clk_100hz;
2213 uint16_t main_vblank_start;
2214 uint16_t main_vblank_end;
2215 uint16_t mall_region_lines;
2216 uint16_t prefetch_lines;
2217 uint16_t prefetch_to_mall_start_lines;
2218 uint16_t processing_delay_lines;
2219 uint16_t htotal; // required to calculate line time for multi-display cases
2220 uint16_t vtotal;
2221 uint8_t main_pipe_index;
2222 uint8_t phantom_pipe_index;
2223 /* Since the microschedule is calculated in terms of OTG lines,
2224 * include any scaling factors to make sure when we get accurate
2225 * conversion when programming MALL_START_LINE (which is in terms
2226 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor
2227 * is 1/2 (numerator = 1, denominator = 2).
2228 */
2229 uint8_t scale_factor_numerator;
2230 uint8_t scale_factor_denominator;
2231 uint8_t is_drr;
2232 uint8_t main_split_pipe_index;
2233 uint8_t phantom_split_pipe_index;
2234 } subvp_data;
2235
2236 struct {
2237 uint32_t pix_clk_100hz;
2238 uint16_t vblank_start;
2239 uint16_t vblank_end;
2240 uint16_t vstartup_start;
2241 uint16_t vtotal;
2242 uint16_t htotal;
2243 uint8_t vblank_pipe_index;
2244 uint8_t padding[1];
2245 struct {
2246 uint8_t drr_in_use;
2247 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame
2248 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK
2249 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling
2250 uint8_t use_ramping; // Use ramping or not
2251 uint8_t drr_vblank_start_margin;
2252 } drr_info; // DRR considered as part of SubVP + VBLANK case
2253 } vblank_data;
2254 } pipe_config;
2255
2256 /* - subvp_data in the union (pipe_config) takes up 27 bytes.
2257 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only
2258 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
2259 */
2260 uint8_t mode; // enum mclk_switch_mode
2261 };
2262
2263 /**
2264 * Config data for Sub-VP and FPO
2265 * Named "v2" for now -- once FPO and SUBVP are fully merged
2266 * the type name can be updated
2267 */
2268 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
2269 uint16_t watermark_a_cache;
2270 uint8_t vertical_int_margin_us;
2271 uint8_t pstate_allow_width_us;
2272 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
2273 };
2274
2275 /**
2276 * DMUB rb command definition for Sub-VP and FPO
2277 * Named "v2" for now -- once FPO and SUBVP are fully merged
2278 * the type name can be updated
2279 */
2280 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {
2281 struct dmub_cmd_header header;
2282 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
2283 };
2284
2285 struct dmub_flip_addr_info {
2286 uint32_t surf_addr_lo;
2287 uint32_t surf_addr_c_lo;
2288 uint32_t meta_addr_lo;
2289 uint32_t meta_addr_c_lo;
2290 uint16_t surf_addr_hi;
2291 uint16_t surf_addr_c_hi;
2292 uint16_t meta_addr_hi;
2293 uint16_t meta_addr_c_hi;
2294 };
2295
2296 struct dmub_fams2_flip_info {
2297 union {
2298 struct {
2299 uint8_t is_immediate: 1;
2300 } bits;
2301 uint8_t all;
2302 } config;
2303 uint8_t otg_inst;
2304 uint8_t pipe_mask;
2305 uint8_t pad;
2306 struct dmub_flip_addr_info addr_info;
2307 };
2308
2309 struct dmub_rb_cmd_fams2_flip {
2310 struct dmub_cmd_header header;
2311 struct dmub_fams2_flip_info flip_info;
2312 };
2313
2314 struct dmub_cmd_lsdma_data {
2315 union {
2316 struct lsdma_init_data {
2317 union dmub_addr gpu_addr_base;
2318 uint32_t ring_size;
2319 } init_data;
2320 struct lsdma_tiled_copy_data {
2321 uint32_t src_addr_lo;
2322 uint32_t src_addr_hi;
2323
2324 uint32_t dst_addr_lo;
2325 uint32_t dst_addr_hi;
2326
2327 uint32_t src_x : 16;
2328 uint32_t src_y : 16;
2329
2330 uint32_t dst_x : 16;
2331 uint32_t dst_y : 16;
2332
2333 uint32_t src_width : 16;
2334 uint32_t src_height : 16;
2335
2336 uint32_t dst_width : 16;
2337 uint32_t dst_height : 16;
2338
2339 uint32_t rect_x : 16;
2340 uint32_t rect_y : 16;
2341
2342 uint32_t src_swizzle_mode : 5;
2343 uint32_t src_mip_max : 5;
2344 uint32_t src_mip_id : 5;
2345 uint32_t dst_mip_max : 5;
2346 uint32_t dst_swizzle_mode : 5;
2347 uint32_t dst_mip_id : 5;
2348 uint32_t tmz : 1;
2349 uint32_t dcc : 1;
2350
2351 uint32_t data_format : 6;
2352 uint32_t padding1 : 4;
2353 uint32_t dst_element_size : 3;
2354 uint32_t num_type : 3;
2355 uint32_t src_element_size : 3;
2356 uint32_t write_compress : 2;
2357 uint32_t cache_policy_dst : 2;
2358 uint32_t cache_policy_src : 2;
2359 uint32_t read_compress : 2;
2360 uint32_t src_dim : 2;
2361 uint32_t dst_dim : 2;
2362 uint32_t max_uncom : 1;
2363
2364 uint32_t max_com : 2;
2365 uint32_t padding : 30;
2366 } tiled_copy_data;
2367 struct lsdma_linear_copy_data {
2368 uint32_t src_lo;
2369 uint32_t src_hi;
2370
2371 uint32_t dst_lo;
2372 uint32_t dst_hi;
2373
2374 uint32_t count : 30;
2375 uint32_t cache_policy_dst : 2;
2376
2377 uint32_t tmz : 1;
2378 uint32_t cache_policy_src : 2;
2379 uint32_t padding : 29;
2380 } linear_copy_data;
2381 struct lsdma_linear_sub_window_copy_data {
2382 uint32_t src_lo;
2383 uint32_t src_hi;
2384
2385 uint32_t dst_lo;
2386 uint32_t dst_hi;
2387
2388 uint32_t src_x : 16;
2389 uint32_t src_y : 16;
2390
2391 uint32_t dst_x : 16;
2392 uint32_t dst_y : 16;
2393
2394 uint32_t rect_x : 16;
2395 uint32_t rect_y : 16;
2396
2397 uint32_t src_pitch : 16;
2398 uint32_t dst_pitch : 16;
2399
2400 uint32_t src_slice_pitch;
2401 uint32_t dst_slice_pitch;
2402
2403 uint32_t tmz : 1;
2404 uint32_t element_size : 3;
2405 uint32_t src_cache_policy : 3;
2406 uint32_t dst_cache_policy : 3;
2407 uint32_t reserved0 : 22;
2408 } linear_sub_window_copy_data;
2409 struct lsdma_reg_write_data {
2410 uint32_t reg_addr;
2411 uint32_t reg_data;
2412 } reg_write_data;
2413 struct lsdma_pio_copy_data {
2414 uint32_t src_lo;
2415 uint32_t src_hi;
2416
2417 uint32_t dst_lo;
2418 uint32_t dst_hi;
2419
2420 union {
2421 struct {
2422 uint32_t byte_count : 26;
2423 uint32_t src_loc : 1;
2424 uint32_t dst_loc : 1;
2425 uint32_t src_addr_inc : 1;
2426 uint32_t dst_addr_inc : 1;
2427 uint32_t overlap_disable : 1;
2428 uint32_t constant_fill : 1;
2429 } fields;
2430 uint32_t raw;
2431 } packet;
2432 } pio_copy_data;
2433 struct lsdma_pio_constfill_data {
2434 uint32_t dst_lo;
2435 uint32_t dst_hi;
2436
2437 union {
2438 struct {
2439 uint32_t byte_count : 26;
2440 uint32_t src_loc : 1;
2441 uint32_t dst_loc : 1;
2442 uint32_t src_addr_inc : 1;
2443 uint32_t dst_addr_inc : 1;
2444 uint32_t overlap_disable : 1;
2445 uint32_t constant_fill : 1;
2446 } fields;
2447 uint32_t raw;
2448 } packet;
2449
2450 uint32_t data;
2451 } pio_constfill_data;
2452
2453 uint32_t all[14];
2454 } u;
2455 };
2456
2457 struct dmub_rb_cmd_lsdma {
2458 struct dmub_cmd_header header;
2459 struct dmub_cmd_lsdma_data lsdma_data;
2460 };
2461
2462 struct dmub_optc_state_v2 {
2463 uint32_t v_total_min;
2464 uint32_t v_total_max;
2465 uint32_t v_total_mid;
2466 uint32_t v_total_mid_frame_num;
2467 uint8_t program_manual_trigger;
2468 uint8_t tg_inst;
2469 uint8_t pad[2];
2470 };
2471
2472 struct dmub_optc_position {
2473 uint32_t vpos;
2474 uint32_t hpos;
2475 uint32_t frame;
2476 };
2477
2478 struct dmub_rb_cmd_fams2_drr_update {
2479 struct dmub_cmd_header header;
2480 struct dmub_optc_state_v2 dmub_optc_state_req;
2481 };
2482
2483 /* HW and FW global configuration data for FAMS2 */
2484 /* FAMS2 types and structs */
2485 enum fams2_stream_type {
2486 FAMS2_STREAM_TYPE_NONE = 0,
2487 FAMS2_STREAM_TYPE_VBLANK = 1,
2488 FAMS2_STREAM_TYPE_VACTIVE = 2,
2489 FAMS2_STREAM_TYPE_DRR = 3,
2490 FAMS2_STREAM_TYPE_SUBVP = 4,
2491 };
2492
2493 struct dmub_rect16 {
2494 /**
2495 * Dirty rect x offset.
2496 */
2497 uint16_t x;
2498
2499 /**
2500 * Dirty rect y offset.
2501 */
2502 uint16_t y;
2503
2504 /**
2505 * Dirty rect width.
2506 */
2507 uint16_t width;
2508
2509 /**
2510 * Dirty rect height.
2511 */
2512 uint16_t height;
2513 };
2514
2515 /* static stream state */
2516 struct dmub_fams2_legacy_stream_static_state {
2517 uint8_t vactive_det_fill_delay_otg_vlines;
2518 uint8_t programming_delay_otg_vlines;
2519 }; //v0
2520
2521 struct dmub_fams2_subvp_stream_static_state {
2522 uint16_t vratio_numerator;
2523 uint16_t vratio_denominator;
2524 uint16_t phantom_vtotal;
2525 uint16_t phantom_vactive;
2526 union {
2527 struct {
2528 uint8_t is_multi_planar : 1;
2529 uint8_t is_yuv420 : 1;
2530 } bits;
2531 uint8_t all;
2532 } config;
2533 uint8_t programming_delay_otg_vlines;
2534 uint8_t prefetch_to_mall_otg_vlines;
2535 uint8_t phantom_otg_inst;
2536 uint8_t phantom_pipe_mask;
2537 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)
2538 }; //v0
2539
2540 struct dmub_fams2_drr_stream_static_state {
2541 uint16_t nom_stretched_vtotal;
2542 uint8_t programming_delay_otg_vlines;
2543 uint8_t only_stretch_if_required;
2544 uint8_t pad[2];
2545 }; //v0
2546
2547 struct dmub_fams2_cmd_legacy_stream_static_state {
2548 uint16_t vactive_det_fill_delay_otg_vlines;
2549 uint16_t programming_delay_otg_vlines;
2550 uint32_t disallow_time_us;
2551 }; //v1
2552
2553 struct dmub_fams2_cmd_subvp_stream_static_state {
2554 uint16_t vratio_numerator;
2555 uint16_t vratio_denominator;
2556 uint16_t phantom_vtotal;
2557 uint16_t phantom_vactive;
2558 uint16_t programming_delay_otg_vlines;
2559 uint16_t prefetch_to_mall_otg_vlines;
2560 union {
2561 struct {
2562 uint8_t is_multi_planar : 1;
2563 uint8_t is_yuv420 : 1;
2564 } bits;
2565 uint8_t all;
2566 } config;
2567 uint8_t phantom_otg_inst;
2568 uint8_t phantom_pipe_mask;
2569 uint8_t pad0;
2570 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)
2571 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)];
2572 }; //v1
2573
2574 struct dmub_fams2_cmd_drr_stream_static_state {
2575 uint16_t nom_stretched_vtotal;
2576 uint16_t programming_delay_otg_vlines;
2577 uint8_t only_stretch_if_required;
2578 uint8_t pad[3];
2579 }; //v1
2580
2581 union dmub_fams2_stream_static_sub_state {
2582 struct dmub_fams2_legacy_stream_static_state legacy;
2583 struct dmub_fams2_subvp_stream_static_state subvp;
2584 struct dmub_fams2_drr_stream_static_state drr;
2585 }; //v0
2586
2587 union dmub_fams2_cmd_stream_static_sub_state {
2588 COMMON_STREAM_STATIC_SUB_STATE
2589 }; //v1
2590
2591 union dmub_fams2_stream_static_sub_state_v2 {
2592 COMMON_STREAM_STATIC_SUB_STATE
2593 }; //v2
2594
2595 struct dmub_fams2_stream_static_state {
2596 enum fams2_stream_type type;
2597 uint32_t otg_vline_time_ns;
2598 uint32_t otg_vline_time_ticks;
2599 uint16_t htotal;
2600 uint16_t vtotal; // nominal vtotal
2601 uint16_t vblank_start;
2602 uint16_t vblank_end;
2603 uint16_t max_vtotal;
2604 uint16_t allow_start_otg_vline;
2605 uint16_t allow_end_otg_vline;
2606 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed
2607 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start
2608 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution
2609 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing
2610 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline
2611 union {
2612 struct {
2613 uint8_t is_drr: 1; // stream is DRR enabled
2614 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal
2615 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank
2616 } bits;
2617 uint8_t all;
2618 } config;
2619 uint8_t otg_inst;
2620 uint8_t pipe_mask; // pipe mask for the whole config
2621 uint8_t num_planes;
2622 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)
2623 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];
2624 union dmub_fams2_stream_static_sub_state sub_state;
2625 }; //v0
2626
2627 struct dmub_fams2_cmd_stream_static_base_state {
2628 enum fams2_stream_type type;
2629 uint32_t otg_vline_time_ns;
2630 uint32_t otg_vline_time_ticks;
2631 uint16_t htotal;
2632 uint16_t vtotal; // nominal vtotal
2633 uint16_t vblank_start;
2634 uint16_t vblank_end;
2635 uint16_t max_vtotal;
2636 uint16_t allow_start_otg_vline;
2637 uint16_t allow_end_otg_vline;
2638 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed
2639 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start
2640 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution
2641 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing
2642 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline
2643 union {
2644 struct {
2645 uint8_t is_drr : 1; // stream is DRR enabled
2646 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal
2647 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank
2648 } bits;
2649 uint8_t all;
2650 } config;
2651 uint8_t otg_inst;
2652 uint8_t pipe_mask; // pipe mask for the whole config
2653 uint8_t num_planes;
2654 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)
2655 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)];
2656 }; //v1
2657
2658 struct dmub_fams2_stream_static_state_v1 {
2659 struct dmub_fams2_cmd_stream_static_base_state base;
2660 union dmub_fams2_stream_static_sub_state_v2 sub_state;
2661 }; //v1
2662
2663 /**
2664 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive
2665 * p-state request to allow latency
2666 */
2667 enum dmub_fams2_allow_delay_check_mode {
2668 /* No check for request to allow delay */
2669 FAMS2_ALLOW_DELAY_CHECK_NONE = 0,
2670 /* Check for request to allow delay */
2671 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1,
2672 /* Check for prepare to allow delay */
2673 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2,
2674 };
2675
2676 union dmub_fams2_global_feature_config {
2677 struct {
2678 uint32_t enable: 1;
2679 uint32_t enable_ppt_check: 1;
2680 uint32_t enable_stall_recovery: 1;
2681 uint32_t enable_debug: 1;
2682 uint32_t enable_offload_flip: 1;
2683 uint32_t enable_visual_confirm: 1;
2684 uint32_t allow_delay_check_mode: 2;
2685 uint32_t legacy_method_no_fams2 : 1;
2686 uint32_t reserved : 23;
2687 } bits;
2688 uint32_t all;
2689 };
2690
2691 struct dmub_cmd_fams2_global_config {
2692 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin
2693 uint32_t lock_wait_time_us; // time to forecast acquisition of lock
2694 uint32_t num_streams;
2695 union dmub_fams2_global_feature_config features;
2696 uint32_t recovery_timeout_us;
2697 uint32_t hwfq_flip_programming_delay_us;
2698 uint32_t max_allow_to_target_delta_us; // how early DCN could assert P-State allow compared to the P-State target
2699 };
2700
2701 union dmub_cmd_fams2_config {
2702 struct dmub_cmd_fams2_global_config global;
2703 struct dmub_fams2_stream_static_state stream; //v0
2704 union {
2705 struct dmub_fams2_cmd_stream_static_base_state base;
2706 union dmub_fams2_cmd_stream_static_sub_state sub_state;
2707 } stream_v1; //v1
2708 };
2709
2710 struct dmub_fams2_config_v2 {
2711 struct dmub_cmd_fams2_global_config global;
2712 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1
2713 };
2714
2715 /**
2716 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy)
2717 */
2718 struct dmub_rb_cmd_fams2 {
2719 struct dmub_cmd_header header;
2720 union dmub_cmd_fams2_config config;
2721 };
2722
2723 /**
2724 * Indirect buffer descriptor
2725 */
2726 struct dmub_ib_data {
2727 union dmub_addr src; // location of indirect buffer in memory
2728 uint16_t size; // indirect buffer size in bytes
2729 };
2730
2731 /**
2732 * DMUB rb command definition for commands passed over indirect buffer
2733 */
2734 struct dmub_rb_cmd_ib {
2735 struct dmub_cmd_header header;
2736 struct dmub_ib_data ib_data;
2737 };
2738
2739 /**
2740 * enum dmub_cmd_idle_opt_type - Idle optimization command type.
2741 */
2742 enum dmub_cmd_idle_opt_type {
2743 /**
2744 * DCN hardware restore.
2745 */
2746 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
2747
2748 /**
2749 * DCN hardware save.
2750 */
2751 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1,
2752
2753 /**
2754 * DCN hardware notify idle.
2755 */
2756 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2,
2757
2758 /**
2759 * DCN hardware notify power state.
2760 */
2761 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3,
2762
2763 /**
2764 * DCN notify to release HW.
2765 */
2766 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4,
2767 };
2768
2769 /**
2770 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
2771 */
2772 struct dmub_rb_cmd_idle_opt_dcn_restore {
2773 struct dmub_cmd_header header; /**< header */
2774 };
2775
2776 /**
2777 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
2778 */
2779 struct dmub_dcn_notify_idle_cntl_data {
2780 uint8_t driver_idle;
2781 uint8_t skip_otg_disable;
2782 uint8_t reserved[58];
2783 };
2784
2785 /**
2786 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
2787 */
2788 struct dmub_rb_cmd_idle_opt_dcn_notify_idle {
2789 struct dmub_cmd_header header; /**< header */
2790 struct dmub_dcn_notify_idle_cntl_data cntl_data;
2791 };
2792
2793 /**
2794 * enum dmub_idle_opt_dc_power_state - DC power states.
2795 */
2796 enum dmub_idle_opt_dc_power_state {
2797 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0,
2798 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1,
2799 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2,
2800 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4,
2801 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8,
2802 };
2803
2804 /**
2805 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
2806 */
2807 struct dmub_idle_opt_set_dc_power_state_data {
2808 uint8_t power_state; /**< power state */
2809 uint8_t pad[3]; /**< padding */
2810 };
2811
2812 /**
2813 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
2814 */
2815 struct dmub_rb_cmd_idle_opt_set_dc_power_state {
2816 struct dmub_cmd_header header; /**< header */
2817 struct dmub_idle_opt_set_dc_power_state_data data;
2818 };
2819
2820 /**
2821 * struct dmub_clocks - Clock update notification.
2822 */
2823 struct dmub_clocks {
2824 uint32_t dispclk_khz; /**< dispclk kHz */
2825 uint32_t dppclk_khz; /**< dppclk kHz */
2826 uint32_t dcfclk_khz; /**< dcfclk kHz */
2827 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
2828 };
2829
2830 /**
2831 * enum dmub_cmd_clk_mgr_type - Clock manager commands.
2832 */
2833 enum dmub_cmd_clk_mgr_type {
2834 /**
2835 * Notify DMCUB of clock update.
2836 */
2837 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
2838 };
2839
2840 /**
2841 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
2842 */
2843 struct dmub_rb_cmd_clk_mgr_notify_clocks {
2844 struct dmub_cmd_header header; /**< header */
2845 struct dmub_clocks clocks; /**< clock data */
2846 };
2847
2848 /**
2849 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
2850 */
2851 struct dmub_cmd_digx_encoder_control_data {
2852 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
2853 };
2854
2855 /**
2856 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
2857 */
2858 struct dmub_rb_cmd_digx_encoder_control {
2859 struct dmub_cmd_header header; /**< header */
2860 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
2861 };
2862
2863 /**
2864 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
2865 */
2866 struct dmub_cmd_set_pixel_clock_data {
2867 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
2868 };
2869
2870 /**
2871 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
2872 */
2873 struct dmub_rb_cmd_set_pixel_clock {
2874 struct dmub_cmd_header header; /**< header */
2875 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
2876 };
2877
2878 /**
2879 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
2880 */
2881 struct dmub_cmd_enable_disp_power_gating_data {
2882 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
2883 };
2884
2885 /**
2886 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
2887 */
2888 struct dmub_rb_cmd_enable_disp_power_gating {
2889 struct dmub_cmd_header header; /**< header */
2890 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
2891 };
2892
2893 /**
2894 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
2895 */
2896 struct dmub_dig_transmitter_control_data_v1_7 {
2897 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
2898 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
2899 union {
2900 uint8_t digmode; /**< enum atom_encode_mode_def */
2901 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
2902 } mode_laneset;
2903 uint8_t lanenum; /**< Number of lanes */
2904 union {
2905 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
2906 } symclk_units;
2907 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
2908 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
2909 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
2910 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
2911 uint8_t reserved1; /**< For future use */
2912 uint8_t skip_phy_ssc_reduction;
2913 uint8_t reserved2[2]; /**< For future use */
2914 uint32_t reserved3[11]; /**< For future use */
2915 };
2916
2917 /**
2918 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
2919 */
2920 union dmub_cmd_dig1_transmitter_control_data {
2921 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
2922 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
2923 };
2924
2925 /**
2926 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
2927 */
2928 struct dmub_rb_cmd_dig1_transmitter_control {
2929 struct dmub_cmd_header header; /**< header */
2930 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
2931 };
2932
2933 /**
2934 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control
2935 */
2936 struct dmub_rb_cmd_domain_control_data {
2937 uint8_t inst : 6; /**< DOMAIN instance to control */
2938 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */
2939 uint8_t reserved[3]; /**< Reserved for future use */
2940 };
2941
2942 /**
2943 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating
2944 */
2945 struct dmub_rb_cmd_domain_control {
2946 struct dmub_cmd_header header; /**< header */
2947 struct dmub_rb_cmd_domain_control_data data; /**< payload */
2948 };
2949
2950 /**
2951 * DPIA tunnel command parameters.
2952 */
2953 struct dmub_cmd_dig_dpia_control_data {
2954 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */
2955 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
2956 union {
2957 uint8_t digmode; /** enum atom_encode_mode_def */
2958 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */
2959 } mode_laneset;
2960 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */
2961 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */
2962 uint8_t hpdsel; /** =0: HPD is not assigned */
2963 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
2964 uint8_t dpia_id; /** Index of DPIA */
2965 uint8_t fec_rdy : 1;
2966 uint8_t reserved : 7;
2967 uint32_t reserved1;
2968 };
2969
2970 /**
2971 * DMUB command for DPIA tunnel control.
2972 */
2973 struct dmub_rb_cmd_dig1_dpia_control {
2974 struct dmub_cmd_header header;
2975 struct dmub_cmd_dig_dpia_control_data dpia_control;
2976 };
2977
2978 /**
2979 * SET_CONFIG Command Payload (deprecated)
2980 */
2981 struct set_config_cmd_payload {
2982 uint8_t msg_type; /* set config message type */
2983 uint8_t msg_data; /* set config message data */
2984 };
2985
2986 /**
2987 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated)
2988 */
2989 struct dmub_cmd_set_config_control_data {
2990 struct set_config_cmd_payload cmd_pkt;
2991 uint8_t instance; /* DPIA instance */
2992 uint8_t immed_status; /* Immediate status returned in case of error */
2993 };
2994
2995 /**
2996 * SET_CONFIG Request Command Payload
2997 */
2998 struct set_config_request_cmd_payload {
2999 uint8_t instance; /* DPIA instance */
3000 uint8_t immed_status; /* Immediate status returned in case of error */
3001 uint8_t msg_type; /* set config message type */
3002 uint8_t reserved;
3003 uint32_t msg_data; /* set config message data */
3004 };
3005
3006 /**
3007 * DMUB command structure for SET_CONFIG command.
3008 */
3009 struct dmub_rb_cmd_set_config_access {
3010 struct dmub_cmd_header header; /* header */
3011 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */
3012 };
3013
3014 /**
3015 * DMUB command structure for SET_CONFIG request command.
3016 */
3017 struct dmub_rb_cmd_set_config_request {
3018 struct dmub_cmd_header header; /* header */
3019 struct set_config_request_cmd_payload payload; /* set config request payload */
3020 };
3021
3022 /**
3023 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
3024 */
3025 struct dmub_cmd_mst_alloc_slots_control_data {
3026 uint8_t mst_alloc_slots; /* mst slots to be allotted */
3027 uint8_t instance; /* DPIA instance */
3028 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */
3029 uint8_t mst_slots_in_use; /* returns slots in use for error cases */
3030 };
3031
3032 /**
3033 * DMUB command structure for SET_ command.
3034 */
3035 struct dmub_rb_cmd_set_mst_alloc_slots {
3036 struct dmub_cmd_header header; /* header */
3037 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */
3038 };
3039
3040 /**
3041 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command.
3042 */
3043 struct dmub_cmd_tps_notification_data {
3044 uint8_t instance; /* DPIA instance */
3045 uint8_t tps; /* requested training pattern */
3046 uint8_t reserved1;
3047 uint8_t reserved2;
3048 };
3049
3050 /**
3051 * DMUB command structure for SET_TPS_NOTIFICATION command.
3052 */
3053 struct dmub_rb_cmd_set_tps_notification {
3054 struct dmub_cmd_header header; /* header */
3055 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */
3056 };
3057
3058 /**
3059 * DMUB command structure for DPIA HPD int enable control.
3060 */
3061 struct dmub_rb_cmd_dpia_hpd_int_enable {
3062 struct dmub_cmd_header header; /* header */
3063 uint32_t enable; /* dpia hpd interrupt enable */
3064 };
3065
3066 /**
3067 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
3068 */
3069 struct dmub_rb_cmd_dpphy_init {
3070 struct dmub_cmd_header header; /**< header */
3071 uint8_t reserved[60]; /**< reserved bits */
3072 };
3073
3074 /**
3075 * enum dp_aux_request_action - DP AUX request command listing.
3076 *
3077 * 4 AUX request command bits are shifted to high nibble.
3078 */
3079 enum dp_aux_request_action {
3080 /** I2C-over-AUX write request */
3081 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
3082 /** I2C-over-AUX read request */
3083 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
3084 /** I2C-over-AUX write status request */
3085 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
3086 /** I2C-over-AUX write request with MOT=1 */
3087 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
3088 /** I2C-over-AUX read request with MOT=1 */
3089 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
3090 /** I2C-over-AUX write status request with MOT=1 */
3091 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
3092 /** Native AUX write request */
3093 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
3094 /** Native AUX read request */
3095 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
3096 };
3097
3098 /**
3099 * enum aux_return_code_type - DP AUX process return code listing.
3100 */
3101 enum aux_return_code_type {
3102 /** AUX process succeeded */
3103 AUX_RET_SUCCESS = 0,
3104 /** AUX process failed with unknown reason */
3105 AUX_RET_ERROR_UNKNOWN,
3106 /** AUX process completed with invalid reply */
3107 AUX_RET_ERROR_INVALID_REPLY,
3108 /** AUX process timed out */
3109 AUX_RET_ERROR_TIMEOUT,
3110 /** HPD was low during AUX process */
3111 AUX_RET_ERROR_HPD_DISCON,
3112 /** Failed to acquire AUX engine */
3113 AUX_RET_ERROR_ENGINE_ACQUIRE,
3114 /** AUX request not supported */
3115 AUX_RET_ERROR_INVALID_OPERATION,
3116 /** AUX process not available */
3117 AUX_RET_ERROR_PROTOCOL_ERROR,
3118 };
3119
3120 /**
3121 * enum aux_channel_type - DP AUX channel type listing.
3122 */
3123 enum aux_channel_type {
3124 /** AUX thru Legacy DP AUX */
3125 AUX_CHANNEL_LEGACY_DDC,
3126 /** AUX thru DPIA DP tunneling */
3127 AUX_CHANNEL_DPIA
3128 };
3129
3130 /**
3131 * struct aux_transaction_parameters - DP AUX request transaction data
3132 */
3133 struct aux_transaction_parameters {
3134 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
3135 uint8_t action; /**< enum dp_aux_request_action */
3136 uint8_t length; /**< DP AUX request data length */
3137 uint8_t reserved; /**< For future use */
3138 uint32_t address; /**< DP AUX address */
3139 uint8_t data[16]; /**< DP AUX write data */
3140 };
3141
3142 /**
3143 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
3144 */
3145 struct dmub_cmd_dp_aux_control_data {
3146 uint8_t instance; /**< AUX instance or DPIA instance */
3147 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
3148 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
3149 uint8_t reserved0; /**< For future use */
3150 uint16_t timeout; /**< timeout time in us */
3151 uint16_t reserved1; /**< For future use */
3152 enum aux_channel_type type; /**< enum aux_channel_type */
3153 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
3154 };
3155
3156 /**
3157 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
3158 */
3159 struct dmub_rb_cmd_dp_aux_access {
3160 /**
3161 * Command header.
3162 */
3163 struct dmub_cmd_header header;
3164 /**
3165 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
3166 */
3167 struct dmub_cmd_dp_aux_control_data aux_control;
3168 };
3169
3170 /**
3171 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
3172 */
3173 struct dmub_rb_cmd_outbox1_enable {
3174 /**
3175 * Command header.
3176 */
3177 struct dmub_cmd_header header;
3178 /**
3179 * enable: 0x0 -> disable outbox1 notification (default value)
3180 * 0x1 -> enable outbox1 notification
3181 */
3182 uint32_t enable;
3183 };
3184
3185 /* DP AUX Reply command - OutBox Cmd */
3186 /**
3187 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
3188 */
3189 struct aux_reply_data {
3190 /**
3191 * Aux cmd
3192 */
3193 uint8_t command;
3194 /**
3195 * Aux reply data length (max: 16 bytes)
3196 */
3197 uint8_t length;
3198 /**
3199 * Alignment only
3200 */
3201 uint8_t pad[2];
3202 /**
3203 * Aux reply data
3204 */
3205 uint8_t data[16];
3206 };
3207
3208 /**
3209 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
3210 */
3211 struct aux_reply_control_data {
3212 /**
3213 * Reserved for future use
3214 */
3215 uint32_t handle;
3216 /**
3217 * Aux Instance
3218 */
3219 uint8_t instance;
3220 /**
3221 * Aux transaction result: definition in enum aux_return_code_type
3222 */
3223 uint8_t result;
3224 /**
3225 * Alignment only
3226 */
3227 uint16_t pad;
3228 };
3229
3230 /**
3231 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
3232 */
3233 struct dmub_rb_cmd_dp_aux_reply {
3234 /**
3235 * Command header.
3236 */
3237 struct dmub_cmd_header header;
3238 /**
3239 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
3240 */
3241 struct aux_reply_control_data control;
3242 /**
3243 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
3244 */
3245 struct aux_reply_data reply_data;
3246 };
3247
3248 /* DP HPD Notify command - OutBox Cmd */
3249 /**
3250 * DP HPD Type
3251 */
3252 enum dp_hpd_type {
3253 /**
3254 * Normal DP HPD
3255 */
3256 DP_HPD = 0,
3257 /**
3258 * DP HPD short pulse
3259 */
3260 DP_IRQ = 1,
3261 /**
3262 * Failure to acquire DP HPD state
3263 */
3264 DP_NONE_HPD = 2
3265 };
3266
3267 /**
3268 * DP HPD Status
3269 */
3270 enum dp_hpd_status {
3271 /**
3272 * DP_HPD status low
3273 */
3274 DP_HPD_UNPLUG = 0,
3275 /**
3276 * DP_HPD status high
3277 */
3278 DP_HPD_PLUG
3279 };
3280
3281 /**
3282 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
3283 */
3284 struct dp_hpd_data {
3285 /**
3286 * DP HPD instance
3287 */
3288 uint8_t instance;
3289 /**
3290 * HPD type
3291 */
3292 uint8_t hpd_type;
3293 /**
3294 * HPD status: only for type: DP_HPD to indicate status
3295 */
3296 uint8_t hpd_status;
3297 /**
3298 * Alignment only
3299 */
3300 uint8_t pad;
3301 };
3302
3303 /**
3304 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
3305 */
3306 struct dmub_rb_cmd_dp_hpd_notify {
3307 /**
3308 * Command header.
3309 */
3310 struct dmub_cmd_header header;
3311 /**
3312 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
3313 */
3314 struct dp_hpd_data hpd_data;
3315 };
3316
3317 /**
3318 * Definition of a SET_CONFIG reply from DPOA.
3319 */
3320 enum set_config_status {
3321 SET_CONFIG_PENDING = 0,
3322 SET_CONFIG_ACK_RECEIVED,
3323 SET_CONFIG_RX_TIMEOUT,
3324 SET_CONFIG_UNKNOWN_ERROR,
3325 };
3326
3327 /**
3328 * Definition of a set_config reply
3329 */
3330 struct set_config_reply_control_data {
3331 uint8_t instance; /* DPIA Instance */
3332 uint8_t status; /* Set Config reply */
3333 uint16_t pad; /* Alignment */
3334 };
3335
3336 /**
3337 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.
3338 */
3339 struct dmub_rb_cmd_dp_set_config_reply {
3340 struct dmub_cmd_header header;
3341 struct set_config_reply_control_data set_config_reply_control;
3342 };
3343
3344 /**
3345 * Definition of a DPIA notification header
3346 */
3347 struct dpia_notification_header {
3348 uint8_t instance; /**< DPIA Instance */
3349 uint8_t reserved[3];
3350 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */
3351 };
3352
3353 /**
3354 * Definition of the common data struct of DPIA notification
3355 */
3356 struct dpia_notification_common {
3357 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)
3358 - sizeof(struct dpia_notification_header)];
3359 };
3360
3361 /**
3362 * Definition of a DPIA notification data
3363 */
3364 struct dpia_bw_allocation_notify_data {
3365 union {
3366 struct {
3367 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */
3368 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */
3369 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */
3370 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */
3371 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */
3372 uint16_t reserved: 11; /**< Reserved */
3373 } bits;
3374
3375 uint16_t flags;
3376 };
3377
3378 uint8_t cm_id; /**< CM ID */
3379 uint8_t group_id; /**< Group ID */
3380 uint8_t granularity; /**< BW Allocation Granularity */
3381 uint8_t estimated_bw; /**< Estimated_BW */
3382 uint8_t allocated_bw; /**< Allocated_BW */
3383 uint8_t reserved;
3384 };
3385
3386 /**
3387 * union dpia_notify_data_type - DPIA Notification in Outbox command
3388 */
3389 union dpia_notification_data {
3390 /**
3391 * DPIA Notification for common data struct
3392 */
3393 struct dpia_notification_common common_data;
3394
3395 /**
3396 * DPIA Notification for DP BW Allocation support
3397 */
3398 struct dpia_bw_allocation_notify_data dpia_bw_alloc;
3399 };
3400
3401 /**
3402 * Definition of a DPIA notification payload
3403 */
3404 struct dpia_notification_payload {
3405 struct dpia_notification_header header;
3406 union dpia_notification_data data; /**< DPIA notification payload data */
3407 };
3408
3409 /**
3410 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command.
3411 */
3412 struct dmub_rb_cmd_dpia_notification {
3413 struct dmub_cmd_header header; /**< DPIA notification header */
3414 struct dpia_notification_payload payload; /**< DPIA notification payload */
3415 };
3416
3417 /**
3418 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
3419 */
3420 struct dmub_cmd_hpd_state_query_data {
3421 uint8_t instance; /**< HPD instance or DPIA instance */
3422 uint8_t result; /**< For returning HPD state */
3423 uint16_t pad; /** < Alignment */
3424 enum aux_channel_type ch_type; /**< enum aux_channel_type */
3425 enum aux_return_code_type status; /**< for returning the status of command */
3426 };
3427
3428 /**
3429 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
3430 */
3431 struct dmub_rb_cmd_query_hpd_state {
3432 /**
3433 * Command header.
3434 */
3435 struct dmub_cmd_header header;
3436 /**
3437 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
3438 */
3439 struct dmub_cmd_hpd_state_query_data data;
3440 };
3441
3442 /**
3443 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data.
3444 */
3445 struct dmub_rb_cmd_hpd_sense_notify_data {
3446 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */
3447 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */
3448 };
3449
3450 /**
3451 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command.
3452 */
3453 struct dmub_rb_cmd_hpd_sense_notify {
3454 struct dmub_cmd_header header; /**< header */
3455 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */
3456 };
3457
3458 /*
3459 * Command IDs should be treated as stable ABI.
3460 * Do not reuse or modify IDs.
3461 */
3462
3463 /**
3464 * PSR command sub-types.
3465 */
3466 enum dmub_cmd_psr_type {
3467 /**
3468 * Set PSR version support.
3469 */
3470 DMUB_CMD__PSR_SET_VERSION = 0,
3471 /**
3472 * Copy driver-calculated parameters to PSR state.
3473 */
3474 DMUB_CMD__PSR_COPY_SETTINGS = 1,
3475 /**
3476 * Enable PSR.
3477 */
3478 DMUB_CMD__PSR_ENABLE = 2,
3479
3480 /**
3481 * Disable PSR.
3482 */
3483 DMUB_CMD__PSR_DISABLE = 3,
3484
3485 /**
3486 * Set PSR level.
3487 * PSR level is a 16-bit value dicated by driver that
3488 * will enable/disable different functionality.
3489 */
3490 DMUB_CMD__PSR_SET_LEVEL = 4,
3491
3492 /**
3493 * Forces PSR enabled until an explicit PSR disable call.
3494 */
3495 DMUB_CMD__PSR_FORCE_STATIC = 5,
3496 /**
3497 * Set vtotal in psr active for FreeSync PSR.
3498 */
3499 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
3500 /**
3501 * Set PSR power option
3502 */
3503 DMUB_CMD__SET_PSR_POWER_OPT = 7,
3504 };
3505
3506 /**
3507 * Different PSR residency modes.
3508 * Different modes change the definition of PSR residency.
3509 */
3510 enum psr_residency_mode {
3511 PSR_RESIDENCY_MODE_PHY = 0,
3512 PSR_RESIDENCY_MODE_ALPM,
3513 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
3514 /* Do not add below. */
3515 PSR_RESIDENCY_MODE_LAST_ELEMENT,
3516 };
3517
3518 enum dmub_cmd_fams_type {
3519 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0,
3520 DMUB_CMD__FAMS_DRR_UPDATE = 1,
3521 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd
3522 /**
3523 * For SubVP set manual trigger in FW because it
3524 * triggers DRR_UPDATE_PENDING which SubVP relies
3525 * on (for any SubVP cases that use a DRR display)
3526 */
3527 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
3528 DMUB_CMD__FAMS2_CONFIG = 4,
3529 DMUB_CMD__FAMS2_DRR_UPDATE = 5,
3530 DMUB_CMD__FAMS2_FLIP = 6,
3531 DMUB_CMD__FAMS2_IB_CONFIG = 7,
3532 };
3533
3534 /**
3535 * PSR versions.
3536 */
3537 enum psr_version {
3538 /**
3539 * PSR version 1.
3540 */
3541 PSR_VERSION_1 = 0,
3542 /**
3543 * Freesync PSR SU.
3544 */
3545 PSR_VERSION_SU_1 = 1,
3546 /**
3547 * PSR not supported.
3548 */
3549 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide
3550 };
3551
3552 /**
3553 * PHY Link rate for DP.
3554 */
3555 enum phy_link_rate {
3556 /**
3557 * not supported.
3558 */
3559 PHY_RATE_UNKNOWN = 0,
3560 /**
3561 * Rate_1 (RBR) - 1.62 Gbps/Lane
3562 */
3563 PHY_RATE_162 = 1,
3564 /**
3565 * Rate_2 - 2.16 Gbps/Lane
3566 */
3567 PHY_RATE_216 = 2,
3568 /**
3569 * Rate_3 - 2.43 Gbps/Lane
3570 */
3571 PHY_RATE_243 = 3,
3572 /**
3573 * Rate_4 (HBR) - 2.70 Gbps/Lane
3574 */
3575 PHY_RATE_270 = 4,
3576 /**
3577 * Rate_5 (RBR2)- 3.24 Gbps/Lane
3578 */
3579 PHY_RATE_324 = 5,
3580 /**
3581 * Rate_6 - 4.32 Gbps/Lane
3582 */
3583 PHY_RATE_432 = 6,
3584 /**
3585 * Rate_7 (HBR2)- 5.40 Gbps/Lane
3586 */
3587 PHY_RATE_540 = 7,
3588 /**
3589 * Rate_8 (HBR3)- 8.10 Gbps/Lane
3590 */
3591 PHY_RATE_810 = 8,
3592 /**
3593 * UHBR10 - 10.0 Gbps/Lane
3594 */
3595 PHY_RATE_1000 = 9,
3596 /**
3597 * UHBR13.5 - 13.5 Gbps/Lane
3598 */
3599 PHY_RATE_1350 = 10,
3600 /**
3601 * UHBR10 - 20.0 Gbps/Lane
3602 */
3603 PHY_RATE_2000 = 11,
3604
3605 PHY_RATE_675 = 12,
3606 /**
3607 * Rate 12 - 6.75 Gbps/Lane
3608 */
3609 };
3610
3611 /**
3612 * enum dmub_phy_fsm_state - PHY FSM states.
3613 * PHY FSM state to transit to during PSR enable/disable.
3614 */
3615 enum dmub_phy_fsm_state {
3616 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
3617 DMUB_PHY_FSM_RESET,
3618 DMUB_PHY_FSM_RESET_RELEASED,
3619 DMUB_PHY_FSM_SRAM_LOAD_DONE,
3620 DMUB_PHY_FSM_INITIALIZED,
3621 DMUB_PHY_FSM_CALIBRATED,
3622 DMUB_PHY_FSM_CALIBRATED_LP,
3623 DMUB_PHY_FSM_CALIBRATED_PG,
3624 DMUB_PHY_FSM_POWER_DOWN,
3625 DMUB_PHY_FSM_PLL_EN,
3626 DMUB_PHY_FSM_TX_EN,
3627 DMUB_PHY_FSM_TX_EN_TEST_MODE,
3628 DMUB_PHY_FSM_FAST_LP,
3629 DMUB_PHY_FSM_P2_PLL_OFF_CPM,
3630 DMUB_PHY_FSM_P2_PLL_OFF_PG,
3631 DMUB_PHY_FSM_P2_PLL_OFF,
3632 DMUB_PHY_FSM_P2_PLL_ON,
3633 };
3634
3635 /**
3636 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
3637 */
3638 struct dmub_cmd_psr_copy_settings_data {
3639 /**
3640 * Flags that can be set by driver to change some PSR behaviour.
3641 */
3642 union dmub_psr_debug_flags debug;
3643 /**
3644 * 16-bit value dicated by driver that will enable/disable different functionality.
3645 */
3646 uint16_t psr_level;
3647 /**
3648 * DPP HW instance.
3649 */
3650 uint8_t dpp_inst;
3651 /**
3652 * MPCC HW instance.
3653 * Not used in dmub fw,
3654 * dmub fw will get active opp by reading odm registers.
3655 */
3656 uint8_t mpcc_inst;
3657 /**
3658 * OPP HW instance.
3659 * Not used in dmub fw,
3660 * dmub fw will get active opp by reading odm registers.
3661 */
3662 uint8_t opp_inst;
3663 /**
3664 * OTG HW instance.
3665 */
3666 uint8_t otg_inst;
3667 /**
3668 * DIG FE HW instance.
3669 */
3670 uint8_t digfe_inst;
3671 /**
3672 * DIG BE HW instance.
3673 */
3674 uint8_t digbe_inst;
3675 /**
3676 * DP PHY HW instance.
3677 */
3678 uint8_t dpphy_inst;
3679 /**
3680 * AUX HW instance.
3681 */
3682 uint8_t aux_inst;
3683 /**
3684 * Determines if SMU optimzations are enabled/disabled.
3685 */
3686 uint8_t smu_optimizations_en;
3687 /**
3688 * Unused.
3689 * TODO: Remove.
3690 */
3691 uint8_t frame_delay;
3692 /**
3693 * If RFB setup time is greater than the total VBLANK time,
3694 * it is not possible for the sink to capture the video frame
3695 * in the same frame the SDP is sent. In this case,
3696 * the frame capture indication bit should be set and an extra
3697 * static frame should be transmitted to the sink.
3698 */
3699 uint8_t frame_cap_ind;
3700 /**
3701 * Granularity of Y offset supported by sink.
3702 */
3703 uint8_t su_y_granularity;
3704 /**
3705 * Indicates whether sink should start capturing
3706 * immediately following active scan line,
3707 * or starting with the 2nd active scan line.
3708 */
3709 uint8_t line_capture_indication;
3710 /**
3711 * Multi-display optimizations are implemented on certain ASICs.
3712 */
3713 uint8_t multi_disp_optimizations_en;
3714 /**
3715 * The last possible line SDP may be transmitted without violating
3716 * the RFB setup time or entering the active video frame.
3717 */
3718 uint16_t init_sdp_deadline;
3719 /**
3720 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
3721 */
3722 uint8_t rate_control_caps;
3723 /*
3724 * Force PSRSU always doing full frame update
3725 */
3726 uint8_t force_ffu_mode;
3727 /**
3728 * Length of each horizontal line in us.
3729 */
3730 uint32_t line_time_in_us;
3731 /**
3732 * FEC enable status in driver
3733 */
3734 uint8_t fec_enable_status;
3735 /**
3736 * FEC re-enable delay when PSR exit.
3737 * unit is 100us, range form 0~255(0xFF).
3738 */
3739 uint8_t fec_enable_delay_in100us;
3740 /**
3741 * PSR control version.
3742 */
3743 uint8_t cmd_version;
3744 /**
3745 * Panel Instance.
3746 * Panel instance to identify which psr_state to use
3747 * Currently the support is only for 0 or 1
3748 */
3749 uint8_t panel_inst;
3750 /*
3751 * DSC enable status in driver
3752 */
3753 uint8_t dsc_enable_status;
3754 /*
3755 * Use FSM state for PSR power up/down
3756 */
3757 uint8_t use_phy_fsm;
3758 /**
3759 * frame delay for frame re-lock
3760 */
3761 uint8_t relock_delay_frame_cnt;
3762 /**
3763 * esd recovery indicate.
3764 */
3765 uint8_t esd_recovery;
3766 /**
3767 * DSC Slice height.
3768 */
3769 uint16_t dsc_slice_height;
3770 /**
3771 * Some panels request main link off before xth vertical line
3772 */
3773 uint16_t poweroff_before_vertical_line;
3774 /**
3775 * Some panels cannot handle idle pattern during PSR entry.
3776 * To power down phy before disable stream to avoid sending
3777 * idle pattern.
3778 */
3779 uint8_t power_down_phy_before_disable_stream;
3780 };
3781
3782 /**
3783 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
3784 */
3785 struct dmub_rb_cmd_psr_copy_settings {
3786 /**
3787 * Command header.
3788 */
3789 struct dmub_cmd_header header;
3790 /**
3791 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
3792 */
3793 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
3794 };
3795
3796 /**
3797 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
3798 */
3799 struct dmub_cmd_psr_set_level_data {
3800 /**
3801 * 16-bit value dicated by driver that will enable/disable different functionality.
3802 */
3803 uint16_t psr_level;
3804 /**
3805 * PSR control version.
3806 */
3807 uint8_t cmd_version;
3808 /**
3809 * Panel Instance.
3810 * Panel instance to identify which psr_state to use
3811 * Currently the support is only for 0 or 1
3812 */
3813 uint8_t panel_inst;
3814 };
3815
3816 /**
3817 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
3818 */
3819 struct dmub_rb_cmd_psr_set_level {
3820 /**
3821 * Command header.
3822 */
3823 struct dmub_cmd_header header;
3824 /**
3825 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
3826 */
3827 struct dmub_cmd_psr_set_level_data psr_set_level_data;
3828 };
3829
3830 struct dmub_rb_cmd_psr_enable_data {
3831 /**
3832 * PSR control version.
3833 */
3834 uint8_t cmd_version;
3835 /**
3836 * Panel Instance.
3837 * Panel instance to identify which psr_state to use
3838 * Currently the support is only for 0 or 1
3839 */
3840 uint8_t panel_inst;
3841 /**
3842 * Phy state to enter.
3843 * Values to use are defined in dmub_phy_fsm_state
3844 */
3845 uint8_t phy_fsm_state;
3846 /**
3847 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
3848 * Set this using enum phy_link_rate.
3849 * This does not support HDMI/DP2 for now.
3850 */
3851 uint8_t phy_rate;
3852 };
3853
3854 /**
3855 * Definition of a DMUB_CMD__PSR_ENABLE command.
3856 * PSR enable/disable is controlled using the sub_type.
3857 */
3858 struct dmub_rb_cmd_psr_enable {
3859 /**
3860 * Command header.
3861 */
3862 struct dmub_cmd_header header;
3863
3864 struct dmub_rb_cmd_psr_enable_data data;
3865 };
3866
3867 /**
3868 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
3869 */
3870 struct dmub_cmd_psr_set_version_data {
3871 /**
3872 * PSR version that FW should implement.
3873 */
3874 enum psr_version version;
3875 /**
3876 * PSR control version.
3877 */
3878 uint8_t cmd_version;
3879 /**
3880 * Panel Instance.
3881 * Panel instance to identify which psr_state to use
3882 * Currently the support is only for 0 or 1
3883 */
3884 uint8_t panel_inst;
3885 /**
3886 * Explicit padding to 4 byte boundary.
3887 */
3888 uint8_t pad[2];
3889 };
3890
3891 /**
3892 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
3893 */
3894 struct dmub_rb_cmd_psr_set_version {
3895 /**
3896 * Command header.
3897 */
3898 struct dmub_cmd_header header;
3899 /**
3900 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
3901 */
3902 struct dmub_cmd_psr_set_version_data psr_set_version_data;
3903 };
3904
3905 struct dmub_cmd_psr_force_static_data {
3906 /**
3907 * PSR control version.
3908 */
3909 uint8_t cmd_version;
3910 /**
3911 * Panel Instance.
3912 * Panel instance to identify which psr_state to use
3913 * Currently the support is only for 0 or 1
3914 */
3915 uint8_t panel_inst;
3916 /**
3917 * Explicit padding to 4 byte boundary.
3918 */
3919 uint8_t pad[2];
3920 };
3921
3922 /**
3923 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
3924 */
3925 struct dmub_rb_cmd_psr_force_static {
3926 /**
3927 * Command header.
3928 */
3929 struct dmub_cmd_header header;
3930 /**
3931 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
3932 */
3933 struct dmub_cmd_psr_force_static_data psr_force_static_data;
3934 };
3935
3936 /**
3937 * PSR SU debug flags.
3938 */
3939 union dmub_psr_su_debug_flags {
3940 /**
3941 * PSR SU debug flags.
3942 */
3943 struct {
3944 /**
3945 * Update dirty rect in SW only.
3946 */
3947 uint8_t update_dirty_rect_only : 1;
3948 /**
3949 * Reset the cursor/plane state before processing the call.
3950 */
3951 uint8_t reset_state : 1;
3952 } bitfields;
3953
3954 /**
3955 * Union for debug flags.
3956 */
3957 uint32_t u32All;
3958 };
3959
3960 /**
3961 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
3962 * This triggers a selective update for PSR SU.
3963 */
3964 struct dmub_cmd_update_dirty_rect_data {
3965 /**
3966 * Dirty rects from OS.
3967 */
3968 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
3969 /**
3970 * PSR SU debug flags.
3971 */
3972 union dmub_psr_su_debug_flags debug_flags;
3973 /**
3974 * Pipe index.
3975 */
3976 uint8_t pipe_idx;
3977 /**
3978 * Number of dirty rects.
3979 */
3980 uint8_t dirty_rect_count;
3981 /**
3982 * dirty rects cmd version.
3983 */
3984 uint8_t cmd_version;
3985 /**
3986 * Panel Instance.
3987 * Panel instance to identify which psr_state to use
3988 * Currently the support is only for 0 or 1
3989 */
3990 uint8_t panel_inst;
3991 /**
3992 * OTG HW instance
3993 */
3994 uint8_t otg_inst;
3995 /**
3996 * Padding for 4 byte alignment
3997 */
3998 uint8_t padding[3];
3999 };
4000
4001 /**
4002 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
4003 */
4004 struct dmub_rb_cmd_update_dirty_rect {
4005 /**
4006 * Command header.
4007 */
4008 struct dmub_cmd_header header;
4009 /**
4010 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
4011 */
4012 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
4013 };
4014
4015 /**
4016 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
4017 */
4018 union dmub_reg_cursor_control_cfg {
4019 struct {
4020 uint32_t cur_enable: 1;
4021 uint32_t reser0: 3;
4022 uint32_t cur_2x_magnify: 1;
4023 uint32_t reser1: 3;
4024 uint32_t mode: 3;
4025 uint32_t reser2: 5;
4026 uint32_t pitch: 2;
4027 uint32_t reser3: 6;
4028 uint32_t line_per_chunk: 5;
4029 uint32_t reser4: 3;
4030 } bits;
4031 uint32_t raw;
4032 };
4033 struct dmub_cursor_position_cache_hubp {
4034 union dmub_reg_cursor_control_cfg cur_ctl;
4035 union dmub_reg_position_cfg {
4036 struct {
4037 uint32_t cur_x_pos: 16;
4038 uint32_t cur_y_pos: 16;
4039 } bits;
4040 uint32_t raw;
4041 } position;
4042 union dmub_reg_hot_spot_cfg {
4043 struct {
4044 uint32_t hot_x: 16;
4045 uint32_t hot_y: 16;
4046 } bits;
4047 uint32_t raw;
4048 } hot_spot;
4049 union dmub_reg_dst_offset_cfg {
4050 struct {
4051 uint32_t dst_x_offset: 13;
4052 uint32_t reserved: 19;
4053 } bits;
4054 uint32_t raw;
4055 } dst_offset;
4056 };
4057
4058 union dmub_reg_cur0_control_cfg {
4059 struct {
4060 uint32_t cur0_enable: 1;
4061 uint32_t expansion_mode: 1;
4062 uint32_t reser0: 1;
4063 uint32_t cur0_rom_en: 1;
4064 uint32_t mode: 3;
4065 uint32_t reserved: 25;
4066 } bits;
4067 uint32_t raw;
4068 };
4069 struct dmub_cursor_position_cache_dpp {
4070 union dmub_reg_cur0_control_cfg cur0_ctl;
4071 };
4072 struct dmub_cursor_position_cfg {
4073 struct dmub_cursor_position_cache_hubp pHubp;
4074 struct dmub_cursor_position_cache_dpp pDpp;
4075 uint8_t pipe_idx;
4076 /*
4077 * Padding is required. To be 4 Bytes Aligned.
4078 */
4079 uint8_t padding[3];
4080 };
4081
4082 struct dmub_cursor_attribute_cache_hubp {
4083 uint32_t SURFACE_ADDR_HIGH;
4084 uint32_t SURFACE_ADDR;
4085 union dmub_reg_cursor_control_cfg cur_ctl;
4086 union dmub_reg_cursor_size_cfg {
4087 struct {
4088 uint32_t width: 16;
4089 uint32_t height: 16;
4090 } bits;
4091 uint32_t raw;
4092 } size;
4093 union dmub_reg_cursor_settings_cfg {
4094 struct {
4095 uint32_t dst_y_offset: 8;
4096 uint32_t chunk_hdl_adjust: 2;
4097 uint32_t reserved: 22;
4098 } bits;
4099 uint32_t raw;
4100 } settings;
4101 };
4102 struct dmub_cursor_attribute_cache_dpp {
4103 union dmub_reg_cur0_control_cfg cur0_ctl;
4104 };
4105 struct dmub_cursor_attributes_cfg {
4106 struct dmub_cursor_attribute_cache_hubp aHubp;
4107 struct dmub_cursor_attribute_cache_dpp aDpp;
4108 };
4109
4110 struct dmub_cmd_update_cursor_payload0 {
4111 /**
4112 * Cursor dirty rects.
4113 */
4114 struct dmub_rect cursor_rect;
4115 /**
4116 * PSR SU debug flags.
4117 */
4118 union dmub_psr_su_debug_flags debug_flags;
4119 /**
4120 * Cursor enable/disable.
4121 */
4122 uint8_t enable;
4123 /**
4124 * Pipe index.
4125 */
4126 uint8_t pipe_idx;
4127 /**
4128 * Cursor update cmd version.
4129 */
4130 uint8_t cmd_version;
4131 /**
4132 * Panel Instance.
4133 * Panel instance to identify which psr_state to use
4134 * Currently the support is only for 0 or 1
4135 */
4136 uint8_t panel_inst;
4137 /**
4138 * Cursor Position Register.
4139 * Registers contains Hubp & Dpp modules
4140 */
4141 struct dmub_cursor_position_cfg position_cfg;
4142 /**
4143 * OTG HW instance
4144 */
4145 uint8_t otg_inst;
4146 /**
4147 * Padding for 4 byte alignment
4148 */
4149 uint8_t padding[3];
4150 };
4151
4152 struct dmub_cmd_update_cursor_payload1 {
4153 struct dmub_cursor_attributes_cfg attribute_cfg;
4154 };
4155
4156 union dmub_cmd_update_cursor_info_data {
4157 struct dmub_cmd_update_cursor_payload0 payload0;
4158 struct dmub_cmd_update_cursor_payload1 payload1;
4159 };
4160 /**
4161 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
4162 */
4163 struct dmub_rb_cmd_update_cursor_info {
4164 /**
4165 * Command header.
4166 */
4167 struct dmub_cmd_header header;
4168 /**
4169 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
4170 */
4171 union dmub_cmd_update_cursor_info_data update_cursor_info_data;
4172 };
4173
4174 /**
4175 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
4176 */
4177 struct dmub_cmd_psr_set_vtotal_data {
4178 /**
4179 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
4180 */
4181 uint16_t psr_vtotal_idle;
4182 /**
4183 * PSR control version.
4184 */
4185 uint8_t cmd_version;
4186 /**
4187 * Panel Instance.
4188 * Panel instance to identify which psr_state to use
4189 * Currently the support is only for 0 or 1
4190 */
4191 uint8_t panel_inst;
4192 /*
4193 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
4194 */
4195 uint16_t psr_vtotal_su;
4196 /**
4197 * Explicit padding to 4 byte boundary.
4198 */
4199 uint8_t pad2[2];
4200 };
4201
4202 /**
4203 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
4204 */
4205 struct dmub_rb_cmd_psr_set_vtotal {
4206 /**
4207 * Command header.
4208 */
4209 struct dmub_cmd_header header;
4210 /**
4211 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
4212 */
4213 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
4214 };
4215
4216 /**
4217 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
4218 */
4219 struct dmub_cmd_psr_set_power_opt_data {
4220 /**
4221 * PSR control version.
4222 */
4223 uint8_t cmd_version;
4224 /**
4225 * Panel Instance.
4226 * Panel instance to identify which psr_state to use
4227 * Currently the support is only for 0 or 1
4228 */
4229 uint8_t panel_inst;
4230 /**
4231 * Explicit padding to 4 byte boundary.
4232 */
4233 uint8_t pad[2];
4234 /**
4235 * PSR power option
4236 */
4237 uint32_t power_opt;
4238 };
4239
4240 /**
4241 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
4242 */
4243 struct dmub_rb_cmd_psr_set_power_opt {
4244 /**
4245 * Command header.
4246 */
4247 struct dmub_cmd_header header;
4248 /**
4249 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
4250 */
4251 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
4252 };
4253
4254 enum dmub_alpm_mode {
4255 ALPM_AUXWAKE = 0,
4256 ALPM_AUXLESS = 1,
4257 ALPM_UNSUPPORTED = 2,
4258 };
4259
4260 /**
4261 * Definition of Replay Residency GPINT command.
4262 * Bit[0] - Residency mode for Revision 0
4263 * Bit[1] - Enable/Disable state
4264 * Bit[2-3] - Revision number
4265 * Bit[4-7] - Residency mode for Revision 1
4266 * Bit[8] - Panel instance
4267 * Bit[9-15] - Reserved
4268 */
4269
4270 enum pr_residency_mode {
4271 PR_RESIDENCY_MODE_PHY = 0x0,
4272 PR_RESIDENCY_MODE_ALPM,
4273 PR_RESIDENCY_MODE_IPS2,
4274 PR_RESIDENCY_MODE_FRAME_CNT,
4275 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
4276 };
4277
4278 #define REPLAY_RESIDENCY_MODE_SHIFT (0)
4279 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1)
4280 #define REPLAY_RESIDENCY_REVISION_SHIFT (2)
4281 #define REPLAY_RESIDENCY_MODE2_SHIFT (4)
4282
4283 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
4284 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT)
4285 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
4286
4287 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT)
4288 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT)
4289 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT)
4290 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT)
4291
4292 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
4293 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT)
4294 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
4295
4296 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT)
4297 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT)
4298 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT)
4299
4300 /**
4301 * Definition of a replay_state.
4302 */
4303 enum replay_state {
4304 REPLAY_STATE_0 = 0x0,
4305 REPLAY_STATE_1 = 0x10,
4306 REPLAY_STATE_1A = 0x11,
4307 REPLAY_STATE_2 = 0x20,
4308 REPLAY_STATE_2A = 0x21,
4309 REPLAY_STATE_3 = 0x30,
4310 REPLAY_STATE_3INIT = 0x31,
4311 REPLAY_STATE_4 = 0x40,
4312 REPLAY_STATE_4A = 0x41,
4313 REPLAY_STATE_4B = 0x42,
4314 REPLAY_STATE_4C = 0x43,
4315 REPLAY_STATE_4D = 0x44,
4316 REPLAY_STATE_4E = 0x45,
4317 REPLAY_STATE_4B_LOCKED = 0x4A,
4318 REPLAY_STATE_4C_UNLOCKED = 0x4B,
4319 REPLAY_STATE_5 = 0x50,
4320 REPLAY_STATE_5A = 0x51,
4321 REPLAY_STATE_5B = 0x52,
4322 REPLAY_STATE_5A_LOCKED = 0x5A,
4323 REPLAY_STATE_5B_UNLOCKED = 0x5B,
4324 REPLAY_STATE_6 = 0x60,
4325 REPLAY_STATE_6A = 0x61,
4326 REPLAY_STATE_6B = 0x62,
4327 REPLAY_STATE_INVALID = 0xFF,
4328 };
4329
4330 /**
4331 * Definition of a panel replay state
4332 */
4333 enum pr_state {
4334 PR_STATE_0 = 0x00, // State 0 steady state
4335 // Pending SDP and Unlock before back to State 0
4336 PR_STATE_0_PENDING_SDP_AND_UNLOCK = 0x01,
4337 PR_STATE_1 = 0x10, // State 1
4338 PR_STATE_2 = 0x20, // State 2 steady state
4339 // Pending frame transmission before transition to State 2
4340 PR_STATE_2_PENDING_FRAME_TRANSMISSION = 0x30,
4341 // Active and Powered Up
4342 PR_STATE_2_POWERED = 0x31,
4343 // Active and Powered Down, but need to blank HUBP after DPG_EN latch
4344 PR_STATE_2_PENDING_HUBP_BLANK = 0x32,
4345 // Active and Pending Power Up
4346 PR_STATE_2_PENDING_POWER_UP = 0x33,
4347 // Active and Powered Up, Pending DPG latch
4348 PR_STATE_2_PENDING_LOCK = 0x34,
4349 // Active and Powered Up, Pending SDP and Unlock
4350 PR_STATE_2_PENDING_SDP_AND_UNLOCK = 0x35,
4351 // Pending transmission of AS SDP for timing sync, but no rfb update
4352 PR_STATE_2_PENDING_AS_SDP = 0x36,
4353 // Invalid
4354 PR_STATE_INVALID = 0xFF,
4355 };
4356
4357 /**
4358 * Replay command sub-types.
4359 */
4360 enum dmub_cmd_replay_type {
4361 /**
4362 * Copy driver-calculated parameters to REPLAY state.
4363 */
4364 DMUB_CMD__REPLAY_COPY_SETTINGS = 0,
4365 /**
4366 * Enable REPLAY.
4367 */
4368 DMUB_CMD__REPLAY_ENABLE = 1,
4369 /**
4370 * Set Replay power option.
4371 */
4372 DMUB_CMD__SET_REPLAY_POWER_OPT = 2,
4373 /**
4374 * Set coasting vtotal.
4375 */
4376 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3,
4377 /**
4378 * Set power opt and coasting vtotal.
4379 */
4380 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4,
4381 /**
4382 * Set disabled iiming sync.
4383 */
4384 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5,
4385 /**
4386 * Set Residency Frameupdate Timer.
4387 */
4388 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6,
4389 /**
4390 * Set pseudo vtotal
4391 */
4392 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7,
4393 /**
4394 * Set adaptive sync sdp enabled
4395 */
4396 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8,
4397 /**
4398 * Set Replay General command.
4399 */
4400 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16,
4401 };
4402
4403 /*
4404 * Panel Replay sub-types
4405 */
4406 enum dmub_cmd_panel_replay_type {
4407 DMUB_CMD__PR_ENABLE = 0,
4408 DMUB_CMD__PR_COPY_SETTINGS = 1,
4409 DMUB_CMD__PR_UPDATE_STATE = 2,
4410 DMUB_CMD__PR_GENERAL_CMD = 3,
4411 };
4412
4413 enum dmub_cmd_panel_replay_state_update_subtype {
4414 PR_STATE_UPDATE_COASTING_VTOTAL = 0x1,
4415 PR_STATE_UPDATE_SYNC_MODE = 0x2,
4416 PR_STATE_UPDATE_RUNTIME_FLAGS = 0x3,
4417 };
4418
4419 enum dmub_cmd_panel_replay_general_subtype {
4420 PR_GENERAL_CMD_DEBUG_OPTION = 0x1,
4421 };
4422
4423 /**
4424 * Replay general command sub-types.
4425 */
4426 enum dmub_cmd_replay_general_subtype {
4427 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1,
4428 /**
4429 * TODO: For backward compatible, allow new command only.
4430 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED,
4431 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER,
4432 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL,
4433 */
4434 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP,
4435 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION,
4436 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS,
4437 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE,
4438 REPLAY_GENERAL_CMD_VIDEO_CONFERENCING,
4439 REPLAY_GENERAL_CMD_SET_CONTINUOUSLY_RESYNC,
4440 };
4441
4442 struct dmub_alpm_auxless_data {
4443 uint16_t lfps_setup_ns;
4444 uint16_t lfps_period_ns;
4445 uint16_t lfps_silence_ns;
4446 uint16_t lfps_t1_t2_override_us;
4447 short lfps_t1_t2_offset_us;
4448 uint8_t lttpr_count;
4449 /*
4450 * Padding to align structure to 4 byte boundary.
4451 */
4452 uint8_t pad[1];
4453 };
4454
4455 /**
4456 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
4457 */
4458 struct dmub_cmd_replay_copy_settings_data {
4459 /**
4460 * Flags that can be set by driver to change some replay behaviour.
4461 */
4462 union replay_debug_flags debug;
4463
4464 /**
4465 * @flags: Flags used to determine feature functionality.
4466 */
4467 union replay_hw_flags flags;
4468
4469 /**
4470 * DPP HW instance.
4471 */
4472 uint8_t dpp_inst;
4473 /**
4474 * OTG HW instance.
4475 */
4476 uint8_t otg_inst;
4477 /**
4478 * DIG FE HW instance.
4479 */
4480 uint8_t digfe_inst;
4481 /**
4482 * DIG BE HW instance.
4483 */
4484 uint8_t digbe_inst;
4485 /**
4486 * AUX HW instance.
4487 */
4488 uint8_t aux_inst;
4489 /**
4490 * Panel Instance.
4491 * Panel isntance to identify which psr_state to use
4492 * Currently the support is only for 0 or 1
4493 */
4494 uint8_t panel_inst;
4495 /**
4496 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare
4497 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode
4498 */
4499 uint8_t pixel_deviation_per_line;
4500 /**
4501 * @max_deviation_line: The max number of deviation line that can keep the timing
4502 * synchronized between the Source and Sink during Replay normal sleep mode.
4503 */
4504 uint8_t max_deviation_line;
4505 /**
4506 * Length of each horizontal line in ns.
4507 */
4508 uint32_t line_time_in_ns;
4509 /**
4510 * PHY instance.
4511 */
4512 uint8_t dpphy_inst;
4513 /**
4514 * Determines if SMU optimzations are enabled/disabled.
4515 */
4516 uint8_t smu_optimizations_en;
4517 /**
4518 * Determines if timing sync are enabled/disabled.
4519 */
4520 uint8_t replay_timing_sync_supported;
4521 /*
4522 * Use FSM state for Replay power up/down
4523 */
4524 uint8_t use_phy_fsm;
4525 /**
4526 * Use for AUX-less ALPM LFPS wake operation
4527 */
4528 struct dmub_alpm_auxless_data auxless_alpm_data;
4529 /**
4530 * @hpo_stream_enc_inst: HPO stream encoder instance
4531 */
4532 uint8_t hpo_stream_enc_inst;
4533 /**
4534 * @hpo_link_enc_inst: HPO link encoder instance
4535 */
4536 uint8_t hpo_link_enc_inst;
4537 /**
4538 * Determines if fast resync in ultra sleep mode is enabled/disabled.
4539 */
4540 uint8_t replay_support_fast_resync_in_ultra_sleep_mode;
4541 /**
4542 * @pad: Align structure to 4 byte boundary.
4543 */
4544 uint8_t pad[1];
4545 };
4546
4547
4548 /**
4549 * Replay versions.
4550 */
4551 enum replay_version {
4552 /**
4553 * FreeSync Replay
4554 */
4555 REPLAY_VERSION_FREESYNC_REPLAY = 0,
4556 /**
4557 * Panel Replay
4558 */
4559 REPLAY_VERSION_PANEL_REPLAY = 1,
4560 /**
4561 * Replay not supported.
4562 */
4563 REPLAY_VERSION_UNSUPPORTED = 0xFF,
4564 };
4565
4566 /**
4567 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
4568 */
4569 struct dmub_rb_cmd_replay_copy_settings {
4570 /**
4571 * Command header.
4572 */
4573 struct dmub_cmd_header header;
4574 /**
4575 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
4576 */
4577 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data;
4578 };
4579
4580 /**
4581 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable
4582 */
4583 enum replay_enable {
4584 /**
4585 * Disable REPLAY.
4586 */
4587 REPLAY_DISABLE = 0,
4588 /**
4589 * Enable REPLAY.
4590 */
4591 REPLAY_ENABLE = 1,
4592 };
4593
4594 /**
4595 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_ENABLE command.
4596 */
4597 struct dmub_rb_cmd_smart_power_oled_enable_data {
4598 /**
4599 * SMART_POWER_OLED enable or disable.
4600 */
4601 uint8_t enable;
4602 /**
4603 * Panel Instance.
4604 * Panel isntance to identify which replay_state to use
4605 * Currently the support is only for 0 or 1
4606 */
4607 uint8_t panel_inst;
4608
4609 uint16_t peak_nits;
4610 /**
4611 * OTG HW instance.
4612 */
4613 uint8_t otg_inst;
4614 /**
4615 * DIG FE HW instance.
4616 */
4617 uint8_t digfe_inst;
4618 /**
4619 * DIG BE HW instance.
4620 */
4621 uint8_t digbe_inst;
4622 uint8_t debugcontrol;
4623 /*
4624 * vertical interrupt trigger line
4625 */
4626 uint32_t triggerline;
4627
4628 uint16_t fixed_max_cll;
4629
4630 uint8_t pad[2];
4631 };
4632
4633 /**
4634 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command.
4635 */
4636 struct dmub_rb_cmd_replay_enable_data {
4637 /**
4638 * Replay enable or disable.
4639 */
4640 uint8_t enable;
4641 /**
4642 * Panel Instance.
4643 * Panel isntance to identify which replay_state to use
4644 * Currently the support is only for 0 or 1
4645 */
4646 uint8_t panel_inst;
4647 /**
4648 * Phy state to enter.
4649 * Values to use are defined in dmub_phy_fsm_state
4650 */
4651 uint8_t phy_fsm_state;
4652 /**
4653 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
4654 * Set this using enum phy_link_rate.
4655 * This does not support HDMI/DP2 for now.
4656 */
4657 uint8_t phy_rate;
4658 };
4659
4660 /**
4661 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
4662 * Replay enable/disable is controlled using action in data.
4663 */
4664 struct dmub_rb_cmd_replay_enable {
4665 /**
4666 * Command header.
4667 */
4668 struct dmub_cmd_header header;
4669
4670 struct dmub_rb_cmd_replay_enable_data data;
4671 };
4672
4673 /**
4674 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4675 */
4676 struct dmub_cmd_replay_set_power_opt_data {
4677 /**
4678 * Panel Instance.
4679 * Panel isntance to identify which replay_state to use
4680 * Currently the support is only for 0 or 1
4681 */
4682 uint8_t panel_inst;
4683 /**
4684 * Explicit padding to 4 byte boundary.
4685 */
4686 uint8_t pad[3];
4687 /**
4688 * REPLAY power option
4689 */
4690 uint32_t power_opt;
4691 };
4692
4693 /**
4694 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
4695 */
4696 struct dmub_cmd_replay_set_timing_sync_data {
4697 /**
4698 * Panel Instance.
4699 * Panel isntance to identify which replay_state to use
4700 * Currently the support is only for 0 or 1
4701 */
4702 uint8_t panel_inst;
4703 /**
4704 * REPLAY set_timing_sync
4705 */
4706 uint8_t timing_sync_supported;
4707 /**
4708 * Explicit padding to 4 byte boundary.
4709 */
4710 uint8_t pad[2];
4711 };
4712
4713 /**
4714 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
4715 */
4716 struct dmub_cmd_replay_set_pseudo_vtotal {
4717 /**
4718 * Panel Instance.
4719 * Panel isntance to identify which replay_state to use
4720 * Currently the support is only for 0 or 1
4721 */
4722 uint8_t panel_inst;
4723 /**
4724 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal
4725 */
4726 uint16_t vtotal;
4727 /**
4728 * Explicit padding to 4 byte boundary.
4729 */
4730 uint8_t pad;
4731 };
4732 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data {
4733 /**
4734 * Panel Instance.
4735 * Panel isntance to identify which replay_state to use
4736 * Currently the support is only for 0 or 1
4737 */
4738 uint8_t panel_inst;
4739 /**
4740 * enabled: set adaptive sync sdp enabled
4741 */
4742 uint8_t force_disabled;
4743
4744 uint8_t pad[2];
4745 };
4746 struct dmub_cmd_replay_set_general_cmd_data {
4747 /**
4748 * Panel Instance.
4749 * Panel isntance to identify which replay_state to use
4750 * Currently the support is only for 0 or 1
4751 */
4752 uint8_t panel_inst;
4753 /**
4754 * subtype: replay general cmd sub type
4755 */
4756 uint8_t subtype;
4757
4758 uint8_t pad[2];
4759 /**
4760 * config data with param1 and param2
4761 */
4762 uint32_t param1;
4763
4764 uint32_t param2;
4765 };
4766
4767 /**
4768 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4769 */
4770 struct dmub_rb_cmd_replay_set_power_opt {
4771 /**
4772 * Command header.
4773 */
4774 struct dmub_cmd_header header;
4775 /**
4776 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4777 */
4778 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
4779 };
4780
4781 /**
4782 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4783 */
4784 struct dmub_cmd_replay_set_coasting_vtotal_data {
4785 /**
4786 * 16-bit value dicated by driver that indicates the coasting vtotal.
4787 */
4788 uint16_t coasting_vtotal;
4789 /**
4790 * REPLAY control version.
4791 */
4792 uint8_t cmd_version;
4793 /**
4794 * Panel Instance.
4795 * Panel isntance to identify which replay_state to use
4796 * Currently the support is only for 0 or 1
4797 */
4798 uint8_t panel_inst;
4799 /**
4800 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part.
4801 */
4802 uint16_t coasting_vtotal_high;
4803 /**
4804 * frame skip number.
4805 */
4806 uint16_t frame_skip_number;
4807 };
4808
4809 /**
4810 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4811 */
4812 struct dmub_rb_cmd_replay_set_coasting_vtotal {
4813 /**
4814 * Command header.
4815 */
4816 struct dmub_cmd_header header;
4817 /**
4818 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4819 */
4820 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
4821 };
4822
4823 /**
4824 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.
4825 */
4826 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal {
4827 /**
4828 * Command header.
4829 */
4830 struct dmub_cmd_header header;
4831 /**
4832 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4833 */
4834 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
4835 /**
4836 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4837 */
4838 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
4839 };
4840
4841 /**
4842 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
4843 */
4844 struct dmub_rb_cmd_replay_set_timing_sync {
4845 /**
4846 * Command header.
4847 */
4848 struct dmub_cmd_header header;
4849 /**
4850 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
4851 */
4852 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data;
4853 };
4854
4855 /**
4856 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
4857 */
4858 struct dmub_rb_cmd_replay_set_pseudo_vtotal {
4859 /**
4860 * Command header.
4861 */
4862 struct dmub_cmd_header header;
4863 /**
4864 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
4865 */
4866 struct dmub_cmd_replay_set_pseudo_vtotal data;
4867 };
4868
4869 /**
4870 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
4871 */
4872 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp {
4873 /**
4874 * Command header.
4875 */
4876 struct dmub_cmd_header header;
4877 /**
4878 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
4879 */
4880 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data;
4881 };
4882
4883 /**
4884 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
4885 */
4886 struct dmub_rb_cmd_replay_set_general_cmd {
4887 /**
4888 * Command header.
4889 */
4890 struct dmub_cmd_header header;
4891 /**
4892 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
4893 */
4894 struct dmub_cmd_replay_set_general_cmd_data data;
4895 };
4896
4897 /**
4898 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
4899 */
4900 struct dmub_cmd_replay_frameupdate_timer_data {
4901 /**
4902 * Panel Instance.
4903 * Panel isntance to identify which replay_state to use
4904 * Currently the support is only for 0 or 1
4905 */
4906 uint8_t panel_inst;
4907 /**
4908 * Replay Frameupdate Timer Enable or not
4909 */
4910 uint8_t enable;
4911 /**
4912 * REPLAY force reflash frame update number
4913 */
4914 uint16_t frameupdate_count;
4915 };
4916 /**
4917 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER
4918 */
4919 struct dmub_rb_cmd_replay_set_frameupdate_timer {
4920 /**
4921 * Command header.
4922 */
4923 struct dmub_cmd_header header;
4924 /**
4925 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4926 */
4927 struct dmub_cmd_replay_frameupdate_timer_data data;
4928 };
4929
4930 /**
4931 * Definition union of replay command set
4932 */
4933 union dmub_replay_cmd_set {
4934 /**
4935 * Panel Instance.
4936 * Panel isntance to identify which replay_state to use
4937 * Currently the support is only for 0 or 1
4938 */
4939 uint8_t panel_inst;
4940 /**
4941 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data.
4942 */
4943 struct dmub_cmd_replay_set_timing_sync_data sync_data;
4944 /**
4945 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data.
4946 */
4947 struct dmub_cmd_replay_frameupdate_timer_data timer_data;
4948 /**
4949 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data.
4950 */
4951 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data;
4952 /**
4953 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data.
4954 */
4955 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data;
4956 /**
4957 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data.
4958 */
4959 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data;
4960 };
4961
4962 /**
4963 * SMART POWER OLED command sub-types.
4964 */
4965 enum dmub_cmd_smart_power_oled_type {
4966
4967 /**
4968 * Enable/Disable SMART_POWER_OLED.
4969 */
4970 DMUB_CMD__SMART_POWER_OLED_ENABLE = 1,
4971 /**
4972 * Get current MaxCLL value if SMART POWER OLED is enabled.
4973 */
4974 DMUB_CMD__SMART_POWER_OLED_GETMAXCLL = 2,
4975 };
4976
4977 /**
4978 * Definition of a DMUB_CMD__SMART_POWER_OLED command.
4979 */
4980 struct dmub_rb_cmd_smart_power_oled_enable {
4981 /**
4982 * Command header.
4983 */
4984 struct dmub_cmd_header header;
4985
4986 struct dmub_rb_cmd_smart_power_oled_enable_data data;
4987 };
4988
4989 struct dmub_cmd_smart_power_oled_getmaxcll_input {
4990 uint8_t panel_inst;
4991 uint8_t pad[3];
4992 };
4993
4994 struct dmub_cmd_smart_power_oled_getmaxcll_output {
4995 uint16_t current_max_cll;
4996 uint8_t pad[2];
4997 };
4998
4999 /**
5000 * Definition of a DMUB_CMD__SMART_POWER_OLED command.
5001 */
5002 struct dmub_rb_cmd_smart_power_oled_getmaxcll {
5003 struct dmub_cmd_header header; /**< Command header */
5004 /**
5005 * Data passed from driver to FW in a DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command.
5006 */
5007 union dmub_cmd_smart_power_oled_getmaxcll_data {
5008 struct dmub_cmd_smart_power_oled_getmaxcll_input input; /**< Input */
5009 struct dmub_cmd_smart_power_oled_getmaxcll_output output; /**< Output */
5010 uint32_t output_raw; /**< Raw data output */
5011 } data;
5012 };
5013
5014 /**
5015 * Set of HW components that can be locked.
5016 *
5017 * Note: If updating with more HW components, fields
5018 * in dmub_inbox0_cmd_lock_hw must be updated to match.
5019 */
5020 union dmub_hw_lock_flags {
5021 /**
5022 * Set of HW components that can be locked.
5023 */
5024 struct {
5025 /**
5026 * Lock/unlock OTG master update lock.
5027 */
5028 uint8_t lock_pipe : 1;
5029 /**
5030 * Lock/unlock cursor.
5031 */
5032 uint8_t lock_cursor : 1;
5033 /**
5034 * Lock/unlock global update lock.
5035 */
5036 uint8_t lock_dig : 1;
5037 /**
5038 * Triple buffer lock requires additional hw programming to usual OTG master lock.
5039 */
5040 uint8_t triple_buffer_lock : 1;
5041 } bits;
5042
5043 /**
5044 * Union for HW Lock flags.
5045 */
5046 uint8_t u8All;
5047 };
5048
5049 /**
5050 * Instances of HW to be locked.
5051 *
5052 * Note: If updating with more HW components, fields
5053 * in dmub_inbox0_cmd_lock_hw must be updated to match.
5054 */
5055 struct dmub_hw_lock_inst_flags {
5056 /**
5057 * OTG HW instance for OTG master update lock.
5058 */
5059 uint8_t otg_inst;
5060 /**
5061 * OPP instance for cursor lock.
5062 */
5063 uint8_t opp_inst;
5064 /**
5065 * OTG HW instance for global update lock.
5066 * TODO: Remove, and re-use otg_inst.
5067 */
5068 uint8_t dig_inst;
5069 /**
5070 * Explicit pad to 4 byte boundary.
5071 */
5072 uint8_t pad;
5073 };
5074
5075 /**
5076 * Clients that can acquire the HW Lock Manager.
5077 *
5078 * Note: If updating with more clients, fields in
5079 * dmub_inbox0_cmd_lock_hw must be updated to match.
5080 */
5081 enum hw_lock_client {
5082 /**
5083 * Driver is the client of HW Lock Manager.
5084 */
5085 HW_LOCK_CLIENT_DRIVER = 0,
5086 /**
5087 * PSR SU is the client of HW Lock Manager.
5088 */
5089 HW_LOCK_CLIENT_PSR_SU = 1,
5090 HW_LOCK_CLIENT_SUBVP = 3,
5091 /**
5092 * Replay is the client of HW Lock Manager.
5093 */
5094 HW_LOCK_CLIENT_REPLAY = 4,
5095 HW_LOCK_CLIENT_FAMS2 = 5,
5096 HW_LOCK_CLIENT_CURSOR_OFFLOAD = 6,
5097 /**
5098 * Invalid client.
5099 */
5100 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
5101 };
5102
5103 /**
5104 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
5105 */
5106 struct dmub_cmd_lock_hw_data {
5107 /**
5108 * Specifies the client accessing HW Lock Manager.
5109 */
5110 enum hw_lock_client client;
5111 /**
5112 * HW instances to be locked.
5113 */
5114 struct dmub_hw_lock_inst_flags inst_flags;
5115 /**
5116 * Which components to be locked.
5117 */
5118 union dmub_hw_lock_flags hw_locks;
5119 /**
5120 * Specifies lock/unlock.
5121 */
5122 uint8_t lock;
5123 /**
5124 * HW can be unlocked separately from releasing the HW Lock Mgr.
5125 * This flag is set if the client wishes to release the object.
5126 */
5127 uint8_t should_release;
5128 /**
5129 * Explicit padding to 4 byte boundary.
5130 */
5131 uint8_t pad;
5132 };
5133
5134 /**
5135 * Definition of a DMUB_CMD__HW_LOCK command.
5136 * Command is used by driver and FW.
5137 */
5138 struct dmub_rb_cmd_lock_hw {
5139 /**
5140 * Command header.
5141 */
5142 struct dmub_cmd_header header;
5143 /**
5144 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
5145 */
5146 struct dmub_cmd_lock_hw_data lock_hw_data;
5147 };
5148
5149 /**
5150 * ABM command sub-types.
5151 */
5152 enum dmub_cmd_abm_type {
5153 /**
5154 * Initialize parameters for ABM algorithm.
5155 * Data is passed through an indirect buffer.
5156 */
5157 DMUB_CMD__ABM_INIT_CONFIG = 0,
5158 /**
5159 * Set OTG and panel HW instance.
5160 */
5161 DMUB_CMD__ABM_SET_PIPE = 1,
5162 /**
5163 * Set user requested backklight level.
5164 */
5165 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
5166 /**
5167 * Set ABM operating/aggression level.
5168 */
5169 DMUB_CMD__ABM_SET_LEVEL = 3,
5170 /**
5171 * Set ambient light level.
5172 */
5173 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
5174 /**
5175 * Enable/disable fractional duty cycle for backlight PWM.
5176 */
5177 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
5178
5179 /**
5180 * unregister vertical interrupt after steady state is reached
5181 */
5182 DMUB_CMD__ABM_PAUSE = 6,
5183
5184 /**
5185 * Save and Restore ABM state. On save we save parameters, and
5186 * on restore we update state with passed in data.
5187 */
5188 DMUB_CMD__ABM_SAVE_RESTORE = 7,
5189
5190 /**
5191 * Query ABM caps.
5192 */
5193 DMUB_CMD__ABM_QUERY_CAPS = 8,
5194
5195 /**
5196 * Set ABM Events
5197 */
5198 DMUB_CMD__ABM_SET_EVENT = 9,
5199
5200 /**
5201 * Get the current ACE curve.
5202 */
5203 DMUB_CMD__ABM_GET_ACE_CURVE = 10,
5204
5205 /**
5206 * Get current histogram data
5207 */
5208 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11,
5209 };
5210
5211 /**
5212 * LSDMA command sub-types.
5213 */
5214 enum dmub_cmd_lsdma_type {
5215 /**
5216 * Initialize parameters for LSDMA.
5217 * Ring buffer is mapped to the ring buffer
5218 */
5219 DMUB_CMD__LSDMA_INIT_CONFIG = 0,
5220 /**
5221 * LSDMA copies data from source to destination linearly
5222 */
5223 DMUB_CMD__LSDMA_LINEAR_COPY = 1,
5224 /**
5225 * LSDMA copies data from source to destination linearly in sub window
5226 */
5227 DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2,
5228 /**
5229 * Send the tiled-to-tiled copy command
5230 */
5231 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 3,
5232 /**
5233 * Send the poll reg write command
5234 */
5235 DMUB_CMD__LSDMA_POLL_REG_WRITE = 4,
5236 /**
5237 * Send the pio copy command
5238 */
5239 DMUB_CMD__LSDMA_PIO_COPY = 5,
5240 /**
5241 * Send the pio constfill command
5242 */
5243 DMUB_CMD__LSDMA_PIO_CONSTFILL = 6,
5244 };
5245
5246 struct abm_ace_curve {
5247 /**
5248 * @offsets: ACE curve offsets.
5249 */
5250 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS];
5251
5252 /**
5253 * @thresholds: ACE curve thresholds.
5254 */
5255 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS];
5256
5257 /**
5258 * @slopes: ACE curve slopes.
5259 */
5260 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS];
5261 };
5262
5263 struct fixed_pt_format {
5264 /**
5265 * @sign_bit: Indicates whether one bit is reserved for the sign.
5266 */
5267 bool sign_bit;
5268
5269 /**
5270 * @num_int_bits: Number of bits used for integer part.
5271 */
5272 uint8_t num_int_bits;
5273
5274 /**
5275 * @num_frac_bits: Number of bits used for fractional part.
5276 */
5277 uint8_t num_frac_bits;
5278
5279 /**
5280 * @pad: Explicit padding to 4 byte boundary.
5281 */
5282 uint8_t pad;
5283 };
5284
5285 struct abm_caps {
5286 /**
5287 * @num_hg_bins: Number of histogram bins.
5288 */
5289 uint8_t num_hg_bins;
5290
5291 /**
5292 * @num_ace_segments: Number of ACE curve segments.
5293 */
5294 uint8_t num_ace_segments;
5295
5296 /**
5297 * @pad: Explicit padding to 4 byte boundary.
5298 */
5299 uint8_t pad[2];
5300
5301 /**
5302 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0.
5303 */
5304 struct fixed_pt_format ace_thresholds_format;
5305
5306 /**
5307 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0.
5308 */
5309 struct fixed_pt_format ace_offsets_format;
5310
5311 /**
5312 * @ace_slopes_format: Format of the ACE slopes.
5313 */
5314 struct fixed_pt_format ace_slopes_format;
5315 };
5316
5317 /**
5318 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
5319 * Requirements:
5320 * - Padded explicitly to 32-bit boundary.
5321 * - Must ensure this structure matches the one on driver-side,
5322 * otherwise it won't be aligned.
5323 */
5324 struct abm_config_table {
5325 /**
5326 * Gamma curve thresholds, used for crgb conversion.
5327 */
5328 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
5329 /**
5330 * Gamma curve offsets, used for crgb conversion.
5331 */
5332 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
5333 /**
5334 * Gamma curve slopes, used for crgb conversion.
5335 */
5336 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
5337 /**
5338 * Custom backlight curve thresholds.
5339 */
5340 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
5341 /**
5342 * Custom backlight curve offsets.
5343 */
5344 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
5345 /**
5346 * Ambient light thresholds.
5347 */
5348 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
5349 /**
5350 * Minimum programmable backlight.
5351 */
5352 uint16_t min_abm_backlight; // 122B
5353 /**
5354 * Minimum reduction values.
5355 */
5356 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
5357 /**
5358 * Maximum reduction values.
5359 */
5360 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
5361 /**
5362 * Bright positive gain.
5363 */
5364 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
5365 /**
5366 * Dark negative gain.
5367 */
5368 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
5369 /**
5370 * Hybrid factor.
5371 */
5372 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
5373 /**
5374 * Contrast factor.
5375 */
5376 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
5377 /**
5378 * Deviation gain.
5379 */
5380 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
5381 /**
5382 * Minimum knee.
5383 */
5384 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
5385 /**
5386 * Maximum knee.
5387 */
5388 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
5389 /**
5390 * Unused.
5391 */
5392 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
5393 /**
5394 * Explicit padding to 4 byte boundary.
5395 */
5396 uint8_t pad3[3]; // 229B
5397 /**
5398 * Backlight ramp reduction.
5399 */
5400 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
5401 /**
5402 * Backlight ramp start.
5403 */
5404 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
5405 };
5406
5407 /**
5408 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
5409 */
5410 struct dmub_cmd_abm_set_pipe_data {
5411 /**
5412 * OTG HW instance.
5413 */
5414 uint8_t otg_inst;
5415
5416 /**
5417 * Panel Control HW instance.
5418 */
5419 uint8_t panel_inst;
5420
5421 /**
5422 * Controls how ABM will interpret a set pipe or set level command.
5423 */
5424 uint8_t set_pipe_option;
5425
5426 /**
5427 * Unused.
5428 * TODO: Remove.
5429 */
5430 uint8_t ramping_boundary;
5431
5432 /**
5433 * PwrSeq HW Instance.
5434 */
5435 uint8_t pwrseq_inst;
5436
5437 /**
5438 * Explicit padding to 4 byte boundary.
5439 */
5440 uint8_t pad[3];
5441 };
5442
5443 /**
5444 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
5445 */
5446 struct dmub_rb_cmd_abm_set_pipe {
5447 /**
5448 * Command header.
5449 */
5450 struct dmub_cmd_header header;
5451
5452 /**
5453 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
5454 */
5455 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
5456 };
5457
5458 /**
5459 * Type of backlight control method to be used by ABM module
5460 */
5461 enum dmub_backlight_control_type {
5462 /**
5463 * PWM Backlight control
5464 */
5465 DMU_BACKLIGHT_CONTROL_PWM = 0,
5466 /**
5467 * VESA Aux-based backlight control
5468 */
5469 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1,
5470 /**
5471 * AMD DPCD Aux-based backlight control
5472 */
5473 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2,
5474 };
5475
5476 /**
5477 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
5478 */
5479 struct dmub_cmd_abm_set_backlight_data {
5480 /**
5481 * Number of frames to ramp to backlight user level.
5482 */
5483 uint32_t frame_ramp;
5484
5485 /**
5486 * Requested backlight level from user.
5487 */
5488 uint32_t backlight_user_level;
5489
5490 /**
5491 * ABM control version.
5492 */
5493 uint8_t version;
5494
5495 /**
5496 * Panel Control HW instance mask.
5497 * Bit 0 is Panel Control HW instance 0.
5498 * Bit 1 is Panel Control HW instance 1.
5499 */
5500 uint8_t panel_mask;
5501
5502 /**
5503 * AUX HW Instance.
5504 */
5505 uint8_t aux_inst;
5506
5507 /**
5508 * Explicit padding to 4 byte boundary.
5509 */
5510 uint8_t pad[1];
5511
5512 /**
5513 * Backlight control type.
5514 * Value 0 is PWM backlight control.
5515 * Value 1 is VAUX backlight control.
5516 * Value 2 is AMD DPCD AUX backlight control.
5517 */
5518 enum dmub_backlight_control_type backlight_control_type;
5519
5520 /**
5521 * Minimum luminance in nits.
5522 */
5523 uint32_t min_luminance;
5524
5525 /**
5526 * Maximum luminance in nits.
5527 */
5528 uint32_t max_luminance;
5529
5530 /**
5531 * Minimum backlight in pwm.
5532 */
5533 uint32_t min_backlight_pwm;
5534
5535 /**
5536 * Maximum backlight in pwm.
5537 */
5538 uint32_t max_backlight_pwm;
5539 };
5540
5541 /**
5542 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
5543 */
5544 struct dmub_rb_cmd_abm_set_backlight {
5545 /**
5546 * Command header.
5547 */
5548 struct dmub_cmd_header header;
5549
5550 /**
5551 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
5552 */
5553 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
5554 };
5555
5556 /**
5557 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
5558 */
5559 struct dmub_cmd_abm_set_level_data {
5560 /**
5561 * Set current ABM operating/aggression level.
5562 */
5563 uint32_t level;
5564
5565 /**
5566 * ABM control version.
5567 */
5568 uint8_t version;
5569
5570 /**
5571 * Panel Control HW instance mask.
5572 * Bit 0 is Panel Control HW instance 0.
5573 * Bit 1 is Panel Control HW instance 1.
5574 */
5575 uint8_t panel_mask;
5576
5577 /**
5578 * Explicit padding to 4 byte boundary.
5579 */
5580 uint8_t pad[2];
5581 };
5582
5583 /**
5584 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
5585 */
5586 struct dmub_rb_cmd_abm_set_level {
5587 /**
5588 * Command header.
5589 */
5590 struct dmub_cmd_header header;
5591
5592 /**
5593 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
5594 */
5595 struct dmub_cmd_abm_set_level_data abm_set_level_data;
5596 };
5597
5598 /**
5599 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
5600 */
5601 struct dmub_cmd_abm_set_ambient_level_data {
5602 /**
5603 * Ambient light sensor reading from OS.
5604 */
5605 uint32_t ambient_lux;
5606
5607 /**
5608 * ABM control version.
5609 */
5610 uint8_t version;
5611
5612 /**
5613 * Panel Control HW instance mask.
5614 * Bit 0 is Panel Control HW instance 0.
5615 * Bit 1 is Panel Control HW instance 1.
5616 */
5617 uint8_t panel_mask;
5618
5619 /**
5620 * Explicit padding to 4 byte boundary.
5621 */
5622 uint8_t pad[2];
5623 };
5624
5625 /**
5626 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
5627 */
5628 struct dmub_rb_cmd_abm_set_ambient_level {
5629 /**
5630 * Command header.
5631 */
5632 struct dmub_cmd_header header;
5633
5634 /**
5635 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
5636 */
5637 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
5638 };
5639
5640 /**
5641 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
5642 */
5643 struct dmub_cmd_abm_set_pwm_frac_data {
5644 /**
5645 * Enable/disable fractional duty cycle for backlight PWM.
5646 * TODO: Convert to uint8_t.
5647 */
5648 uint32_t fractional_pwm;
5649
5650 /**
5651 * ABM control version.
5652 */
5653 uint8_t version;
5654
5655 /**
5656 * Panel Control HW instance mask.
5657 * Bit 0 is Panel Control HW instance 0.
5658 * Bit 1 is Panel Control HW instance 1.
5659 */
5660 uint8_t panel_mask;
5661
5662 /**
5663 * Explicit padding to 4 byte boundary.
5664 */
5665 uint8_t pad[2];
5666 };
5667
5668 /**
5669 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
5670 */
5671 struct dmub_rb_cmd_abm_set_pwm_frac {
5672 /**
5673 * Command header.
5674 */
5675 struct dmub_cmd_header header;
5676
5677 /**
5678 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
5679 */
5680 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
5681 };
5682
5683 /**
5684 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
5685 */
5686 struct dmub_cmd_abm_init_config_data {
5687 /**
5688 * Location of indirect buffer used to pass init data to ABM.
5689 */
5690 union dmub_addr src;
5691
5692 /**
5693 * Indirect buffer length.
5694 */
5695 uint16_t bytes;
5696
5697
5698 /**
5699 * ABM control version.
5700 */
5701 uint8_t version;
5702
5703 /**
5704 * Panel Control HW instance mask.
5705 * Bit 0 is Panel Control HW instance 0.
5706 * Bit 1 is Panel Control HW instance 1.
5707 */
5708 uint8_t panel_mask;
5709
5710 /**
5711 * Explicit padding to 4 byte boundary.
5712 */
5713 uint8_t pad[2];
5714 };
5715
5716 /**
5717 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
5718 */
5719 struct dmub_rb_cmd_abm_init_config {
5720 /**
5721 * Command header.
5722 */
5723 struct dmub_cmd_header header;
5724
5725 /**
5726 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
5727 */
5728 struct dmub_cmd_abm_init_config_data abm_init_config_data;
5729 };
5730
5731 /**
5732 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
5733 */
5734
5735 struct dmub_cmd_abm_pause_data {
5736
5737 /**
5738 * Panel Control HW instance mask.
5739 * Bit 0 is Panel Control HW instance 0.
5740 * Bit 1 is Panel Control HW instance 1.
5741 */
5742 uint8_t panel_mask;
5743
5744 /**
5745 * OTG hw instance
5746 */
5747 uint8_t otg_inst;
5748
5749 /**
5750 * Enable or disable ABM pause
5751 */
5752 uint8_t enable;
5753
5754 /**
5755 * Explicit padding to 4 byte boundary.
5756 */
5757 uint8_t pad[1];
5758 };
5759
5760 /**
5761 * Definition of a DMUB_CMD__ABM_PAUSE command.
5762 */
5763 struct dmub_rb_cmd_abm_pause {
5764 /**
5765 * Command header.
5766 */
5767 struct dmub_cmd_header header;
5768
5769 /**
5770 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
5771 */
5772 struct dmub_cmd_abm_pause_data abm_pause_data;
5773 };
5774
5775 /**
5776 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command.
5777 */
5778 struct dmub_cmd_abm_query_caps_in {
5779 /**
5780 * Panel instance.
5781 */
5782 uint8_t panel_inst;
5783
5784 /**
5785 * Explicit padding to 4 byte boundary.
5786 */
5787 uint8_t pad[3];
5788 };
5789
5790 /**
5791 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command.
5792 */
5793 struct dmub_cmd_abm_query_caps_out {
5794 /**
5795 * SW Algorithm caps.
5796 */
5797 struct abm_caps sw_caps;
5798
5799 /**
5800 * ABM HW caps.
5801 */
5802 struct abm_caps hw_caps;
5803 };
5804
5805 /**
5806 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.
5807 */
5808 struct dmub_rb_cmd_abm_query_caps {
5809 /**
5810 * Command header.
5811 */
5812 struct dmub_cmd_header header;
5813
5814 /**
5815 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command.
5816 */
5817 union {
5818 struct dmub_cmd_abm_query_caps_in abm_query_caps_in;
5819 struct dmub_cmd_abm_query_caps_out abm_query_caps_out;
5820 } data;
5821 };
5822
5823 /**
5824 * enum dmub_abm_ace_curve_type - ACE curve type.
5825 */
5826 enum dmub_abm_ace_curve_type {
5827 /**
5828 * ACE curve as defined by the SW layer.
5829 */
5830 ABM_ACE_CURVE_TYPE__SW = 0,
5831 /**
5832 * ACE curve as defined by the SW to HW translation interface layer.
5833 */
5834 ABM_ACE_CURVE_TYPE__SW_IF = 1,
5835 };
5836
5837 /**
5838 * enum dmub_abm_histogram_type - Histogram type.
5839 */
5840 enum dmub_abm_histogram_type {
5841 /**
5842 * ACE curve as defined by the SW layer.
5843 */
5844 ABM_HISTOGRAM_TYPE__SW = 0,
5845 /**
5846 * ACE curve as defined by the SW to HW translation interface layer.
5847 */
5848 ABM_HISTOGRAM_TYPE__SW_IF = 1,
5849 };
5850
5851 /**
5852 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.
5853 */
5854 struct dmub_rb_cmd_abm_get_ace_curve {
5855 /**
5856 * Command header.
5857 */
5858 struct dmub_cmd_header header;
5859
5860 /**
5861 * Address where ACE curve should be copied.
5862 */
5863 union dmub_addr dest;
5864
5865 /**
5866 * Type of ACE curve being queried.
5867 */
5868 enum dmub_abm_ace_curve_type ace_type;
5869
5870 /**
5871 * Indirect buffer length.
5872 */
5873 uint16_t bytes;
5874
5875 /**
5876 * eDP panel instance.
5877 */
5878 uint8_t panel_inst;
5879
5880 /**
5881 * Explicit padding to 4 byte boundary.
5882 */
5883 uint8_t pad;
5884 };
5885
5886 /**
5887 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command.
5888 */
5889 struct dmub_rb_cmd_abm_get_histogram {
5890 /**
5891 * Command header.
5892 */
5893 struct dmub_cmd_header header;
5894
5895 /**
5896 * Address where Histogram should be copied.
5897 */
5898 union dmub_addr dest;
5899
5900 /**
5901 * Type of Histogram being queried.
5902 */
5903 enum dmub_abm_histogram_type histogram_type;
5904
5905 /**
5906 * Indirect buffer length.
5907 */
5908 uint16_t bytes;
5909
5910 /**
5911 * eDP panel instance.
5912 */
5913 uint8_t panel_inst;
5914
5915 /**
5916 * Explicit padding to 4 byte boundary.
5917 */
5918 uint8_t pad;
5919 };
5920
5921 /**
5922 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
5923 */
5924 struct dmub_rb_cmd_abm_save_restore {
5925 /**
5926 * Command header.
5927 */
5928 struct dmub_cmd_header header;
5929
5930 /**
5931 * OTG hw instance
5932 */
5933 uint8_t otg_inst;
5934
5935 /**
5936 * Enable or disable ABM pause
5937 */
5938 uint8_t freeze;
5939
5940 /**
5941 * Explicit padding to 4 byte boundary.
5942 */
5943 uint8_t debug;
5944
5945 /**
5946 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
5947 */
5948 struct dmub_cmd_abm_init_config_data abm_init_config_data;
5949 };
5950
5951 /**
5952 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.
5953 */
5954
5955 struct dmub_cmd_abm_set_event_data {
5956
5957 /**
5958 * VB Scaling Init. Strength Mapping
5959 * Byte 0: 0~255 for VB level 0
5960 * Byte 1: 0~255 for VB level 1
5961 * Byte 2: 0~255 for VB level 2
5962 * Byte 3: 0~255 for VB level 3
5963 */
5964 uint32_t vb_scaling_strength_mapping;
5965 /**
5966 * VariBright Scaling Enable
5967 */
5968 uint8_t vb_scaling_enable;
5969 /**
5970 * Panel Control HW instance mask.
5971 * Bit 0 is Panel Control HW instance 0.
5972 * Bit 1 is Panel Control HW instance 1.
5973 */
5974 uint8_t panel_mask;
5975
5976 /**
5977 * Explicit padding to 4 byte boundary.
5978 */
5979 uint8_t pad[2];
5980 };
5981
5982 /**
5983 * Definition of a DMUB_CMD__ABM_SET_EVENT command.
5984 */
5985 struct dmub_rb_cmd_abm_set_event {
5986 /**
5987 * Command header.
5988 */
5989 struct dmub_cmd_header header;
5990
5991 /**
5992 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.
5993 */
5994 struct dmub_cmd_abm_set_event_data abm_set_event_data;
5995 };
5996
5997 /**
5998 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
5999 */
6000 struct dmub_cmd_query_feature_caps_data {
6001 /**
6002 * DMUB feature capabilities.
6003 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
6004 */
6005 struct dmub_feature_caps feature_caps;
6006 };
6007
6008 /**
6009 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
6010 */
6011 struct dmub_rb_cmd_query_feature_caps {
6012 /**
6013 * Command header.
6014 */
6015 struct dmub_cmd_header header;
6016 /**
6017 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
6018 */
6019 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
6020 };
6021
6022 /**
6023 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
6024 */
6025 struct dmub_cmd_visual_confirm_color_data {
6026 /**
6027 * DMUB visual confirm color
6028 */
6029 struct dmub_visual_confirm_color visual_confirm_color;
6030 };
6031
6032 /**
6033 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
6034 */
6035 struct dmub_rb_cmd_get_visual_confirm_color {
6036 /**
6037 * Command header.
6038 */
6039 struct dmub_cmd_header header;
6040 /**
6041 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
6042 */
6043 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
6044 };
6045
6046 /**
6047 * enum dmub_cmd_panel_cntl_type - Panel control command.
6048 */
6049 enum dmub_cmd_panel_cntl_type {
6050 /**
6051 * Initializes embedded panel hardware blocks.
6052 */
6053 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
6054 /**
6055 * Queries backlight info for the embedded panel.
6056 */
6057 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
6058 /**
6059 * Sets the PWM Freq as per user's requirement.
6060 */
6061 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2,
6062 };
6063
6064 /**
6065 * struct dmub_cmd_panel_cntl_data - Panel control data.
6066 */
6067 struct dmub_cmd_panel_cntl_data {
6068 uint32_t pwrseq_inst; /**< pwrseq instance */
6069 uint32_t current_backlight; /* in/out */
6070 uint32_t bl_pwm_cntl; /* in/out */
6071 uint32_t bl_pwm_period_cntl; /* in/out */
6072 uint32_t bl_pwm_ref_div1; /* in/out */
6073 uint8_t is_backlight_on : 1; /* in/out */
6074 uint8_t is_powered_on : 1; /* in/out */
6075 uint8_t padding[3];
6076 uint32_t bl_pwm_ref_div2; /* in/out */
6077 uint8_t reserved[4];
6078 };
6079
6080 /**
6081 * struct dmub_rb_cmd_panel_cntl - Panel control command.
6082 */
6083 struct dmub_rb_cmd_panel_cntl {
6084 struct dmub_cmd_header header; /**< header */
6085 struct dmub_cmd_panel_cntl_data data; /**< payload */
6086 };
6087
6088 struct dmub_optc_state {
6089 uint32_t v_total_max;
6090 uint32_t v_total_min;
6091 uint32_t tg_inst;
6092 };
6093
6094 struct dmub_rb_cmd_drr_update {
6095 struct dmub_cmd_header header;
6096 struct dmub_optc_state dmub_optc_state_req;
6097 };
6098
6099 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
6100 uint32_t pix_clk_100hz;
6101 uint8_t max_ramp_step;
6102 uint8_t pipes;
6103 uint8_t min_refresh_in_hz;
6104 uint8_t pipe_count;
6105 uint8_t pipe_index[4];
6106 };
6107
6108 struct dmub_cmd_fw_assisted_mclk_switch_config {
6109 uint8_t fams_enabled;
6110 uint8_t visual_confirm_enabled;
6111 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
6112 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
6113 };
6114
6115 struct dmub_rb_cmd_fw_assisted_mclk_switch {
6116 struct dmub_cmd_header header;
6117 struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
6118 };
6119
6120 /**
6121 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
6122 */
6123 struct dmub_cmd_lvtma_control_data {
6124 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
6125 uint8_t bypass_panel_control_wait;
6126 uint8_t reserved_0[2]; /**< For future use */
6127 uint8_t pwrseq_inst; /**< LVTMA control instance */
6128 uint8_t reserved_1[3]; /**< For future use */
6129 };
6130
6131 /**
6132 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
6133 */
6134 struct dmub_rb_cmd_lvtma_control {
6135 /**
6136 * Command header.
6137 */
6138 struct dmub_cmd_header header;
6139 /**
6140 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
6141 */
6142 struct dmub_cmd_lvtma_control_data data;
6143 };
6144
6145 /**
6146 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
6147 */
6148 struct dmub_rb_cmd_transmitter_query_dp_alt_data {
6149 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
6150 uint8_t is_usb; /**< is phy is usb */
6151 uint8_t is_dp_alt_disable; /**< is dp alt disable */
6152 uint8_t is_dp4; /**< is dp in 4 lane */
6153 };
6154
6155 /**
6156 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
6157 */
6158 struct dmub_rb_cmd_transmitter_query_dp_alt {
6159 struct dmub_cmd_header header; /**< header */
6160 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
6161 };
6162
6163 struct phy_test_mode {
6164 uint8_t mode;
6165 uint8_t pat0;
6166 uint8_t pad[2];
6167 };
6168
6169 /**
6170 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
6171 */
6172 struct dmub_rb_cmd_transmitter_set_phy_fsm_data {
6173 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
6174 uint8_t mode; /**< HDMI/DP/DP2 etc */
6175 uint8_t lane_num; /**< Number of lanes */
6176 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */
6177 struct phy_test_mode test_mode;
6178 enum dmub_phy_fsm_state state;
6179 uint32_t status;
6180 uint8_t pad;
6181 };
6182
6183 /**
6184 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
6185 */
6186 struct dmub_rb_cmd_transmitter_set_phy_fsm {
6187 struct dmub_cmd_header header; /**< header */
6188 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */
6189 };
6190
6191 /**
6192 * Maximum number of bytes a chunk sent to DMUB for parsing
6193 */
6194 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
6195
6196 /**
6197 * Represent a chunk of CEA blocks sent to DMUB for parsing
6198 */
6199 struct dmub_cmd_send_edid_cea {
6200 uint16_t offset; /**< offset into the CEA block */
6201 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
6202 uint16_t cea_total_length; /**< total length of the CEA block */
6203 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
6204 uint8_t pad[3]; /**< padding and for future expansion */
6205 };
6206
6207 /**
6208 * Result of VSDB parsing from CEA block
6209 */
6210 struct dmub_cmd_edid_cea_amd_vsdb {
6211 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
6212 uint8_t freesync_supported; /**< 1 if Freesync is supported */
6213 uint16_t amd_vsdb_version; /**< AMD VSDB version */
6214 uint16_t min_frame_rate; /**< Maximum frame rate */
6215 uint16_t max_frame_rate; /**< Minimum frame rate */
6216 };
6217
6218 /**
6219 * Result of sending a CEA chunk
6220 */
6221 struct dmub_cmd_edid_cea_ack {
6222 uint16_t offset; /**< offset of the chunk into the CEA block */
6223 uint8_t success; /**< 1 if this sending of chunk succeeded */
6224 uint8_t pad; /**< padding and for future expansion */
6225 };
6226
6227 /**
6228 * Specify whether the result is an ACK/NACK or the parsing has finished
6229 */
6230 enum dmub_cmd_edid_cea_reply_type {
6231 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
6232 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
6233 };
6234
6235 /**
6236 * Definition of a DMUB_CMD__EDID_CEA command.
6237 */
6238 struct dmub_rb_cmd_edid_cea {
6239 struct dmub_cmd_header header; /**< Command header */
6240 union dmub_cmd_edid_cea_data {
6241 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
6242 struct dmub_cmd_edid_cea_output { /**< output with results */
6243 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
6244 union {
6245 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
6246 struct dmub_cmd_edid_cea_ack ack;
6247 };
6248 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */
6249 } data; /**< Command data */
6250
6251 };
6252
6253 /**
6254 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
6255 */
6256 struct dmub_cmd_cable_id_input {
6257 uint8_t phy_inst; /**< phy inst for cable id data */
6258 };
6259
6260 /**
6261 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
6262 */
6263 struct dmub_cmd_cable_id_output {
6264 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
6265 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */
6266 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
6267 uint8_t RESERVED :2; /**< reserved means not defined */
6268 };
6269
6270 /**
6271 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
6272 */
6273 struct dmub_rb_cmd_get_usbc_cable_id {
6274 struct dmub_cmd_header header; /**< Command header */
6275 /**
6276 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
6277 */
6278 union dmub_cmd_cable_id_data {
6279 struct dmub_cmd_cable_id_input input; /**< Input */
6280 struct dmub_cmd_cable_id_output output; /**< Output */
6281 uint8_t output_raw; /**< Raw data output */
6282 } data;
6283 };
6284
6285 enum dmub_cmd_fused_io_sub_type {
6286 DMUB_CMD__FUSED_IO_EXECUTE = 0,
6287 DMUB_CMD__FUSED_IO_ABORT = 1,
6288 };
6289
6290 enum dmub_cmd_fused_request_type {
6291 FUSED_REQUEST_READ,
6292 FUSED_REQUEST_WRITE,
6293 FUSED_REQUEST_POLL,
6294 };
6295
6296 enum dmub_cmd_fused_request_status {
6297 FUSED_REQUEST_STATUS_SUCCESS,
6298 FUSED_REQUEST_STATUS_BEGIN,
6299 FUSED_REQUEST_STATUS_SUBMIT,
6300 FUSED_REQUEST_STATUS_REPLY,
6301 FUSED_REQUEST_STATUS_POLL,
6302 FUSED_REQUEST_STATUS_ABORTED,
6303 FUSED_REQUEST_STATUS_FAILED = 0x80,
6304 FUSED_REQUEST_STATUS_INVALID,
6305 FUSED_REQUEST_STATUS_BUSY,
6306 FUSED_REQUEST_STATUS_TIMEOUT,
6307 FUSED_REQUEST_STATUS_POLL_TIMEOUT,
6308 };
6309
6310 struct dmub_cmd_fused_request {
6311 uint8_t status;
6312 uint8_t type : 2;
6313 uint8_t _reserved0 : 3;
6314 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing
6315 uint8_t identifier;
6316 uint8_t _reserved1;
6317 uint32_t timeout_us;
6318 union dmub_cmd_fused_request_location {
6319 struct dmub_cmd_fused_request_location_i2c {
6320 uint8_t is_aux : 1; // False
6321 uint8_t ddc_line : 3;
6322 uint8_t over_aux : 1;
6323 uint8_t _reserved0 : 3;
6324 uint8_t address;
6325 uint8_t offset;
6326 uint8_t length;
6327 } i2c;
6328 struct dmub_cmd_fused_request_location_aux {
6329 uint32_t is_aux : 1; // True
6330 uint32_t ddc_line : 3;
6331 uint32_t address : 20;
6332 uint32_t length : 8; // Automatically split into 16B transactions
6333 } aux;
6334 } u;
6335 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected
6336 };
6337
6338 struct dmub_rb_cmd_fused_io {
6339 struct dmub_cmd_header header;
6340 struct dmub_cmd_fused_request request;
6341 };
6342
6343 /**
6344 * Command type of a DMUB_CMD__SECURE_DISPLAY command
6345 */
6346 enum dmub_cmd_secure_display_type {
6347 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */
6348 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,
6349 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY,
6350 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE,
6351 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY
6352 };
6353
6354 #define MAX_ROI_NUM 2
6355
6356 struct dmub_cmd_roi_info {
6357 uint16_t x_start;
6358 uint16_t x_end;
6359 uint16_t y_start;
6360 uint16_t y_end;
6361 uint8_t otg_id;
6362 uint8_t phy_id;
6363 };
6364
6365 struct dmub_cmd_roi_window_ctl {
6366 uint16_t x_start;
6367 uint16_t x_end;
6368 uint16_t y_start;
6369 uint16_t y_end;
6370 bool enable;
6371 };
6372
6373 struct dmub_cmd_roi_ctl_info {
6374 uint8_t otg_id;
6375 uint8_t phy_id;
6376 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM];
6377 };
6378
6379 /**
6380 * Definition of a DMUB_CMD__SECURE_DISPLAY command
6381 */
6382 struct dmub_rb_cmd_secure_display {
6383 struct dmub_cmd_header header;
6384 /**
6385 * Data passed from driver to dmub firmware.
6386 */
6387 struct dmub_cmd_roi_info roi_info;
6388 struct dmub_cmd_roi_ctl_info mul_roi_ctl;
6389 };
6390
6391 /**
6392 * Command type of a DMUB_CMD__PSP command
6393 */
6394 enum dmub_cmd_psp_type {
6395 DMUB_CMD__PSP_ASSR_ENABLE = 0
6396 };
6397
6398 /**
6399 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command.
6400 */
6401 struct dmub_cmd_assr_enable_data {
6402 /**
6403 * ASSR enable or disable.
6404 */
6405 uint8_t enable;
6406 /**
6407 * PHY port type.
6408 * Indicates eDP / non-eDP port type
6409 */
6410 uint8_t phy_port_type;
6411 /**
6412 * PHY port ID.
6413 */
6414 uint8_t phy_port_id;
6415 /**
6416 * Link encoder index.
6417 */
6418 uint8_t link_enc_index;
6419 /**
6420 * HPO mode.
6421 */
6422 uint8_t hpo_mode;
6423
6424 /**
6425 * Reserved field.
6426 */
6427 uint8_t reserved[7];
6428 };
6429
6430 /**
6431 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
6432 */
6433 struct dmub_rb_cmd_assr_enable {
6434 /**
6435 * Command header.
6436 */
6437 struct dmub_cmd_header header;
6438
6439 /**
6440 * Assr data.
6441 */
6442 struct dmub_cmd_assr_enable_data assr_data;
6443
6444 /**
6445 * Reserved field.
6446 */
6447 uint32_t reserved[3];
6448 };
6449
6450 /**
6451 * Current definition of "ips_mode" from driver
6452 */
6453 enum ips_residency_mode {
6454 IPS_RESIDENCY__IPS1_MAX,
6455 IPS_RESIDENCY__IPS2,
6456 IPS_RESIDENCY__IPS1_RCG,
6457 IPS_RESIDENCY__IPS1_ONO2_ON,
6458 IPS_RESIDENCY__IPS1_Z8_RETENTION,
6459 IPS_RESIDENCY__PG_ONO_LAST_SEEN_IN_IPS,
6460 IPS_RESIDENCY__PG_ONO_CURRENT_STATE
6461 };
6462
6463 #define NUM_IPS_HISTOGRAM_BUCKETS 16
6464
6465 /**
6466 * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats
6467 */
6468 struct dmub_ips_residency_info {
6469 uint32_t residency_millipercent;
6470 uint32_t entry_counter;
6471 uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS];
6472 uint64_t total_time_us;
6473 uint64_t total_inactive_time_us;
6474 uint32_t ono_pg_state_at_collection;
6475 uint32_t ono_pg_state_last_seen_in_ips;
6476 };
6477
6478 /**
6479 * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command.
6480 */
6481 struct dmub_cmd_ips_residency_cntl_data {
6482 uint8_t panel_inst;
6483 uint8_t start_measurement;
6484 uint8_t padding[2]; // align to 4-byte boundary
6485 };
6486
6487 struct dmub_rb_cmd_ips_residency_cntl {
6488 struct dmub_cmd_header header;
6489 struct dmub_cmd_ips_residency_cntl_data cntl_data;
6490 };
6491
6492 /**
6493 * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command.
6494 */
6495 struct dmub_cmd_ips_query_residency_info_data {
6496 union dmub_addr dest;
6497 uint32_t size;
6498 uint32_t ips_mode;
6499 uint8_t panel_inst;
6500 uint8_t padding[3]; // align to 4-byte boundary
6501 };
6502
6503 struct dmub_rb_cmd_ips_query_residency_info {
6504 struct dmub_cmd_header header;
6505 struct dmub_cmd_ips_query_residency_info_data info_data;
6506 };
6507
6508 /**
6509 * struct dmub_cmd_cursor_offload_init_data - Payload for cursor offload init command.
6510 */
6511 struct dmub_cmd_cursor_offload_init_data {
6512 union dmub_addr state_addr; /**< State address for dmub_cursor_offload */
6513 uint32_t state_size; /**< State size for dmub_cursor_offload */
6514 };
6515
6516 /**
6517 * struct dmub_rb_cmd_cursor_offload_init - Data for initializing cursor offload.
6518 */
6519 struct dmub_rb_cmd_cursor_offload_init {
6520 struct dmub_cmd_header header;
6521 struct dmub_cmd_cursor_offload_init_data init_data;
6522 };
6523
6524 /**
6525 * struct dmub_cmd_cursor_offload_stream_data - Payload for cursor offload stream command.
6526 */
6527 struct dmub_cmd_cursor_offload_stream_data {
6528 uint32_t otg_inst: 4; /**< OTG instance to control */
6529 uint32_t reserved: 28; /**< Reserved for future use */
6530 uint32_t line_time_in_ns; /**< Line time in ns for the OTG */
6531 uint32_t v_total_max; /**< OTG v_total_max */
6532 };
6533
6534 /**
6535 * struct dmub_rb_cmd_cursor_offload_stream_cntl - Controls a stream for cursor offload.
6536 */
6537 struct dmub_rb_cmd_cursor_offload_stream_cntl {
6538 struct dmub_cmd_header header;
6539 struct dmub_cmd_cursor_offload_stream_data data;
6540 };
6541
6542 /**
6543 * Data passed from driver to FW in a DMUB_CMD__PR_ENABLE command.
6544 */
6545 struct dmub_cmd_pr_enable_data {
6546 /**
6547 * Panel Replay enable or disable.
6548 */
6549 uint8_t enable;
6550 /**
6551 * Panel Instance.
6552 * Panel isntance to identify which replay_state to use
6553 * Currently the support is only for 0 or 1
6554 */
6555 uint8_t panel_inst;
6556 /**
6557 * Phy state to enter.
6558 * Values to use are defined in dmub_phy_fsm_state
6559 */
6560 uint8_t phy_fsm_state;
6561 /**
6562 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
6563 * Set this using enum phy_link_rate.
6564 * This does not support HDMI/DP2 for now.
6565 */
6566 uint8_t phy_rate;
6567 /**
6568 * @hpo_stream_enc_inst: HPO stream encoder instance
6569 */
6570 uint8_t hpo_stream_enc_inst;
6571 /**
6572 * @hpo_link_enc_inst: HPO link encoder instance
6573 */
6574 uint8_t hpo_link_enc_inst;
6575 /**
6576 * @pad: Align structure to 4 byte boundary.
6577 */
6578 uint8_t pad[2];
6579 };
6580
6581 /**
6582 * Definition of a DMUB_CMD__PR_ENABLE command.
6583 * Panel Replay enable/disable is controlled using action in data.
6584 */
6585 struct dmub_rb_cmd_pr_enable {
6586 /**
6587 * Command header.
6588 */
6589 struct dmub_cmd_header header;
6590
6591 struct dmub_cmd_pr_enable_data data;
6592 };
6593
6594 /**
6595 * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command.
6596 */
6597 struct dmub_cmd_pr_copy_settings_data {
6598 /**
6599 * Flags that can be set by driver to change some replay behaviour.
6600 */
6601 union pr_debug_flags debug;
6602
6603 /**
6604 * @flags: Flags used to determine feature functionality.
6605 */
6606 union pr_hw_flags flags;
6607
6608 /**
6609 * DPP HW instance.
6610 */
6611 uint8_t dpp_inst;
6612 /**
6613 * OTG HW instance.
6614 */
6615 uint8_t otg_inst;
6616 /**
6617 * DIG FE HW instance.
6618 */
6619 uint8_t digfe_inst;
6620 /**
6621 * DIG BE HW instance.
6622 */
6623 uint8_t digbe_inst;
6624 /**
6625 * AUX HW instance.
6626 */
6627 uint8_t aux_inst;
6628 /**
6629 * Panel Instance.
6630 * Panel isntance to identify which psr_state to use
6631 * Currently the support is only for 0 or 1
6632 */
6633 uint8_t panel_inst;
6634 /**
6635 * PHY instance.
6636 */
6637 uint8_t dpphy_inst;
6638 /**
6639 * Determines if SMU optimzations are enabled/disabled.
6640 */
6641 uint8_t smu_optimizations_en;
6642 /**
6643 * Length of each horizontal line in ns.
6644 */
6645 uint32_t line_time_in_ns;
6646 /*
6647 * Use FSFT afftet pixel clk
6648 */
6649 uint32_t pix_clk_100hz;
6650 /*
6651 * Use Original pixel clock
6652 */
6653 uint32_t sink_pix_clk_100hz;
6654 /**
6655 * Use for AUX-less ALPM LFPS wake operation
6656 */
6657 struct dmub_alpm_auxless_data auxless_alpm_data;
6658 /**
6659 * DSC Slice height.
6660 */
6661 uint16_t dsc_slice_height;
6662 /*
6663 * Use FSM state for Replay power up/down
6664 */
6665 uint8_t use_phy_fsm;
6666 /**
6667 * @hpo_stream_enc_inst: HPO stream encoder instance
6668 */
6669 uint8_t hpo_stream_enc_inst;
6670 /**
6671 * @hpo_link_enc_inst: HPO link encoder instance
6672 */
6673 uint8_t hpo_link_enc_inst;
6674 /*
6675 * Selective Update granularity needed.
6676 */
6677 uint8_t su_granularity_needed;
6678 /*
6679 * Horizontal granularity for Selective Update.
6680 */
6681 uint16_t su_x_granularity;
6682 /*
6683 * Extended caps of vertical granularity for Selective Update.
6684 */
6685 uint16_t su_y_granularity_extended_caps;
6686 /*
6687 * Vertical granularity for Selective Update.
6688 */
6689 uint8_t su_y_granularity;
6690 /**
6691 * @main_link_activity_option: Indicates main link activity option selected
6692 */
6693 uint8_t main_link_activity_option;
6694 };
6695
6696 /**
6697 * Definition of a DMUB_CMD__PR_COPY_SETTINGS command.
6698 */
6699 struct dmub_rb_cmd_pr_copy_settings {
6700 /**
6701 * Command header.
6702 */
6703 struct dmub_cmd_header header;
6704 /**
6705 * Data passed from driver to FW in a DMUB_CMD__PR_COPY_SETTINGS command.
6706 */
6707 struct dmub_cmd_pr_copy_settings_data data;
6708 };
6709
6710 union dmub_pr_runtime_flags {
6711 struct {
6712 uint32_t disable_abm_optimization : 1; // Disable ABM optimization for PR
6713 } bitfields;
6714 uint32_t u32All;
6715 };
6716
6717 struct dmub_cmd_pr_update_state_data {
6718 /**
6719 * Panel Instance.
6720 * Panel isntance to identify which psr_state to use
6721 * Currently the support is only for 0 or 1
6722 */
6723 uint8_t panel_inst;
6724
6725 uint8_t pad[3]; // align to 4-byte boundary
6726 /*
6727 * Update flags to control the update behavior.
6728 */
6729 uint32_t update_flag;
6730 /**
6731 * state/data to set.
6732 */
6733 uint32_t coasting_vtotal;
6734 uint32_t sync_mode;
6735
6736 union dmub_pr_runtime_flags pr_runtime_flags;
6737 };
6738
6739 struct dmub_cmd_pr_general_cmd_data {
6740 /**
6741 * Panel Instance.
6742 * Panel isntance to identify which psr_state to use
6743 * Currently the support is only for 0 or 1
6744 */
6745 uint8_t panel_inst;
6746 /**
6747 * subtype: PR general cmd sub type
6748 */
6749 uint8_t subtype;
6750
6751 uint8_t pad[2];
6752 /**
6753 * config data by different subtypes
6754 */
6755 union {
6756 uint32_t u32All;
6757 } data;
6758 };
6759
6760 /**
6761 * Definition of a DMUB_CMD__PR_UPDATE_STATE command.
6762 */
6763 struct dmub_rb_cmd_pr_update_state {
6764 /**
6765 * Command header.
6766 */
6767 struct dmub_cmd_header header;
6768 /**
6769 * Data passed from driver to FW in a DMUB_CMD__PR_UPDATE_STATE command.
6770 */
6771 struct dmub_cmd_pr_update_state_data data;
6772 };
6773
6774 /**
6775 * Definition of a DMUB_CMD__PR_GENERAL_CMD command.
6776 */
6777 struct dmub_rb_cmd_pr_general_cmd {
6778 /**
6779 * Command header.
6780 */
6781 struct dmub_cmd_header header;
6782 /**
6783 * Data passed from driver to FW in a DMUB_CMD__PR_GENERAL_CMD command.
6784 */
6785 struct dmub_cmd_pr_general_cmd_data data;
6786 };
6787
6788 /**
6789 * union dmub_rb_cmd - DMUB inbox command.
6790 */
6791 union dmub_rb_cmd {
6792 /**
6793 * Elements shared with all commands.
6794 */
6795 struct dmub_rb_cmd_common cmd_common;
6796 /**
6797 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
6798 */
6799 struct dmub_rb_cmd_read_modify_write read_modify_write;
6800 /**
6801 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
6802 */
6803 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
6804 /**
6805 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
6806 */
6807 struct dmub_rb_cmd_burst_write burst_write;
6808 /**
6809 * Definition of a DMUB_CMD__REG_REG_WAIT command.
6810 */
6811 struct dmub_rb_cmd_reg_wait reg_wait;
6812 /**
6813 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
6814 */
6815 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
6816 /**
6817 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
6818 */
6819 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
6820 /**
6821 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
6822 */
6823 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
6824 /**
6825 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
6826 */
6827 struct dmub_rb_cmd_dpphy_init dpphy_init;
6828 /**
6829 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
6830 */
6831 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
6832 /**
6833 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.
6834 */
6835 struct dmub_rb_cmd_domain_control domain_control;
6836 /**
6837 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
6838 */
6839 struct dmub_rb_cmd_psr_set_version psr_set_version;
6840 /**
6841 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
6842 */
6843 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
6844 /**
6845 * Definition of a DMUB_CMD__PSR_ENABLE command.
6846 */
6847 struct dmub_rb_cmd_psr_enable psr_enable;
6848 /**
6849 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
6850 */
6851 struct dmub_rb_cmd_psr_set_level psr_set_level;
6852 /**
6853 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
6854 */
6855 struct dmub_rb_cmd_psr_force_static psr_force_static;
6856 /**
6857 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
6858 */
6859 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
6860 /**
6861 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
6862 */
6863 struct dmub_rb_cmd_update_cursor_info update_cursor_info;
6864 /**
6865 * Definition of a DMUB_CMD__HW_LOCK command.
6866 * Command is used by driver and FW.
6867 */
6868 struct dmub_rb_cmd_lock_hw lock_hw;
6869 /**
6870 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
6871 */
6872 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
6873 /**
6874 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
6875 */
6876 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;
6877 /**
6878 * Definition of a DMUB_CMD__PLAT_54186_WA command.
6879 */
6880 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
6881 /**
6882 * Definition of a DMUB_CMD__MALL command.
6883 */
6884 struct dmub_rb_cmd_mall mall;
6885
6886 /**
6887 * Definition of a DMUB_CMD__CAB command.
6888 */
6889 struct dmub_rb_cmd_cab_for_ss cab;
6890
6891 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;
6892
6893 /**
6894 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
6895 */
6896 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
6897
6898 /**
6899 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
6900 */
6901 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
6902
6903 /**
6904 * Definition of DMUB_CMD__PANEL_CNTL commands.
6905 */
6906 struct dmub_rb_cmd_panel_cntl panel_cntl;
6907
6908 /**
6909 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
6910 */
6911 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
6912
6913 /**
6914 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
6915 */
6916 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
6917
6918 /**
6919 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
6920 */
6921 struct dmub_rb_cmd_abm_set_level abm_set_level;
6922
6923 /**
6924 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
6925 */
6926 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
6927
6928 /**
6929 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
6930 */
6931 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
6932
6933 /**
6934 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
6935 */
6936 struct dmub_rb_cmd_abm_init_config abm_init_config;
6937
6938 /**
6939 * Definition of a DMUB_CMD__ABM_PAUSE command.
6940 */
6941 struct dmub_rb_cmd_abm_pause abm_pause;
6942
6943 /**
6944 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
6945 */
6946 struct dmub_rb_cmd_abm_save_restore abm_save_restore;
6947
6948 /**
6949 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.
6950 */
6951 struct dmub_rb_cmd_abm_query_caps abm_query_caps;
6952
6953 /**
6954 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.
6955 */
6956 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve;
6957
6958 /**
6959 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command.
6960 */
6961 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram;
6962
6963 /**
6964 * Definition of a DMUB_CMD__ABM_SET_EVENT command.
6965 */
6966 struct dmub_rb_cmd_abm_set_event abm_set_event;
6967
6968 /**
6969 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
6970 */
6971 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
6972
6973 /**
6974 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
6975 */
6976 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
6977
6978 /**
6979 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
6980 */
6981 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
6982
6983 /**
6984 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
6985 */
6986 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
6987 struct dmub_rb_cmd_drr_update drr_update;
6988 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
6989
6990 /**
6991 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
6992 */
6993 struct dmub_rb_cmd_lvtma_control lvtma_control;
6994 /**
6995 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
6996 */
6997 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
6998 /**
6999 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
7000 */
7001 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm;
7002 /**
7003 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
7004 */
7005 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
7006 /**
7007 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
7008 */
7009 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated)
7010 /**
7011 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
7012 */
7013 struct dmub_rb_cmd_set_config_request set_config_request;
7014 /**
7015 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
7016 */
7017 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;
7018 /**
7019 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command.
7020 */
7021 struct dmub_rb_cmd_set_tps_notification set_tps_notification;
7022 /**
7023 * Definition of a DMUB_CMD__EDID_CEA command.
7024 */
7025 struct dmub_rb_cmd_edid_cea edid_cea;
7026 /**
7027 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
7028 */
7029 struct dmub_rb_cmd_get_usbc_cable_id cable_id;
7030
7031 /**
7032 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
7033 */
7034 struct dmub_rb_cmd_query_hpd_state query_hpd;
7035 /**
7036 * Definition of a DMUB_CMD__SECURE_DISPLAY command.
7037 */
7038 struct dmub_rb_cmd_secure_display secure_display;
7039
7040 /**
7041 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
7042 */
7043 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
7044 /**
7045 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
7046 */
7047 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;
7048 /**
7049 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
7050 */
7051 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state;
7052 /*
7053 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
7054 */
7055 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings;
7056 /**
7057 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
7058 */
7059 struct dmub_rb_cmd_replay_enable replay_enable;
7060 /**
7061 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
7062 */
7063 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt;
7064 /**
7065 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
7066 */
7067 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal;
7068 /**
7069 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.
7070 */
7071 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal;
7072
7073 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync;
7074 /**
7075 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
7076 */
7077 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer;
7078 /**
7079 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
7080 */
7081 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal;
7082 /**
7083 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
7084 */
7085 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp;
7086 /**
7087 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
7088 */
7089 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd;
7090 /**
7091 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
7092 */
7093 struct dmub_rb_cmd_assr_enable assr_enable;
7094
7095 struct dmub_rb_cmd_fams2 fams2_config;
7096
7097 struct dmub_rb_cmd_ib ib_fams2_config;
7098
7099 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update;
7100
7101 struct dmub_rb_cmd_fams2_flip fams2_flip;
7102
7103 struct dmub_rb_cmd_fused_io fused_io;
7104
7105 /**
7106 * Definition of a DMUB_CMD__LSDMA command.
7107 */
7108 struct dmub_rb_cmd_lsdma lsdma;
7109
7110 struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl;
7111
7112 struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info;
7113 /**
7114 * Definition of a DMUB_CMD__CURSOR_OFFLOAD_INIT command.
7115 */
7116 struct dmub_rb_cmd_cursor_offload_init cursor_offload_init;
7117 /**
7118 * Definition of a DMUB_CMD__CURSOR_OFFLOAD control commands.
7119 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_ENABLE
7120 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_DISABLE
7121 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_PROGRAM
7122 * - DMUB_CMD__CURSOR_OFFLOAD_STREAM_UPDATE_DRR
7123 */
7124 struct dmub_rb_cmd_cursor_offload_stream_cntl cursor_offload_stream_ctnl;
7125 /**
7126 * Definition of a DMUB_CMD__SMART_POWER_OLED_ENABLE command.
7127 */
7128 struct dmub_rb_cmd_smart_power_oled_enable smart_power_oled_enable;
7129 /**
7130 * Definition of a DMUB_CMD__DMUB_CMD__SMART_POWER_OLED_GETMAXCLL command.
7131 */
7132 struct dmub_rb_cmd_smart_power_oled_getmaxcll smart_power_oled_getmaxcll;
7133 /*
7134 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
7135 */
7136 struct dmub_rb_cmd_pr_copy_settings pr_copy_settings;
7137 /**
7138 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
7139 */
7140 struct dmub_rb_cmd_pr_enable pr_enable;
7141
7142 struct dmub_rb_cmd_pr_update_state pr_update_state;
7143
7144 struct dmub_rb_cmd_pr_general_cmd pr_general_cmd;
7145 };
7146
7147 /**
7148 * union dmub_rb_out_cmd - Outbox command
7149 */
7150 union dmub_rb_out_cmd {
7151 /**
7152 * Parameters common to every command.
7153 */
7154 struct dmub_rb_cmd_common cmd_common;
7155 /**
7156 * AUX reply command.
7157 */
7158 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
7159 /**
7160 * HPD notify command.
7161 */
7162 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
7163 /**
7164 * SET_CONFIG reply command.
7165 */
7166 struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
7167 /**
7168 * DPIA notification command.
7169 */
7170 struct dmub_rb_cmd_dpia_notification dpia_notification;
7171 /**
7172 * HPD sense notification command.
7173 */
7174 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify;
7175 struct dmub_rb_cmd_fused_io fused_io;
7176 };
7177 #pragma pack(pop)
7178
7179
7180 //==============================================================================
7181 //</DMUB_CMD>===================================================================
7182 //==============================================================================
7183 //< DMUB_RB>====================================================================
7184 //==============================================================================
7185
7186 /**
7187 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
7188 */
7189 struct dmub_rb_init_params {
7190 void *ctx; /**< Caller provided context pointer */
7191 void *base_address; /**< CPU base address for ring's data */
7192 uint32_t capacity; /**< Ringbuffer capacity in bytes */
7193 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
7194 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
7195 };
7196
7197 /**
7198 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
7199 */
7200 struct dmub_rb {
7201 void *base_address; /**< CPU address for the ring's data */
7202 uint32_t rptr; /**< Read pointer for consumer in bytes */
7203 uint32_t wrpt; /**< Write pointer for producer in bytes */
7204 uint32_t capacity; /**< Ringbuffer capacity in bytes */
7205
7206 void *ctx; /**< Caller provided context pointer */
7207 void *dmub; /**< Pointer to the DMUB interface */
7208 };
7209
7210 /**
7211 * @brief Checks if the ringbuffer is empty.
7212 *
7213 * @param rb DMUB Ringbuffer
7214 * @return true if empty
7215 * @return false otherwise
7216 */
dmub_rb_empty(struct dmub_rb * rb)7217 static inline bool dmub_rb_empty(struct dmub_rb *rb)
7218 {
7219 return (rb->wrpt == rb->rptr);
7220 }
7221
7222 /**
7223 * @brief gets number of outstanding requests in the RB
7224 *
7225 * @param rb DMUB Ringbuffer
7226 * @return true if full
7227 */
dmub_rb_num_outstanding(struct dmub_rb * rb)7228 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb)
7229 {
7230 uint32_t data_count;
7231
7232 if (rb->wrpt >= rb->rptr)
7233 data_count = rb->wrpt - rb->rptr;
7234 else
7235 data_count = rb->capacity - (rb->rptr - rb->wrpt);
7236
7237 return data_count / DMUB_RB_CMD_SIZE;
7238 }
7239
7240 /**
7241 * @brief gets number of free buffers in the RB
7242 *
7243 * @param rb DMUB Ringbuffer
7244 * @return true if full
7245 */
dmub_rb_num_free(struct dmub_rb * rb)7246 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb)
7247 {
7248 uint32_t data_count;
7249
7250 if (rb->wrpt >= rb->rptr)
7251 data_count = rb->wrpt - rb->rptr;
7252 else
7253 data_count = rb->capacity - (rb->rptr - rb->wrpt);
7254
7255 /* +1 because 1 entry is always unusable */
7256 data_count += DMUB_RB_CMD_SIZE;
7257
7258 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE;
7259 }
7260
7261 /**
7262 * @brief Checks if the ringbuffer is full
7263 *
7264 * @param rb DMUB Ringbuffer
7265 * @return true if full
7266 * @return false otherwise
7267 */
dmub_rb_full(struct dmub_rb * rb)7268 static inline bool dmub_rb_full(struct dmub_rb *rb)
7269 {
7270 uint32_t data_count;
7271
7272 if (rb->wrpt >= rb->rptr)
7273 data_count = rb->wrpt - rb->rptr;
7274 else
7275 data_count = rb->capacity - (rb->rptr - rb->wrpt);
7276
7277 /* -1 because 1 entry is always unusable */
7278 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
7279 }
7280
7281 /**
7282 * @brief Pushes a command into the ringbuffer
7283 *
7284 * @param rb DMUB ringbuffer
7285 * @param cmd The command to push
7286 * @return true if the ringbuffer was not full
7287 * @return false otherwise
7288 */
dmub_rb_push_front(struct dmub_rb * rb,const union dmub_rb_cmd * cmd)7289 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
7290 const union dmub_rb_cmd *cmd)
7291 {
7292 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
7293 const uint8_t *src = (const uint8_t *)cmd;
7294 uint8_t i;
7295
7296 if (rb->capacity == 0)
7297 return false;
7298
7299 if (dmub_rb_full(rb))
7300 return false;
7301
7302 // copying data
7303 for (i = 0; i < DMUB_RB_CMD_SIZE; i++)
7304 *dst++ = *src++;
7305
7306 rb->wrpt += DMUB_RB_CMD_SIZE;
7307
7308 if (rb->wrpt >= rb->capacity)
7309 rb->wrpt %= rb->capacity;
7310
7311 return true;
7312 }
7313
7314 /**
7315 * @brief Pushes a command into the DMUB outbox ringbuffer
7316 *
7317 * @param rb DMUB outbox ringbuffer
7318 * @param cmd Outbox command
7319 * @return true if not full
7320 * @return false otherwise
7321 */
dmub_rb_out_push_front(struct dmub_rb * rb,const union dmub_rb_out_cmd * cmd)7322 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
7323 const union dmub_rb_out_cmd *cmd)
7324 {
7325 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
7326 const uint8_t *src = (const uint8_t *)cmd;
7327
7328 if (rb->capacity == 0)
7329 return false;
7330
7331 if (dmub_rb_full(rb))
7332 return false;
7333
7334 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
7335
7336 rb->wrpt += DMUB_RB_CMD_SIZE;
7337
7338 if (rb->wrpt >= rb->capacity)
7339 rb->wrpt %= rb->capacity;
7340
7341 return true;
7342 }
7343
7344 /**
7345 * @brief Returns the next unprocessed command in the ringbuffer.
7346 *
7347 * @param rb DMUB ringbuffer
7348 * @param cmd The command to return
7349 * @return true if not empty
7350 * @return false otherwise
7351 */
dmub_rb_front(struct dmub_rb * rb,union dmub_rb_cmd ** cmd)7352 static inline bool dmub_rb_front(struct dmub_rb *rb,
7353 union dmub_rb_cmd **cmd)
7354 {
7355 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
7356
7357 if (dmub_rb_empty(rb))
7358 return false;
7359
7360 *cmd = (union dmub_rb_cmd *)rb_cmd;
7361
7362 return true;
7363 }
7364
7365 /**
7366 * @brief Determines the next ringbuffer offset.
7367 *
7368 * @param rb DMUB inbox ringbuffer
7369 * @param num_cmds Number of commands
7370 * @param next_rptr The next offset in the ringbuffer
7371 */
dmub_rb_get_rptr_with_offset(struct dmub_rb * rb,uint32_t num_cmds,uint32_t * next_rptr)7372 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
7373 uint32_t num_cmds,
7374 uint32_t *next_rptr)
7375 {
7376 if (rb->capacity == 0)
7377 return;
7378
7379 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
7380
7381 if (*next_rptr >= rb->capacity)
7382 *next_rptr %= rb->capacity;
7383 }
7384
7385 /**
7386 * @brief Returns a pointer to a command in the inbox.
7387 *
7388 * @param rb DMUB inbox ringbuffer
7389 * @param cmd The inbox command to return
7390 * @param rptr The ringbuffer offset
7391 * @return true if not empty
7392 * @return false otherwise
7393 */
dmub_rb_peek_offset(struct dmub_rb * rb,union dmub_rb_cmd ** cmd,uint32_t rptr)7394 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
7395 union dmub_rb_cmd **cmd,
7396 uint32_t rptr)
7397 {
7398 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
7399
7400 if (dmub_rb_empty(rb))
7401 return false;
7402
7403 *cmd = (union dmub_rb_cmd *)rb_cmd;
7404
7405 return true;
7406 }
7407
7408 /**
7409 * @brief Returns the next unprocessed command in the outbox.
7410 *
7411 * @param rb DMUB outbox ringbuffer
7412 * @param cmd The outbox command to return
7413 * @return true if not empty
7414 * @return false otherwise
7415 */
dmub_rb_out_front(struct dmub_rb * rb,union dmub_rb_out_cmd * cmd)7416 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
7417 union dmub_rb_out_cmd *cmd)
7418 {
7419 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);
7420 uint64_t *dst = (uint64_t *)cmd;
7421 uint8_t i;
7422
7423 if (dmub_rb_empty(rb))
7424 return false;
7425
7426 // copying data
7427 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
7428 *dst++ = *src++;
7429
7430 return true;
7431 }
7432
7433 /**
7434 * @brief Removes the front entry in the ringbuffer.
7435 *
7436 * @param rb DMUB ringbuffer
7437 * @return true if the command was removed
7438 * @return false if there were no commands
7439 */
dmub_rb_pop_front(struct dmub_rb * rb)7440 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
7441 {
7442 if (rb->capacity == 0)
7443 return false;
7444
7445 if (dmub_rb_empty(rb))
7446 return false;
7447
7448 rb->rptr += DMUB_RB_CMD_SIZE;
7449
7450 if (rb->rptr >= rb->capacity)
7451 rb->rptr %= rb->capacity;
7452
7453 return true;
7454 }
7455
7456 /**
7457 * @brief Flushes commands in the ringbuffer to framebuffer memory.
7458 *
7459 * Avoids a race condition where DMCUB accesses memory while
7460 * there are still writes in flight to framebuffer.
7461 *
7462 * @param rb DMUB ringbuffer
7463 */
dmub_rb_flush_pending(const struct dmub_rb * rb)7464 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
7465 {
7466 uint32_t rptr = rb->rptr;
7467 uint32_t wptr = rb->wrpt;
7468
7469 if (rb->capacity == 0)
7470 return;
7471
7472 while (rptr != wptr) {
7473 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
7474 uint8_t i;
7475
7476 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
7477 (void)READ_ONCE(*data++);
7478
7479 rptr += DMUB_RB_CMD_SIZE;
7480 if (rptr >= rb->capacity)
7481 rptr %= rb->capacity;
7482 }
7483 }
7484
7485 /**
7486 * @brief Initializes a DMCUB ringbuffer
7487 *
7488 * @param rb DMUB ringbuffer
7489 * @param init_params initial configuration for the ringbuffer
7490 */
dmub_rb_init(struct dmub_rb * rb,struct dmub_rb_init_params * init_params)7491 static inline void dmub_rb_init(struct dmub_rb *rb,
7492 struct dmub_rb_init_params *init_params)
7493 {
7494 rb->base_address = init_params->base_address;
7495 rb->capacity = init_params->capacity;
7496 rb->rptr = init_params->read_ptr;
7497 rb->wrpt = init_params->write_ptr;
7498 }
7499
7500 /**
7501 * @brief Copies output data from in/out commands into the given command.
7502 *
7503 * @param rb DMUB ringbuffer
7504 * @param cmd Command to copy data into
7505 */
dmub_rb_get_return_data(struct dmub_rb * rb,union dmub_rb_cmd * cmd)7506 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
7507 union dmub_rb_cmd *cmd)
7508 {
7509 // Copy rb entry back into command
7510 uint8_t *rd_ptr = (rb->rptr == 0) ?
7511 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
7512 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
7513
7514 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
7515 }
7516
7517 //==============================================================================
7518 //</DMUB_RB>====================================================================
7519 //==============================================================================
7520 #endif /* _DMUB_CMD_H_ */
7521