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Searched refs:dev_priv (Results 1 – 25 of 58) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Di9xx_plane_regs.h12 #define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) argument
15 #define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) argument
49 #define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) argument
52 #define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) argument
55 #define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) argument
58 #define DSPPOS(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) argument
65 #define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) argument
72 #define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) argument
76 #define DSPTILEOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) argument
83 #define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) argument
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H A Dintel_pipe_crc_regs.h12 #define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_CTL_A) argument
63 #define PIPE_CRC_EXP_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_GREEN_A) argument
67 #define PIPE_CRC_EXP_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_BLUE_A) argument
71 #define PIPE_CRC_EXP_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES1_A_I9… argument
75 #define PIPE_CRC_EXP_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES2_A_G4X) argument
79 #define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RED_A) argument
82 #define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_GREEN_A) argument
85 #define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_BLUE_A) argument
88 #define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_… argument
91 #define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A… argument
H A Dintel_psr_regs.h13 #define TRANS_EXITLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A) argument
27 #define EDP_PSR_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A) argument
70 #define TRANS_PSR_IMR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A) argument
71 #define TRANS_PSR_IIR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A) argument
90 #define EDP_PSR_AUX_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A) argument
100 #define EDP_PSR_AUX_DATA(dev_priv, tran, i) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4… argument
105 #define EDP_PSR_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A) argument
130 #define EDP_PSR_PERF_CNT(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A) argument
137 #define EDP_PSR_DEBUG(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A) argument
157 #define EDP_PSR2_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A) argument
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H A Dintel_cursor_regs.h12 #define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURACNTR) argument
44 #define CURBASE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURABASE) argument
47 #define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS) argument
56 #define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS_ERLY_TPT) argument
59 #define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASIZE) argument
66 #define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_FBC_CTL_A) argument
72 #define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_CHICKEN_A) argument
75 #define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASURFLIVE) argument
H A Dintel_color_regs.h33 #define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ argument
42 #define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ argument
264 #define PIPE_WGC_C01_C00(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00) argument
265 #define PIPE_WGC_C02(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02) argument
266 #define PIPE_WGC_C11_C10(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10) argument
267 #define PIPE_WGC_C12(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12) argument
268 #define PIPE_WGC_C21_C20(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20) argument
269 #define PIPE_WGC_C22(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22) argument
/linux/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_context.c121 static void vmw_context_cotables_unref(struct vmw_private *dev_priv, in vmw_context_cotables_unref() argument
126 u32 cotable_max = has_sm5_context(dev_priv) ? in vmw_context_cotables_unref()
144 struct vmw_private *dev_priv = res->dev_priv; in vmw_hw_context_destroy() local
153 mutex_lock(&dev_priv->cmdbuf_mutex); in vmw_hw_context_destroy()
155 mutex_lock(&dev_priv->binding_mutex); in vmw_hw_context_destroy()
158 mutex_unlock(&dev_priv->binding_mutex); in vmw_hw_context_destroy()
159 if (dev_priv->pinned_bo != NULL && in vmw_hw_context_destroy()
160 !dev_priv->query_cid_valid) in vmw_hw_context_destroy()
161 __vmw_execbuf_release_pinned_bo(dev_priv, NULL); in vmw_hw_context_destroy()
162 mutex_unlock(&dev_priv->cmdbuf_mutex); in vmw_hw_context_destroy()
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H A Dvmwgfx_overlay.c88 static int vmw_overlay_send_put(struct vmw_private *dev_priv, in vmw_overlay_send_put() argument
95 bool have_so = (dev_priv->active_display_unit != vmw_du_legacy); in vmw_overlay_send_put()
119 cmds = VMW_CMD_RESERVE(dev_priv, fifo_size); in vmw_overlay_send_put()
166 vmw_cmd_commit(dev_priv, fifo_size); in vmw_overlay_send_put()
177 static int vmw_overlay_send_stop(struct vmw_private *dev_priv, in vmw_overlay_send_stop() argument
189 cmds = VMW_CMD_RESERVE(dev_priv, sizeof(*cmds)); in vmw_overlay_send_stop()
193 ret = vmw_fallback_wait(dev_priv, false, true, 0, in vmw_overlay_send_stop()
208 vmw_cmd_commit(dev_priv, sizeof(*cmds)); in vmw_overlay_send_stop()
219 static int vmw_overlay_move_buffer(struct vmw_private *dev_priv, in vmw_overlay_move_buffer() argument
224 return vmw_bo_unpin(dev_priv, buf, inter); in vmw_overlay_move_buffer()
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H A Dvmwgfx_execbuf.c129 static int vmw_resource_context_res_add(struct vmw_private *dev_priv,
132 static int vmw_translate_mob_ptr(struct vmw_private *dev_priv,
196 static int vmw_cmd_ctx_first_setup(struct vmw_private *dev_priv, in vmw_cmd_ctx_first_setup() argument
203 ret = vmw_resource_context_res_add(dev_priv, sw_context, res); in vmw_cmd_ctx_first_setup()
208 sw_context->staged_bindings = vmw_binding_state_alloc(dev_priv); in vmw_cmd_ctx_first_setup()
217 node->staged = vmw_binding_state_alloc(dev_priv); in vmw_cmd_ctx_first_setup()
250 static unsigned int vmw_execbuf_res_size(struct vmw_private *dev_priv, in vmw_execbuf_res_size() argument
254 (res_type == vmw_res_context && dev_priv->has_mob)) ? in vmw_execbuf_res_size()
297 struct vmw_private *dev_priv = res->dev_priv; in vmw_execbuf_res_val_add() local
320 priv_size = vmw_execbuf_res_size(dev_priv, res_type); in vmw_execbuf_res_val_add()
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H A Dvmwgfx_streamoutput.c93 struct vmw_private *dev_priv = res->dev_priv; in vmw_dx_streamoutput_unscrub() local
102 cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), so->ctx->id); in vmw_dx_streamoutput_unscrub()
112 vmw_cmd_commit(dev_priv, sizeof(*cmd)); in vmw_dx_streamoutput_unscrub()
121 struct vmw_private *dev_priv = res->dev_priv; in vmw_dx_streamoutput_create() local
128 mutex_lock(&dev_priv->binding_mutex); in vmw_dx_streamoutput_create()
130 mutex_unlock(&dev_priv->binding_mutex); in vmw_dx_streamoutput_create()
141 struct vmw_private *dev_priv = res->dev_priv; in vmw_dx_streamoutput_bind() local
148 mutex_lock(&dev_priv->binding_mutex); in vmw_dx_streamoutput_bind()
150 mutex_unlock(&dev_priv->binding_mutex); in vmw_dx_streamoutput_bind()
163 struct vmw_private *dev_priv = res->dev_priv; in vmw_dx_streamoutput_scrub() local
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H A Dvmwgfx_so.c132 struct vmw_private *dev_priv = res->dev_priv; in vmw_view_commit_notify() local
134 mutex_lock(&dev_priv->binding_mutex); in vmw_view_commit_notify()
149 mutex_unlock(&dev_priv->binding_mutex); in vmw_view_commit_notify()
164 struct vmw_private *dev_priv = res->dev_priv; in vmw_view_create() local
170 mutex_lock(&dev_priv->binding_mutex); in vmw_view_create()
172 mutex_unlock(&dev_priv->binding_mutex); in vmw_view_create()
176 cmd = VMW_CMD_CTX_RESERVE(res->dev_priv, view->cmd_size, view->ctx->id); in vmw_view_create()
178 mutex_unlock(&dev_priv->binding_mutex); in vmw_view_create()
187 vmw_cmd_commit(res->dev_priv, view->cmd_size); in vmw_view_create()
191 mutex_unlock(&dev_priv->binding_mutex); in vmw_view_create()
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H A Dvmwgfx_gmr.c37 static int vmw_gmr2_bind(struct vmw_private *dev_priv, in vmw_gmr2_bind() argument
53 cmd_orig = cmd = VMW_CMD_RESERVE(dev_priv, cmd_size); in vmw_gmr2_bind()
100 vmw_cmd_commit(dev_priv, cmd_size); in vmw_gmr2_bind()
105 static void vmw_gmr2_unbind(struct vmw_private *dev_priv, in vmw_gmr2_unbind() argument
112 cmd = VMW_CMD_RESERVE(dev_priv, define_size); in vmw_gmr2_unbind()
122 vmw_cmd_commit(dev_priv, define_size); in vmw_gmr2_unbind()
126 int vmw_gmr_bind(struct vmw_private *dev_priv, in vmw_gmr_bind() argument
138 if (unlikely(!(dev_priv->capabilities & SVGA_CAP_GMR2))) in vmw_gmr_bind()
141 return vmw_gmr2_bind(dev_priv, &data_iter, num_pages, gmr_id); in vmw_gmr_bind()
145 void vmw_gmr_unbind(struct vmw_private *dev_priv, int gmr_id) in vmw_gmr_unbind() argument
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H A Dvmwgfx_ttm_buffer.c137 struct device *dev = vmw_tt->dev_priv->drm.dev; in vmw_ttm_unmap_from_dma()
158 struct device *dev = vmw_tt->dev_priv->drm.dev; in vmw_ttm_map_for_dma()
175 struct vmw_private *dev_priv = vmw_tt->dev_priv; in vmw_ttm_map_dma() local
182 vsgt->mode = dev_priv->map_mode; in vmw_ttm_map_dma()
188 switch (dev_priv->map_mode) { in vmw_ttm_map_dma()
198 dma_get_max_seg_size(dev_priv->drm.dev), in vmw_ttm_map_dma()
217 drm_warn(&dev_priv->drm, "VSG table map failed!"); in vmw_ttm_map_dma()
235 struct vmw_private *dev_priv = vmw_tt->dev_priv; in vmw_ttm_unmap_dma() local
240 switch (dev_priv->map_mode) { in vmw_ttm_unmap_dma()
295 ret = vmw_gmr_bind(vmw_be->dev_priv, &vmw_be->vsgt, in vmw_ttm_bind()
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H A Dvmwgfx_kms.h106 struct vmw_private *dev_priv; member
170 struct vmw_private *dev_priv; member
375 int vmw_kms_helper_dirty(struct vmw_private *dev_priv,
387 void vmw_kms_helper_validation_finish(struct vmw_private *dev_priv,
393 int vmw_kms_readback(struct vmw_private *dev_priv,
400 vmw_kms_new_framebuffer(struct vmw_private *dev_priv,
405 void vmw_kms_update_implicit_fb(struct vmw_private *dev_priv);
406 void vmw_kms_create_implicit_placement_property(struct vmw_private *dev_priv);
440 int vmw_kms_ldu_init_display(struct vmw_private *dev_priv);
441 int vmw_kms_ldu_close_display(struct vmw_private *dev_priv);
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H A Dvmwgfx_cmdbuf.c115 struct vmw_private *dev_priv; member
307 vmw_write(man->dev_priv, SVGA_REG_COMMAND_HIGH, val); in vmw_cmdbuf_header_submit()
311 vmw_write(man->dev_priv, SVGA_REG_COMMAND_LOW, val); in vmw_cmdbuf_header_submit()
446 vmw_generic_waiter_remove(man->dev_priv, in vmw_cmdbuf_man_process()
448 &man->dev_priv->cmdbuf_waiters); in vmw_cmdbuf_man_process()
451 vmw_generic_waiter_add(man->dev_priv, in vmw_cmdbuf_man_process()
453 &man->dev_priv->cmdbuf_waiters); in vmw_cmdbuf_man_process()
613 vmw_cmd_send_fence(man->dev_priv, &dummy); in vmw_cmdbuf_work_func()
724 vmw_generic_waiter_add(man->dev_priv, in vmw_cmdbuf_idle()
726 &man->dev_priv->cmdbuf_waiters); in vmw_cmdbuf_idle()
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H A Dvmwgfx_cursor_plane.c39 static void vmw_send_define_cursor_cmd(struct vmw_private *dev_priv, in vmw_send_define_cursor_cmd() argument
54 cmd = VMW_CMD_RESERVE(dev_priv, cmd_size); in vmw_send_define_cursor_cmd()
70 vmw_cmd_commit_flush(dev_priv, cmd_size); in vmw_send_define_cursor_cmd()
225 struct vmw_private *dev_priv = vmw_priv(vcp->base.dev); in vmw_cursor_mob_get() local
233 if (!dev_priv->has_mob || in vmw_cursor_mob_get()
234 (dev_priv->capabilities2 & SVGA_CAP2_CURSOR_MOB) == 0) in vmw_cursor_mob_get()
237 mob_max_size = vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); in vmw_cursor_mob_get()
238 cursor_max_dim = vmw_read(dev_priv, SVGA_REG_CURSOR_MAX_DIMENSION); in vmw_cursor_mob_get()
260 ret = vmw_bo_create_and_populate(dev_priv, size, VMW_BO_DOMAIN_MOB, in vmw_cursor_mob_get()
271 ret = vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL); in vmw_cursor_mob_get()
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H A Dvmwgfx_mksstat.h102 .slot = vmw_mksstat_get_kern_slot(current->pid, dev_priv) \
108 _##kern_cntr.old_top = dev_priv->mksstat_kern_top_timer[_##kern_cntr.slot]; \
109 dev_priv->mksstat_kern_top_timer[_##kern_cntr.slot] = kern_cntr; \
116 …const pid_t pid = atomic_cmpxchg(&dev_priv->mksstat_kern_pids[_##kern_cntr.slot], current->pid, MK…
117 …dev_priv->mksstat_kern_top_timer[_##kern_cntr.slot] = _##kern_cntr.old_top; …
123 …BUG_ON(!dev_priv->mksstat_kern_pages[_##kern_cntr.slot]); …
125 …pstat = vmw_mksstat_get_kern_pstat(page_address(dev_priv->mksstat_kern_pages[_##kern_cntr.slot]));…
134 …atomic_set(&dev_priv->mksstat_kern_pids[_##kern_cntr.slot], current->pid); …
H A Dvmwgfx_system_manager.c60 int vmw_sys_man_init(struct vmw_private *dev_priv) in vmw_sys_man_init() argument
62 struct ttm_device *bdev = &dev_priv->bdev; in vmw_sys_man_init()
78 void vmw_sys_man_fini(struct vmw_private *dev_priv) in vmw_sys_man_fini() argument
80 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, in vmw_sys_man_fini()
83 ttm_resource_manager_evict_all(&dev_priv->bdev, man); in vmw_sys_man_fini()
88 ttm_set_driver_manager(&dev_priv->bdev, VMW_PL_SYSTEM, NULL); in vmw_sys_man_fini()
/linux/drivers/gpu/drm/gma500/
H A Dpower.c48 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_power_init() local
51 dev_priv->apm_base = dev_priv->apm_reg & 0xffff; in gma_power_init()
52 dev_priv->ospm_base &= 0xffff; in gma_power_init()
54 if (dev_priv->ops->init_pm) in gma_power_init()
55 dev_priv->ops->init_pm(dev); in gma_power_init()
70 dev_priv->pm_initialized = true; in gma_power_init()
81 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_power_uninit() local
83 if (!dev_priv->pm_initialized) in gma_power_uninit()
97 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_suspend_display() local
99 dev_priv->ops->save_regs(dev); in gma_suspend_display()
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H A Dgtt.c128 static int psb_gtt_enable(struct drm_psb_private *dev_priv) in psb_gtt_enable() argument
130 struct drm_device *dev = &dev_priv->dev; in psb_gtt_enable()
134 ret = pci_read_config_word(pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl); in psb_gtt_enable()
137 ret = pci_write_config_word(pdev, PSB_GMCH_CTRL, dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED); in psb_gtt_enable()
141 dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL); in psb_gtt_enable()
142 PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL); in psb_gtt_enable()
149 static void psb_gtt_disable(struct drm_psb_private *dev_priv) in psb_gtt_disable() argument
151 struct drm_device *dev = &dev_priv->dev; in psb_gtt_disable()
154 pci_write_config_word(pdev, PSB_GMCH_CTRL, dev_priv->gmch_ctrl); in psb_gtt_disable()
155 PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL); in psb_gtt_disable()
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H A Doaktrail_device.c22 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in oaktrail_output_init() local
23 if (dev_priv->iLVDS_enable) in oaktrail_output_init()
24 oaktrail_lvds_init(dev, &dev_priv->mode_dev); in oaktrail_output_init()
27 if (dev_priv->hdmi_priv) in oaktrail_output_init()
28 oaktrail_hdmi_init(dev, &dev_priv->mode_dev); in oaktrail_output_init()
47 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in oaktrail_set_brightness() local
59 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1; in oaktrail_set_brightness()
65 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2; in oaktrail_set_brightness()
77 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in oaktrail_backlight_init() local
83 dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX; in oaktrail_backlight_init()
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H A Dframebuffer.c128 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_setup_outputs() local
135 if (!dev_priv->backlight_property) in psb_setup_outputs()
136 dev_priv->backlight_property = drm_property_create_range(dev, 0, in psb_setup_outputs()
138 dev_priv->ops->output_init(dev); in psb_setup_outputs()
153 crtc_mask = dev_priv->ops->sdvo_mask; in psb_setup_outputs()
157 crtc_mask = dev_priv->ops->lvds_mask; in psb_setup_outputs()
169 crtc_mask = dev_priv->ops->hdmi_mask; in psb_setup_outputs()
189 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_modeset_init() local
190 struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev; in psb_modeset_init()
202 for (i = 0; i < dev_priv->num_pipe; i++) in psb_modeset_init()
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H A Dgma_device.c18 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_get_core_freq() local
29 dev_priv->core_freq = 100; in gma_get_core_freq()
32 dev_priv->core_freq = 133; in gma_get_core_freq()
35 dev_priv->core_freq = 150; in gma_get_core_freq()
38 dev_priv->core_freq = 178; in gma_get_core_freq()
41 dev_priv->core_freq = 200; in gma_get_core_freq()
46 dev_priv->core_freq = 266; in gma_get_core_freq()
49 dev_priv->core_freq = 0; in gma_get_core_freq()
H A Dpsb_device.c20 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_output_init() local
21 psb_intel_lvds_init(dev, &dev_priv->mode_dev); in psb_output_init()
43 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_backlight_setup() local
52 if (!dev_priv->lvds_bl) { in psb_backlight_setup()
56 bl_max_freq = dev_priv->lvds_bl->freq; in psb_backlight_setup()
59 core_clock = dev_priv->core_freq; in psb_backlight_setup()
87 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_init_pm() local
105 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_save_display_registers() local
110 struct psb_state *regs = &dev_priv->regs.psb; in psb_save_display_registers()
126 dev_priv->ops->save_crtc(crtc); in psb_save_display_registers()
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H A Dpsb_drv.h650 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in REGISTER_READ() local
651 return ioread32(dev_priv->vdc_reg + reg); in REGISTER_READ()
656 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in REGISTER_READ_AUX() local
657 return ioread32(dev_priv->aux_reg + reg); in REGISTER_READ_AUX()
682 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in REGISTER_WRITE() local
683 iowrite32((val), dev_priv->vdc_reg + (reg)); in REGISTER_WRITE()
689 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in REGISTER_WRITE_AUX() local
690 iowrite32((val), dev_priv->aux_reg + (reg)); in REGISTER_WRITE_AUX()
710 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in REGISTER_WRITE16() local
711 iowrite16((val), dev_priv->vdc_reg + (reg)); in REGISTER_WRITE16()
[all …]
/linux/drivers/gpu/drm/i915/
H A Dintel_gvt.h40 int intel_gvt_init(struct drm_i915_private *dev_priv);
41 void intel_gvt_driver_remove(struct drm_i915_private *dev_priv);
43 void intel_gvt_resume(struct drm_i915_private *dev_priv);
47 int (*init_device)(struct drm_i915_private *dev_priv);
48 void (*clean_device)(struct drm_i915_private *dev_priv);
56 static inline int intel_gvt_init(struct drm_i915_private *dev_priv) in intel_gvt_init() argument
61 static inline void intel_gvt_driver_remove(struct drm_i915_private *dev_priv) in intel_gvt_driver_remove() argument
65 static inline void intel_gvt_resume(struct drm_i915_private *dev_priv) in intel_gvt_resume() argument

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