Searched refs:dcn_reg_offsets (Results 1 – 13 of 13) sorted by relevance
11 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
117 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]206 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)1149 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
99 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]194 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)1160 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
122 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]212 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)1174 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS, in read_dce_straps()
1379 uint32_t *dcn_reg_offsets; member2058 uint32_t *dcn_reg_offsets; member
106 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]211 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
113 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]210 (ctx->dcn_reg_offsets[reg##reg_name##_BASE_IDX] + reg##reg_name)
178 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]271 (ctx->dcn_reg_offsets[reg##reg_name##_BASE_IDX] + reg##reg_name)
1004 dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets; in dc_construct_ctx()1600 dc->dcn_reg_offsets = init_params->dcn_reg_offsets; in dc_create()
116 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
131 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
111 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
580 init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; in amdgpu_dm_init()