1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dm_services.h"
6 #include "dc.h"
7
8 #include "dcn32/dcn32_init.h"
9 #include "dcn401/dcn401_init.h"
10
11 #include "resource.h"
12 #include "include/irq_service_interface.h"
13 #include "basics/conversion.h"
14 #include "dcn401_resource.h"
15
16 #include "dcn20/dcn20_resource.h"
17 #include "dcn30/dcn30_resource.h"
18 #include "dcn32/dcn32_resource.h"
19 #include "dcn321/dcn321_resource.h"
20 #include "dcn35/dcn35_resource.h"
21
22 #include "dcn10/dcn10_ipp.h"
23 #include "dcn401/dcn401_hubbub.h"
24 #include "dcn401/dcn401_mpc.h"
25 #include "dcn401/dcn401_hubp.h"
26 #include "dio/dcn10/dcn10_dio.h"
27 #include "irq/dcn401/irq_service_dcn401.h"
28 #include "dcn401/dcn401_dpp.h"
29 #include "dcn401/dcn401_optc.h"
30 #include "dcn20/dcn20_hwseq.h"
31 #include "dcn30/dcn30_hwseq.h"
32 #include "dce110/dce110_hwseq.h"
33 #include "dcn20/dcn20_opp.h"
34 #include "dcn401/dcn401_dsc.h"
35 #include "dcn30/dcn30_vpg.h"
36 #include "dcn31/dcn31_vpg.h"
37 #include "dcn30/dcn30_afmt.h"
38 #include "dcn30/dcn30_dio_stream_encoder.h"
39 #include "dcn401/dcn401_dio_stream_encoder.h"
40 #include "dcn401/dcn401_hpo_frl_stream_encoder.h"
41 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
42 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
43 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
44 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
45 #include "dcn31/dcn31_apg.h"
46 #include "dcn31/dcn31_dio_link_encoder.h"
47 #include "dcn401/dcn401_dio_link_encoder.h"
48 #include "dcn10/dcn10_link_encoder.h"
49 #include "dcn321/dcn321_dio_link_encoder.h"
50 #include "dce/dce_clock_source.h"
51 #include "dce/dce_audio.h"
52 #include "dce/dce_hwseq.h"
53 #include "clk_mgr.h"
54 #include "dio/virtual/virtual_stream_encoder.h"
55 #include "dml/display_mode_vba.h"
56 #include "dcn401/dcn401_dccg.h"
57 #include "dcn10/dcn10_resource.h"
58 #include "link_service.h"
59 #include "link_enc_cfg.h"
60 #include "dcn31/dcn31_panel_cntl.h"
61
62 #include "dcn30/dcn30_dwb.h"
63 #include "dcn401/dcn401_mmhubbub.h"
64
65 #include "dcn/dcn_4_1_0_offset.h"
66 #include "dcn/dcn_4_1_0_sh_mask.h"
67 #include "nbif/nbif_6_3_1_offset.h"
68
69 #include "reg_helper.h"
70 #include "dce/dmub_abm.h"
71 #include "dce/dmub_psr.h"
72 #include "dce/dce_aux.h"
73 #include "dce/dce_i2c.h"
74
75 #include "dml/dcn30/display_mode_vba_30.h"
76 #include "vm_helper.h"
77 #include "dcn20/dcn20_vmid.h"
78
79 #include "dc_state_priv.h"
80
81 #include "dml2_0/dml2_wrapper.h"
82
83 #define DC_LOGGER_INIT(logger)
84
85 enum dcn401_clk_src_array_id {
86 DCN401_CLK_SRC_PLL0,
87 DCN401_CLK_SRC_PLL1,
88 DCN401_CLK_SRC_PLL2,
89 DCN401_CLK_SRC_PLL3,
90 //DCN401_CLK_SRC_PLL4,
91 DCN401_CLK_SRC_TOTAL
92 };
93
94 /* begin *********************
95 * macros to expend register list macro defined in HW object header file
96 */
97
98 /* DCN */
99 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
100
101 #define BASE(seg) BASE_INNER(seg)
102
103 #define SR(reg_name)\
104 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
105 reg ## reg_name
106 #define SR_ARR(reg_name, id)\
107 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
108 reg ## reg_name
109 #define SR_ARR_INIT(reg_name, id, value)\
110 REG_STRUCT[id].reg_name = value
111
112 #define SRI(reg_name, block, id)\
113 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
114 reg ## block ## id ## _ ## reg_name
115
116 #define SRI_ARR(reg_name, block, id)\
117 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
118 reg ## block ## id ## _ ## reg_name
119
120 /*
121 * Used when a reg_name would otherwise begin with an integer
122 */
123 #define SRI_ARR_US(reg_name, block, id)\
124 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \
125 reg ## block ## id ## reg_name
126 #define SR_ARR_I2C(reg_name, id) \
127 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
128
129 #define SRI_ARR_I2C(reg_name, block, id)\
130 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
131 reg ## block ## id ## _ ## reg_name
132
133 #define SRI_ARR_DME(reg_name, block, id, offset)\
134 REG_STRUCT[id - offset].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
135 reg ## block ## id ## _ ## reg_name
136
137 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
138 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
139 reg ## block ## id ## _ ## reg_name
140
141 #define SRI2(reg_name, block, id)\
142 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
143 reg ## reg_name
144 #define SRI2_ARR(reg_name, block, id)\
145 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
146 reg ## reg_name
147
148 #define SRIR(var_name, reg_name, block, id)\
149 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 reg ## block ## id ## _ ## reg_name
151
152 #define SRII(reg_name, block, id)\
153 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## reg_name
155
156 #define SRII_ARR_2(reg_name, block, id, inst)\
157 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 reg ## block ## id ## _ ## reg_name
159
160 #define SRII_MPC_RMU(reg_name, block, id)\
161 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
163
164 #define SRII_DWB(reg_name, temp_name, block, id)\
165 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
166 reg ## block ## id ## _ ## temp_name
167
168 #define DCCG_SRII(reg_name, block, id)\
169 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
170 reg ## block ## id ## _ ## reg_name
171
172 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
173 .field_name = reg_name ## __ ## field_name ## post_fix
174
175 #define VUPDATE_SRII(reg_name, block, id)\
176 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
177 reg ## reg_name ## _ ## block ## id
178
179 /* NBIO */
180 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
181
182 #define NBIO_BASE(seg) \
183 NBIO_BASE_INNER(seg)
184
185 #define NBIO_SR(reg_name)\
186 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
187 regBIF_BX0_ ## reg_name
188 #define NBIO_SR_ARR(reg_name, id)\
189 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
190 regBIF_BX0_ ## reg_name
191
192 #define CTX ctx
193 #define REG(reg_name) \
194 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
195
196 static struct bios_registers bios_regs;
197
198 #define bios_regs_init() \
199 NBIO_SR(BIOS_SCRATCH_3),\
200 NBIO_SR(BIOS_SCRATCH_6)
201
202 #define clk_src_regs_init(index, pllid)\
203 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
204
205 static struct dce110_clk_src_regs clk_src_regs[5];
206
207 static const struct dce110_clk_src_shift cs_shift = {
208 CS_COMMON_MASK_SH_LIST_DCN4_0_1(__SHIFT)
209 };
210
211 static const struct dce110_clk_src_mask cs_mask = {
212 CS_COMMON_MASK_SH_LIST_DCN4_0_1(_MASK)
213 };
214
215 #define abm_regs_init(id)\
216 ABM_DCN401_REG_LIST_RI(id)
217
218 static struct dce_abm_registers abm_regs[4];
219
220 static const struct dce_abm_shift abm_shift = {
221 ABM_MASK_SH_LIST_DCN401(__SHIFT)
222 };
223
224 static const struct dce_abm_mask abm_mask = {
225 ABM_MASK_SH_LIST_DCN401(_MASK)
226 };
227
228 #define audio_regs_init(id)\
229 AUD_COMMON_REG_LIST_RI(id)
230
231 static struct dce_audio_registers audio_regs[5];
232
233 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
234 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
235 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
236 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
237
238 static const struct dce_audio_shift audio_shift = {
239 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
240 };
241
242 static const struct dce_audio_mask audio_mask = {
243 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
244 };
245
246 #define vpg_regs_init(id)\
247 VPG_DCN401_REG_LIST_RI(id)
248
249 static struct dcn31_vpg_registers vpg_regs[9];
250
251 static const struct dcn31_vpg_shift vpg_shift = {
252 DCN31_VPG_MASK_SH_LIST(__SHIFT)
253 };
254
255 static const struct dcn31_vpg_mask vpg_mask = {
256 DCN31_VPG_MASK_SH_LIST(_MASK)
257 };
258
259 #define afmt_regs_init(id)\
260 AFMT_DCN3_REG_LIST_RI(id)
261
262 static struct dcn30_afmt_registers afmt_regs[5];
263
264 static const struct dcn30_afmt_shift afmt_shift = {
265 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
266 };
267
268 static const struct dcn30_afmt_mask afmt_mask = {
269 DCN3_AFMT_MASK_SH_LIST(_MASK)
270 };
271
272 #define apg_regs_init(id)\
273 APG_DCN31_REG_LIST_RI(id)
274
275 static struct dcn31_apg_registers apg_regs[4];
276
277 static const struct dcn31_apg_shift apg_shift = {
278 DCN31_APG_MASK_SH_LIST(__SHIFT)
279 };
280
281 static const struct dcn31_apg_mask apg_mask = {
282 DCN31_APG_MASK_SH_LIST(_MASK)
283 };
284
285 #define stream_enc_regs_init(id)\
286 SE_DCN4_01_REG_LIST_RI(id)
287
288 static struct dcn10_stream_enc_registers stream_enc_regs[4];
289
290 static const struct dcn10_stream_encoder_shift se_shift = {
291 SE_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
292 };
293
294 static const struct dcn10_stream_encoder_mask se_mask = {
295 SE_COMMON_MASK_SH_LIST_DCN401(_MASK)
296 };
297
298 #define aux_regs_init(id)\
299 DCN2_AUX_REG_LIST_RI(id)
300
301 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
302
303 #define hpd_regs_init(id)\
304 HPD_REG_LIST_RI(id)
305
306 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
307
308 #define link_regs_init(id, phyid) \
309 LE_DCN401_REG_LIST_RI(id), \
310 LE_DCN60_REG_LIST_RI(id)
311
312 static struct dcn10_link_enc_registers link_enc_regs[4];
313
314
315 static const struct dcn10_link_enc_shift le_shift = {
316 LINK_ENCODER_MASK_SH_LIST_DCN401(__SHIFT), \
317 LINK_ENCODER_MASK_SH_LIST_DCN60_ON_DCN401(__SHIFT)
318 };
319
320 static const struct dcn10_link_enc_mask le_mask = {
321 LINK_ENCODER_MASK_SH_LIST_DCN401(_MASK), \
322 LINK_ENCODER_MASK_SH_LIST_DCN60_ON_DCN401(_MASK)
323 };
324
325
326 #define hpo_frl_stream_encoder_reg_list(id)\
327 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id)
328
329 #define hpo_frl_stream_encoder_dme_reg_list(id)\
330 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST_RI(id, 4)
331
332 static struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[2];
333
334 static const struct dcn401_hpo_frl_stream_encoder_shift hpo_se_shift = {
335 DCN401_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT)
336 };
337
338 static const struct dcn401_hpo_frl_stream_encoder_mask hpo_se_mask = {
339 DCN401_HPO_STREAM_ENC_MASK_SH_LIST(_MASK)
340 };
341
342 #define hpo_frl_link_encoder_reg_list(id)\
343 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST_RI(id)
344
345 static struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[1];
346
347 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
348 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
349 };
350
351 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
352 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
353 };
354
355 #define hpo_dp_stream_encoder_reg_init(id)\
356 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
357
358 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
359
360 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
361 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
362 };
363
364 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
365 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
366 };
367
368
369 #define hpo_dp_link_encoder_reg_init(id)\
370 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
371 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
372 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
373 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
374 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
375
376 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4];
377
378 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
379 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
380 };
381
382 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
383 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
384 };
385
386 #define dpp_regs_init(id)\
387 DPP_REG_LIST_DCN401_COMMON_RI(id)
388
389 static struct dcn401_dpp_registers dpp_regs[4];
390
391 static const struct dcn401_dpp_shift tf_shift = {
392 DPP_REG_LIST_SH_MASK_DCN401_COMMON(__SHIFT)
393 };
394
395 static const struct dcn401_dpp_mask tf_mask = {
396 DPP_REG_LIST_SH_MASK_DCN401_COMMON(_MASK)
397 };
398
399 #define opp_regs_init(id)\
400 OPP_REG_LIST_DCN401_RI(id)
401
402 static struct dcn20_opp_registers opp_regs[4];
403
404 static const struct dcn20_opp_shift opp_shift = {
405 OPP_MASK_SH_LIST_DCN20(__SHIFT)
406 };
407
408 static const struct dcn20_opp_mask opp_mask = {
409 OPP_MASK_SH_LIST_DCN20(_MASK)
410 };
411
412 #define aux_engine_regs_init(id) \
413 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
414 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
415 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
416 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)
417
418 static struct dce110_aux_registers aux_engine_regs[5];
419
420 static const struct dce110_aux_registers_shift aux_shift = {
421 DCN_AUX_MASK_SH_LIST(__SHIFT)
422 };
423
424 static const struct dce110_aux_registers_mask aux_mask = {
425 DCN_AUX_MASK_SH_LIST(_MASK)
426 };
427
428 #define dwbc_regs_dcn401_init(id)\
429 DWBC_COMMON_REG_LIST_DCN30_RI(id)
430
431 static struct dcn30_dwbc_registers dwbc401_regs[1];
432
433 static const struct dcn30_dwbc_shift dwbc401_shift = {
434 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
435 };
436
437 static const struct dcn30_dwbc_mask dwbc401_mask = {
438 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
439 };
440
441
442 #define mcif_wb_regs_dcn401_init(id) \
443 MCIF_WB_COMMON_REG_LIST_DCN4_01_RI(id)
444
445 static struct dcn35_mmhubbub_registers mcif_wb401_regs[1];
446
447 static const struct dcn401_mmhubbub_shift mcif_wb401_shift = {
448 MCIF_WB_COMMON_MASK_SH_LIST_DCN4_01(__SHIFT)
449 };
450
451 static const struct dcn401_mmhubbub_mask mcif_wb401_mask = {
452 MCIF_WB_COMMON_MASK_SH_LIST_DCN4_01(_MASK)
453 };
454
455 #define dsc_regs_init(id)\
456 DSC_REG_LIST_DCN401_RI(id)
457
458 static struct dcn401_dsc_registers dsc_regs[4];
459
460 static const struct dcn401_dsc_shift dsc_shift = {
461 DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)
462 };
463
464 static const struct dcn401_dsc_mask dsc_mask = {
465 DSC_REG_LIST_SH_MASK_DCN401(_MASK)
466 };
467
468 static struct dcn401_mpc_registers mpc_regs;
469
470 #define dcn_mpc_regs_init()\
471 MPC_REG_LIST_DCN4_01_RI(0),\
472 MPC_REG_LIST_DCN4_01_RI(1),\
473 MPC_REG_LIST_DCN4_01_RI(2),\
474 MPC_REG_LIST_DCN4_01_RI(3),\
475 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
476 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
477 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
478 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
479 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
480
481 static const struct dcn401_mpc_shift mpc_shift = {
482 MPC_COMMON_MASK_SH_LIST_DCN4_01(__SHIFT)
483 };
484
485 static const struct dcn401_mpc_mask mpc_mask = {
486 MPC_COMMON_MASK_SH_LIST_DCN4_01(_MASK)
487 };
488
489 #define optc_regs_init(id)\
490 OPTC_COMMON_REG_LIST_DCN401_RI(id)
491
492 static struct dcn_optc_registers optc_regs[4];
493
494 static const struct dcn_optc_shift optc_shift = {
495 OPTC_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
496 };
497
498 static const struct dcn_optc_mask optc_mask = {
499 OPTC_COMMON_MASK_SH_LIST_DCN401(_MASK)
500 };
501
502 #define hubp_regs_init(id)\
503 HUBP_REG_LIST_DCN401_RI(id)
504
505 static struct dcn_hubp2_registers hubp_regs[4];
506
507 static const struct dcn_hubp2_shift hubp_shift = {
508 HUBP_MASK_SH_LIST_DCN401(__SHIFT)
509 };
510
511 static const struct dcn_hubp2_mask hubp_mask = {
512 HUBP_MASK_SH_LIST_DCN401(_MASK)
513 };
514
515 static struct dcn_hubbub_registers hubbub_reg;
516 #define hubbub_reg_init()\
517 HUBBUB_REG_LIST_DCN4_01_RI(0)
518
519 static const struct dcn_hubbub_shift hubbub_shift = {
520 HUBBUB_MASK_SH_LIST_DCN4_01(__SHIFT)
521 };
522
523 static const struct dcn_hubbub_mask hubbub_mask = {
524 HUBBUB_MASK_SH_LIST_DCN4_01(_MASK)
525 };
526
527 static struct dccg_registers dccg_regs;
528
529 #define dccg_regs_init()\
530 DCCG_REG_LIST_DCN401_RI()
531
532 static const struct dccg_shift dccg_shift = {
533 DCCG_MASK_SH_LIST_DCN401(__SHIFT)
534 };
535
536 static const struct dccg_mask dccg_mask = {
537 DCCG_MASK_SH_LIST_DCN401(_MASK)
538 };
539
540 #define SRII2(reg_name_pre, reg_name_post, id)\
541 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
542 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
543 reg ## reg_name_pre ## id ## _ ## reg_name_post
544
545
546 #define HWSEQ_DCN401_REG_LIST()\
547 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
548 SR(DIO_MEM_PWR_CTRL), \
549 SR(ODM_MEM_PWR_CTRL3), \
550 SR(MMHUBBUB_MEM_PWR_CNTL), \
551 SR(DCCG_GATE_DISABLE_CNTL), \
552 SR(DCCG_GATE_DISABLE_CNTL2), \
553 SR(DCFCLK_CNTL),\
554 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
555 SRII(PIXEL_RATE_CNTL, OTG, 0), \
556 SRII(PIXEL_RATE_CNTL, OTG, 1),\
557 SRII(PIXEL_RATE_CNTL, OTG, 2),\
558 SRII(PIXEL_RATE_CNTL, OTG, 3),\
559 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
560 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
561 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
562 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
563 SR(MICROSECOND_TIME_BASE_DIV), \
564 SR(MILLISECOND_TIME_BASE_DIV), \
565 SR(DISPCLK_FREQ_CHANGE_CNTL), \
566 SR(RBBMIF_TIMEOUT_DIS), \
567 SR(RBBMIF_TIMEOUT_DIS_2), \
568 SR(DCHUBBUB_CRC_CTRL), \
569 SR(DPP_TOP0_DPP_CRC_CTRL), \
570 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
571 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
572 SR(MPC_CRC_CTRL), \
573 SR(MPC_CRC_RESULT_GB), \
574 SR(MPC_CRC_RESULT_C), \
575 SR(MPC_CRC_RESULT_AR), \
576 SR(DOMAIN0_PG_CONFIG), \
577 SR(DOMAIN1_PG_CONFIG), \
578 SR(DOMAIN2_PG_CONFIG), \
579 SR(DOMAIN3_PG_CONFIG), \
580 SR(DOMAIN16_PG_CONFIG), \
581 SR(DOMAIN17_PG_CONFIG), \
582 SR(DOMAIN18_PG_CONFIG), \
583 SR(DOMAIN19_PG_CONFIG), \
584 SR(DOMAIN22_PG_CONFIG), \
585 SR(DOMAIN23_PG_CONFIG), \
586 SR(DOMAIN24_PG_CONFIG), \
587 SR(DOMAIN25_PG_CONFIG), \
588 SR(DOMAIN0_PG_STATUS), \
589 SR(DOMAIN1_PG_STATUS), \
590 SR(DOMAIN2_PG_STATUS), \
591 SR(DOMAIN3_PG_STATUS), \
592 SR(DOMAIN16_PG_STATUS), \
593 SR(DOMAIN17_PG_STATUS), \
594 SR(DOMAIN18_PG_STATUS), \
595 SR(DOMAIN19_PG_STATUS), \
596 SR(DOMAIN22_PG_STATUS), \
597 SR(DOMAIN23_PG_STATUS), \
598 SR(DOMAIN24_PG_STATUS), \
599 SR(DOMAIN25_PG_STATUS), \
600 SR(DC_IP_REQUEST_CNTL), \
601 SR(AZALIA_AUDIO_DTO), \
602 SR(HPO_TOP_HW_CONTROL),\
603 SR(AZALIA_CONTROLLER_CLOCK_GATING)
604
605 static struct dce_hwseq_registers hwseq_reg;
606
607 #define HWSEQ_DCN60_REG_LIST() \
608 SR(HDCP_INTERRUPT_DEST)
609
610 #define hwseq_reg_init() \
611 HWSEQ_DCN401_REG_LIST(), \
612 HWSEQ_DCN60_REG_LIST()
613
614 #define HWSEQ_DCN401_MASK_SH_LIST(mask_sh)\
615 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
616 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
617 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
618 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
619 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
620 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
621 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
622 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
623 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
624 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
625 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
626 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
627 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
628 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
629 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
630 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
631 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
632 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
633 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
634 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
635 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
636 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
637 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
638 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
639 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
640 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
641 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
642 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
643 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
644 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
645 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
646 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
647 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
648 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
649 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
650 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
651 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
652 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
653 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
654 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
655 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
656 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \
657 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
658 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh)
659
660 #define HWSEQ_DCN60_MASK_SH_LIST(mask_sh) \
661 HWS_SF(, HDCP_INTERRUPT_DEST, DOUT_IHC_HDCP0_I2C_XFER_REQ_INTERRUPT_DEST, mask_sh), \
662 HWS_SF(, HDCP_INTERRUPT_DEST, DOUT_IHC_HDCP1_I2C_XFER_REQ_INTERRUPT_DEST, mask_sh), \
663 HWS_SF(, HDCP_INTERRUPT_DEST, DOUT_IHC_HDCP2_I2C_XFER_REQ_INTERRUPT_DEST, mask_sh), \
664 HWS_SF(, HDCP_INTERRUPT_DEST, DOUT_IHC_HDCP3_I2C_XFER_REQ_INTERRUPT_DEST, mask_sh)
665
666 static const struct dce_hwseq_shift hwseq_shift = {
667 HWSEQ_DCN401_MASK_SH_LIST(__SHIFT), \
668 HWSEQ_DCN60_MASK_SH_LIST(__SHIFT)
669 };
670
671 static const struct dce_hwseq_mask hwseq_mask = {
672 HWSEQ_DCN401_MASK_SH_LIST(_MASK), \
673 HWSEQ_DCN60_MASK_SH_LIST(_MASK)
674 };
675
676 #define vmid_regs_init(id)\
677 DCN20_VMID_REG_LIST_RI(id)
678
679 static struct dcn_vmid_registers vmid_regs[16];
680
681 static const struct dcn20_vmid_shift vmid_shifts = {
682 DCN20_VMID_MASK_SH_LIST(__SHIFT)
683 };
684
685 static const struct dcn20_vmid_mask vmid_masks = {
686 DCN20_VMID_MASK_SH_LIST(_MASK)
687 };
688
689 #define dio_regs_init() \
690 DIO_REG_LIST_DCN10()
691
692 static struct dcn_dio_registers dio_regs;
693
694 #define DIO_MASK_SH_LIST_DCN401(mask_sh)\
695 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
696
697 static const struct dcn_dio_shift dio_shift = {
698 DIO_MASK_SH_LIST_DCN401(__SHIFT)
699 };
700
701 static const struct dcn_dio_mask dio_mask = {
702 DIO_MASK_SH_LIST_DCN401(_MASK)
703 };
704
705 static const struct resource_caps res_cap_dcn4_01 = {
706 .num_timing_generator = 4,
707 .num_opp = 4,
708 .num_video_plane = 4,
709 .num_audio = 4,
710 .num_stream_encoder = 4,
711 .num_hpo_frl = 1,
712 .num_hpo_dp_stream_encoder = 4,
713 .num_hpo_dp_link_encoder = 4,
714 .num_pll = 4,
715 .num_dwb = 1,
716 .num_ddc = 4,
717 .num_vmid = 16,
718 .num_mpc_3dlut = 4,
719 .num_dsc = 4,
720 };
721
722 static const struct dc_plane_cap plane_cap = {
723 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
724 .per_pixel_alpha = true,
725
726 .pixel_format_support = {
727 .argb8888 = true,
728 .nv12 = true,
729 .fp16 = true,
730 .p010 = true,
731 .ayuv = false,
732 },
733
734 .max_upscale_factor = {
735 .argb8888 = 16000,
736 .nv12 = 16000,
737 .fp16 = 16000
738 },
739
740 // 6:1 downscaling ratio: 1000/6 = 166.666
741 .max_downscale_factor = {
742 .argb8888 = 167,
743 .nv12 = 167,
744 .fp16 = 167
745 },
746 64,
747 64
748 };
749
750 static const struct dc_debug_options debug_defaults_drv = {
751 .limit_ffe = 3,
752 .disable_dmcu = true,
753 .force_abm_enable = false,
754 .clock_trace = true,
755 .disable_pplib_clock_request = false,
756 .pipe_split_policy = MPC_SPLIT_AVOID,
757 .force_single_disp_pipe_split = false,
758 .disable_dcc = DCC_ENABLE,
759 .vsr_support = true,
760 .performance_trace = false,
761 .max_downscale_src_width = 7680,/*upto 8K*/
762 .disable_pplib_wm_range = false,
763 .scl_reset_length10 = true,
764 .sanity_checks = false,
765 .underflow_assert_delay_us = 0xFFFFFFFF,
766 .dwb_fi_phase = -1, // -1 = disable,
767 .dmub_command_table = true,
768 .enable_mem_low_power = {
769 .bits = {
770 .vga = false,
771 .i2c = false,
772 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
773 .dscl = false,
774 .cm = false,
775 .mpc = false,
776 .optc = true,
777 }
778 },
779 .use_max_lb = true,
780 .force_disable_subvp = false,
781 .disable_force_pstate_allow_on_hw_release = false,
782 .exit_idle_opt_for_cursor_updates = true,
783 .using_dml2 = true,
784 .using_dml21 = true,
785 .enable_single_display_2to1_odm_policy = true,
786
787 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
788 .enable_double_buffered_dsc_pg_support = true,
789 .enable_dp_dig_pixel_rate_div_policy = 1,
790 .allow_sw_cursor_fallback = false,
791 .alloc_extra_way_for_cursor = true,
792 .min_prefetch_in_strobe_ns = 60000, // 60us
793 .disable_unbounded_requesting = false,
794 .dcc_meta_propagation_delay_us = 10,
795 .fams_version = {
796 .minor = 1,
797 .major = 2,
798 }, //v2.1
799 .fams2_config = {
800 .bits = {
801 .enable = true,
802 .enable_offload_flip = true,
803 .enable_stall_recovery = true,
804 }
805 },
806 .force_cositing = CHROMA_COSITING_NONE + 1,
807 };
808
809 static const struct dc_check_config config_defaults = {
810 .enable_legacy_fast_update = false,
811 };
812
dcn401_aux_engine_create(struct dc_context * ctx,uint32_t inst)813 static struct dce_aux *dcn401_aux_engine_create(
814 struct dc_context *ctx,
815 uint32_t inst)
816 {
817 struct aux_engine_dce110 *aux_engine =
818 kzalloc_obj(struct aux_engine_dce110);
819
820 if (!aux_engine)
821 return NULL;
822
823 #undef REG_STRUCT
824 #define REG_STRUCT aux_engine_regs
825 aux_engine_regs_init(0),
826 aux_engine_regs_init(1),
827 aux_engine_regs_init(2),
828 aux_engine_regs_init(3);
829
830 dce110_aux_engine_construct(aux_engine, ctx, inst,
831 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
832 &aux_engine_regs[inst],
833 &aux_mask,
834 &aux_shift,
835 ctx->dc->caps.extended_aux_timeout_support);
836
837 return &aux_engine->base;
838 }
839 #define i2c_inst_regs_init(id)\
840 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
841
842 static struct dce_i2c_registers i2c_hw_regs[5];
843
844 static const struct dce_i2c_shift i2c_shifts = {
845 I2C_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
846 };
847
848 static const struct dce_i2c_mask i2c_masks = {
849 I2C_COMMON_MASK_SH_LIST_DCN401(_MASK)
850 };
851
dcn401_i2c_hw_create(struct dc_context * ctx,uint32_t inst)852 static struct dce_i2c_hw *dcn401_i2c_hw_create(
853 struct dc_context *ctx,
854 uint32_t inst)
855 {
856 struct dce_i2c_hw *dce_i2c_hw =
857 kzalloc_obj(struct dce_i2c_hw);
858
859 if (!dce_i2c_hw)
860 return NULL;
861
862 #undef REG_STRUCT
863 #define REG_STRUCT i2c_hw_regs
864 i2c_inst_regs_init(1),
865 i2c_inst_regs_init(2),
866 i2c_inst_regs_init(3),
867 i2c_inst_regs_init(4);
868
869 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
870 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
871
872 return dce_i2c_hw;
873 }
874
dcn401_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)875 static struct clock_source *dcn401_clock_source_create(
876 struct dc_context *ctx,
877 struct dc_bios *bios,
878 enum clock_source_id id,
879 const struct dce110_clk_src_regs *regs,
880 bool dp_clk_src)
881 {
882 struct dce110_clk_src *clk_src =
883 kzalloc_obj(struct dce110_clk_src);
884
885 if (!clk_src)
886 return NULL;
887
888 if (dcn401_clk_src_construct(clk_src, ctx, bios, id,
889 regs, &cs_shift, &cs_mask)) {
890 clk_src->base.dp_clk_src = dp_clk_src;
891 return &clk_src->base;
892 }
893
894 kfree(clk_src);
895 BREAK_TO_DEBUGGER();
896 return NULL;
897 }
898
dcn401_hubbub_create(struct dc_context * ctx)899 static struct hubbub *dcn401_hubbub_create(struct dc_context *ctx)
900 {
901 int i;
902
903 struct dcn20_hubbub *hubbub2 = kzalloc_obj(struct dcn20_hubbub);
904
905 if (!hubbub2)
906 return NULL;
907
908
909 #undef REG_STRUCT
910 #define REG_STRUCT hubbub_reg
911 hubbub_reg_init();
912
913 #undef REG_STRUCT
914 #define REG_STRUCT vmid_regs
915 vmid_regs_init(0),
916 vmid_regs_init(1),
917 vmid_regs_init(2),
918 vmid_regs_init(3),
919 vmid_regs_init(4),
920 vmid_regs_init(5),
921 vmid_regs_init(6),
922 vmid_regs_init(7),
923 vmid_regs_init(8),
924 vmid_regs_init(9),
925 vmid_regs_init(10),
926 vmid_regs_init(11),
927 vmid_regs_init(12),
928 vmid_regs_init(13),
929 vmid_regs_init(14),
930 vmid_regs_init(15);
931
932 hubbub401_construct(hubbub2, ctx,
933 &hubbub_reg,
934 &hubbub_shift,
935 &hubbub_mask,
936 DCN4_01_DEFAULT_DET_SIZE, //nominal (default) detile buffer size in kbytes,
937 8, //dml2 ip_params_st.pixel_chunk_size_kbytes
938 DCN4_01_CRB_SIZE_KB); //dml2 ip_params_st.config_return_buffer_size_in_kbytes
939
940 for (i = 0; i < res_cap_dcn4_01.num_vmid; i++) {
941 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
942
943 vmid->ctx = ctx;
944
945 vmid->regs = &vmid_regs[i];
946 vmid->shifts = &vmid_shifts;
947 vmid->masks = &vmid_masks;
948 }
949
950 return &hubbub2->base;
951 }
952
dcn401_dio_create(struct dc_context * ctx)953 static struct dio *dcn401_dio_create(struct dc_context *ctx)
954 {
955 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
956
957 if (!dio10)
958 return NULL;
959
960 #undef REG_STRUCT
961 #define REG_STRUCT dio_regs
962 dio_regs_init();
963
964 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
965
966 return &dio10->base;
967 }
968
dcn401_hubp_create(struct dc_context * ctx,uint32_t inst)969 static struct hubp *dcn401_hubp_create(
970 struct dc_context *ctx,
971 uint32_t inst)
972 {
973 struct dcn20_hubp *hubp2 =
974 kzalloc_obj(struct dcn20_hubp);
975
976 if (!hubp2)
977 return NULL;
978
979 #undef REG_STRUCT
980 #define REG_STRUCT hubp_regs
981 hubp_regs_init(0),
982 hubp_regs_init(1),
983 hubp_regs_init(2),
984 hubp_regs_init(3);
985
986 if (hubp401_construct(hubp2, ctx, inst,
987 &hubp_regs[inst], &hubp_shift, &hubp_mask))
988 return &hubp2->base;
989
990 BREAK_TO_DEBUGGER();
991 kfree(hubp2);
992 return NULL;
993 }
994
dcn401_dpp_destroy(struct dpp ** dpp)995 static void dcn401_dpp_destroy(struct dpp **dpp)
996 {
997 kfree(TO_DCN401_DPP(*dpp));
998 *dpp = NULL;
999 }
1000
dcn401_dpp_create(struct dc_context * ctx,uint32_t inst)1001 static struct dpp *dcn401_dpp_create(
1002 struct dc_context *ctx,
1003 uint32_t inst)
1004 {
1005 struct dcn401_dpp *dpp401 =
1006 kzalloc_obj(struct dcn401_dpp);
1007
1008 if (!dpp401)
1009 return NULL;
1010
1011 #undef REG_STRUCT
1012 #define REG_STRUCT dpp_regs
1013 dpp_regs_init(0),
1014 dpp_regs_init(1),
1015 dpp_regs_init(2),
1016 dpp_regs_init(3);
1017
1018 if (dpp401_construct(dpp401, ctx, inst,
1019 &dpp_regs[inst], &tf_shift, &tf_mask))
1020 return &dpp401->base;
1021
1022 BREAK_TO_DEBUGGER();
1023 kfree(dpp401);
1024 return NULL;
1025 }
1026
dcn401_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1027 static struct mpc *dcn401_mpc_create(
1028 struct dc_context *ctx,
1029 int num_mpcc,
1030 int num_rmu)
1031 {
1032 struct dcn401_mpc *mpc401 = kzalloc_obj(struct dcn401_mpc);
1033
1034 if (!mpc401)
1035 return NULL;
1036
1037 #undef REG_STRUCT
1038 #define REG_STRUCT mpc_regs
1039 dcn_mpc_regs_init();
1040
1041 dcn401_mpc_construct(mpc401, ctx,
1042 &mpc_regs,
1043 &mpc_shift,
1044 &mpc_mask,
1045 num_mpcc,
1046 num_rmu);
1047
1048 return &mpc401->base;
1049 }
1050
dcn401_opp_create(struct dc_context * ctx,uint32_t inst)1051 static struct output_pixel_processor *dcn401_opp_create(
1052 struct dc_context *ctx, uint32_t inst)
1053 {
1054 struct dcn20_opp *opp4 =
1055 kzalloc_obj(struct dcn20_opp);
1056
1057 if (!opp4) {
1058 BREAK_TO_DEBUGGER();
1059 return NULL;
1060 }
1061
1062 #undef REG_STRUCT
1063 #define REG_STRUCT opp_regs
1064 opp_regs_init(0),
1065 opp_regs_init(1),
1066 opp_regs_init(2),
1067 opp_regs_init(3);
1068
1069 dcn20_opp_construct(opp4, ctx, inst,
1070 &opp_regs[inst], &opp_shift, &opp_mask);
1071 return &opp4->base;
1072 }
1073
1074
dcn401_timing_generator_create(struct dc_context * ctx,uint32_t instance)1075 static struct timing_generator *dcn401_timing_generator_create(
1076 struct dc_context *ctx,
1077 uint32_t instance)
1078 {
1079 struct optc *tgn10 =
1080 kzalloc_obj(struct optc);
1081
1082 if (!tgn10)
1083 return NULL;
1084 #undef REG_STRUCT
1085 #define REG_STRUCT optc_regs
1086 optc_regs_init(0),
1087 optc_regs_init(1),
1088 optc_regs_init(2),
1089 optc_regs_init(3);
1090
1091 tgn10->base.inst = instance;
1092 tgn10->base.ctx = ctx;
1093
1094 tgn10->tg_regs = &optc_regs[instance];
1095 tgn10->tg_shift = &optc_shift;
1096 tgn10->tg_mask = &optc_mask;
1097
1098 dcn401_timing_generator_init(tgn10);
1099
1100 return &tgn10->base;
1101 }
1102
1103 static const struct encoder_feature_support link_enc_feature = {
1104 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1105 .max_hdmi_pixel_clock = 600000,
1106 .hdmi_ycbcr420_supported = true,
1107 .dp_ycbcr420_supported = true,
1108 .fec_supported = true,
1109 .flags.bits.IS_HBR2_CAPABLE = true,
1110 .flags.bits.IS_HBR3_CAPABLE = true,
1111 .flags.bits.IS_TPS3_CAPABLE = true,
1112 .flags.bits.IS_TPS4_CAPABLE = true
1113 };
1114
dcn401_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1115 static struct link_encoder *dcn401_link_encoder_create(
1116 struct dc_context *ctx,
1117 const struct encoder_init_data *enc_init_data)
1118 {
1119 struct dcn20_link_encoder *enc20 =
1120 kzalloc_obj(struct dcn20_link_encoder);
1121
1122 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1123 return NULL;
1124
1125 #undef REG_STRUCT
1126 #define REG_STRUCT link_enc_aux_regs
1127 aux_regs_init(0),
1128 aux_regs_init(1),
1129 aux_regs_init(2),
1130 aux_regs_init(3);
1131
1132 #undef REG_STRUCT
1133 #define REG_STRUCT link_enc_hpd_regs
1134 hpd_regs_init(0),
1135 hpd_regs_init(1),
1136 hpd_regs_init(2),
1137 hpd_regs_init(3);
1138 #undef REG_STRUCT
1139 #define REG_STRUCT link_enc_regs
1140 link_regs_init(0, A),
1141 link_regs_init(1, B),
1142 link_regs_init(2, C),
1143 link_regs_init(3, D);
1144
1145 dcn401_link_encoder_construct(enc20,
1146 enc_init_data,
1147 &link_enc_feature,
1148 &link_enc_regs[enc_init_data->transmitter],
1149 &link_enc_aux_regs[enc_init_data->channel - 1],
1150 &link_enc_hpd_regs[enc_init_data->hpd_source],
1151 &le_shift,
1152 &le_mask);
1153 return &enc20->enc10.base;
1154 }
1155
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1156 static void read_dce_straps(
1157 struct dc_context *ctx,
1158 struct resource_straps *straps)
1159 {
1160 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1161 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1162
1163 }
1164
dcn401_create_audio(struct dc_context * ctx,unsigned int inst)1165 static struct audio *dcn401_create_audio(
1166 struct dc_context *ctx, unsigned int inst)
1167 {
1168
1169 #undef REG_STRUCT
1170 #define REG_STRUCT audio_regs
1171 audio_regs_init(0),
1172 audio_regs_init(1),
1173 audio_regs_init(2),
1174 audio_regs_init(3),
1175 audio_regs_init(4);
1176
1177 return dce_audio_create(ctx, inst,
1178 &audio_regs[inst], &audio_shift, &audio_mask);
1179 }
1180
dcn401_vpg_create(struct dc_context * ctx,uint32_t inst)1181 static struct vpg *dcn401_vpg_create(
1182 struct dc_context *ctx,
1183 uint32_t inst)
1184 {
1185 struct dcn31_vpg *vpg4 = kzalloc_obj(struct dcn31_vpg);
1186
1187 if (!vpg4)
1188 return NULL;
1189
1190
1191 #undef REG_STRUCT
1192 #define REG_STRUCT vpg_regs
1193 vpg_regs_init(0),
1194 vpg_regs_init(1),
1195 vpg_regs_init(2),
1196 vpg_regs_init(3),
1197 vpg_regs_init(4),
1198 vpg_regs_init(5),
1199 vpg_regs_init(6),
1200 vpg_regs_init(7),
1201 vpg_regs_init(8);
1202
1203 vpg31_construct(vpg4, ctx, inst,
1204 &vpg_regs[inst],
1205 &vpg_shift,
1206 &vpg_mask);
1207
1208 return &vpg4->base;
1209 }
1210
dcn401_afmt_create(struct dc_context * ctx,uint32_t inst)1211 static struct afmt *dcn401_afmt_create(
1212 struct dc_context *ctx,
1213 uint32_t inst)
1214 {
1215 struct dcn30_afmt *afmt401 = kzalloc_obj(struct dcn30_afmt);
1216
1217 if (!afmt401)
1218 return NULL;
1219
1220 #undef REG_STRUCT
1221 #define REG_STRUCT afmt_regs
1222 afmt_regs_init(0),
1223 afmt_regs_init(1),
1224 afmt_regs_init(2),
1225 afmt_regs_init(3),
1226 afmt_regs_init(4);
1227
1228 afmt3_construct(afmt401, ctx, inst,
1229 &afmt_regs[inst],
1230 &afmt_shift,
1231 &afmt_mask);
1232
1233 return &afmt401->base;
1234 }
1235
dcn401_apg_create(struct dc_context * ctx,uint32_t inst)1236 static struct apg *dcn401_apg_create(
1237 struct dc_context *ctx,
1238 uint32_t inst)
1239 {
1240 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1241
1242 if (!apg31)
1243 return NULL;
1244
1245 #undef REG_STRUCT
1246 #define REG_STRUCT apg_regs
1247 apg_regs_init(0),
1248 apg_regs_init(1),
1249 apg_regs_init(2),
1250 apg_regs_init(3);
1251
1252 apg31_construct(apg31, ctx, inst,
1253 &apg_regs[inst],
1254 &apg_shift,
1255 &apg_mask);
1256
1257 return &apg31->base;
1258 }
1259
dcn401_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1260 static struct stream_encoder *dcn401_stream_encoder_create(
1261 enum engine_id eng_id,
1262 struct dc_context *ctx)
1263 {
1264 struct dcn10_stream_encoder *enc1;
1265 struct vpg *vpg;
1266 struct afmt *afmt;
1267 int vpg_inst;
1268 int afmt_inst;
1269
1270 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1271 if (eng_id <= ENGINE_ID_DIGF) {
1272 vpg_inst = eng_id;
1273 afmt_inst = eng_id;
1274 } else
1275 return NULL;
1276
1277 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1278 vpg = dcn401_vpg_create(ctx, vpg_inst);
1279 afmt = dcn401_afmt_create(ctx, afmt_inst);
1280
1281 if (!enc1 || !vpg || !afmt || eng_id >= ARRAY_SIZE(stream_enc_regs)) {
1282 kfree(enc1);
1283 kfree(vpg);
1284 kfree(afmt);
1285 return NULL;
1286 }
1287 #undef REG_STRUCT
1288 #define REG_STRUCT stream_enc_regs
1289 stream_enc_regs_init(0),
1290 stream_enc_regs_init(1),
1291 stream_enc_regs_init(2),
1292 stream_enc_regs_init(3);
1293 //stream_enc_regs_init(4);
1294
1295 dcn401_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1296 eng_id, vpg, afmt,
1297 &stream_enc_regs[eng_id],
1298 &se_shift, &se_mask);
1299 return &enc1->base;
1300 }
1301
dcn401_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1302 static struct hpo_frl_stream_encoder *dcn401_hpo_frl_stream_encoder_create(
1303 enum engine_id eng_id,
1304 struct dc_context *ctx)
1305 {
1306 struct dcn401_hpo_frl_stream_encoder *hpo_enc401;
1307 struct vpg *vpg;
1308 struct afmt *afmt;
1309 int vpg_inst;
1310 int afmt_inst;
1311
1312 #undef REG_STRUCT
1313 #define REG_STRUCT hpo_frl_stream_enc_regs
1314 hpo_frl_stream_encoder_reg_list(0),
1315 hpo_frl_stream_encoder_dme_reg_list(4);
1316
1317 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */
1318 if (eng_id == ENGINE_ID_HPO_0) {
1319 vpg_inst = 4;
1320 afmt_inst = 4;
1321 } else
1322 return NULL;
1323
1324 /* allocate HPO stream encoder and create VPG, AFMT sub-blocks */
1325 hpo_enc401 = kzalloc_obj(struct dcn401_hpo_frl_stream_encoder);
1326 vpg = dcn401_vpg_create(ctx, vpg_inst);
1327 afmt = dcn401_afmt_create(ctx, afmt_inst);
1328
1329 if (!hpo_enc401 || !vpg || !afmt) {
1330 kfree(hpo_enc401);
1331 kfree(vpg);
1332 kfree(afmt);
1333 return NULL;
1334 }
1335
1336 dcn401_hpo_frl_stream_encoder_construct(hpo_enc401, ctx, ctx->dc_bios,
1337 eng_id, vpg, afmt,
1338 &hpo_frl_stream_enc_regs[eng_id-ENGINE_ID_HPO_0],
1339 &hpo_se_shift, &hpo_se_mask);
1340
1341 return &hpo_enc401->base;
1342 }
1343
dcn401_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1344 static struct hpo_frl_link_encoder *dcn401_hpo_frl_link_encoder_create(
1345 enum engine_id eng_id,
1346 struct dc_context *ctx)
1347 {
1348 struct dcn30_hpo_frl_link_encoder *hpo_link_enc;
1349 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
1350
1351 #undef REG_STRUCT
1352 #define REG_STRUCT hpo_frl_link_enc_regs
1353 hpo_frl_link_encoder_reg_list(0);
1354
1355 /* allocate HPO link encoder */
1356 hpo_link_enc = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
1357 if (!hpo_link_enc)
1358 return NULL; /* out of memory */
1359
1360 hpo_frl_link_encoder3_construct(hpo_link_enc, ctx, eng_id-ENGINE_ID_HPO_0,
1361 &hpo_frl_link_enc_regs[eng_id-ENGINE_ID_HPO_0],
1362 &hpo_le_shift, &hpo_le_mask);
1363
1364 return &hpo_link_enc->base;
1365 }
1366
dcn401_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1367 static struct hpo_dp_stream_encoder *dcn401_hpo_dp_stream_encoder_create(
1368 enum engine_id eng_id,
1369 struct dc_context *ctx)
1370 {
1371 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1372 struct vpg *vpg;
1373 struct apg *apg;
1374 uint32_t hpo_dp_inst;
1375 uint32_t vpg_inst;
1376 uint32_t apg_inst;
1377
1378 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1379 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1380
1381 /* Mapping of VPG register blocks to HPO DP block instance:
1382 * VPG[6] -> HPO_DP[0]
1383 * VPG[7] -> HPO_DP[1]
1384 * VPG[8] -> HPO_DP[2]
1385 * VPG[9] -> HPO_DP[3]
1386 */
1387 vpg_inst = hpo_dp_inst + 5;
1388
1389 /* Mapping of APG register blocks to HPO DP block instance:
1390 * APG[0] -> HPO_DP[0]
1391 * APG[1] -> HPO_DP[1]
1392 * APG[2] -> HPO_DP[2]
1393 * APG[3] -> HPO_DP[3]
1394 */
1395 apg_inst = hpo_dp_inst;
1396
1397 /* allocate HPO stream encoder and create VPG sub-block */
1398 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1399 vpg = dcn401_vpg_create(ctx, vpg_inst);
1400 apg = dcn401_apg_create(ctx, apg_inst);
1401
1402 if (!hpo_dp_enc31 || !vpg || !apg) {
1403 kfree(hpo_dp_enc31);
1404 kfree(vpg);
1405 kfree(apg);
1406 return NULL;
1407 }
1408
1409 #undef REG_STRUCT
1410 #define REG_STRUCT hpo_dp_stream_enc_regs
1411 hpo_dp_stream_encoder_reg_init(0),
1412 hpo_dp_stream_encoder_reg_init(1),
1413 hpo_dp_stream_encoder_reg_init(2),
1414 hpo_dp_stream_encoder_reg_init(3);
1415
1416 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1417 hpo_dp_inst, eng_id, vpg, apg,
1418 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1419 &hpo_dp_se_shift, &hpo_dp_se_mask);
1420
1421 return &hpo_dp_enc31->base;
1422 }
1423
dcn401_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1424 static struct hpo_dp_link_encoder *dcn401_hpo_dp_link_encoder_create(
1425 uint8_t inst,
1426 struct dc_context *ctx)
1427 {
1428 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1429
1430 /* allocate HPO link encoder */
1431 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1432 if (!hpo_dp_enc31)
1433 return NULL; /* out of memory */
1434
1435 #undef REG_STRUCT
1436 #define REG_STRUCT hpo_dp_link_enc_regs
1437 hpo_dp_link_encoder_reg_init(0),
1438 hpo_dp_link_encoder_reg_init(1),
1439 hpo_dp_link_encoder_reg_init(2),
1440 hpo_dp_link_encoder_reg_init(3);
1441
1442 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1443 &hpo_dp_link_enc_regs[inst],
1444 &hpo_dp_le_shift, &hpo_dp_le_mask);
1445
1446 return &hpo_dp_enc31->base;
1447 }
1448
dcn401_calc_num_avail_chans_for_mall(struct dc * dc,unsigned int num_chans)1449 static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans)
1450 {
1451 unsigned int num_available_chans = 1;
1452
1453 /* channels for MALL must be a power of 2 */
1454 while (num_chans > 1) {
1455 num_available_chans = (num_available_chans << 1);
1456 num_chans = (num_chans >> 1);
1457 }
1458
1459 /* cannot be odd */
1460 num_available_chans &= ~1;
1461
1462 /* clamp to max available channels for MALL per ASIC */
1463 if (ASICREV_IS_GC_12_0_0_A0(dc->ctx->asic_id.hw_internal_rev)) {
1464 num_available_chans = num_available_chans > 16 ? 16 : num_available_chans;
1465 } else if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) {
1466 num_available_chans = num_available_chans > 8 ? 8 : num_available_chans;
1467 }
1468
1469 return num_available_chans;
1470 }
1471
dcn401_hwseq_create(struct dc_context * ctx)1472 static struct dce_hwseq *dcn401_hwseq_create(
1473 struct dc_context *ctx)
1474 {
1475 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1476
1477 #undef REG_STRUCT
1478 #define REG_STRUCT hwseq_reg
1479 hwseq_reg_init();
1480
1481 if (hws) {
1482 hws->ctx = ctx;
1483 hws->regs = &hwseq_reg;
1484 hws->shifts = &hwseq_shift;
1485 hws->masks = &hwseq_mask;
1486 }
1487
1488 return hws;
1489 }
1490 static const struct resource_create_funcs res_create_funcs = {
1491 .read_dce_straps = read_dce_straps,
1492 .create_audio = dcn401_create_audio,
1493 .create_stream_encoder = dcn401_stream_encoder_create,
1494 .create_hpo_frl_stream_encoder = dcn401_hpo_frl_stream_encoder_create,
1495 .create_hpo_dp_stream_encoder = dcn401_hpo_dp_stream_encoder_create,
1496 .create_hpo_dp_link_encoder = dcn401_hpo_dp_link_encoder_create,
1497 .create_hwseq = dcn401_hwseq_create,
1498 };
1499
dcn401_dsc_destroy(struct display_stream_compressor ** dsc)1500 static void dcn401_dsc_destroy(struct display_stream_compressor **dsc)
1501 {
1502 kfree(container_of(*dsc, struct dcn401_dsc, base));
1503 *dsc = NULL;
1504 }
1505
dcn401_resource_destruct(struct dcn401_resource_pool * pool)1506 static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)
1507 {
1508 unsigned int i;
1509
1510 for (i = 0; i < pool->base.stream_enc_count; i++) {
1511 if (pool->base.stream_enc[i] != NULL) {
1512 if (pool->base.stream_enc[i]->vpg != NULL) {
1513 kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1514 pool->base.stream_enc[i]->vpg = NULL;
1515 }
1516 if (pool->base.stream_enc[i]->afmt != NULL) {
1517 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1518 pool->base.stream_enc[i]->afmt = NULL;
1519 }
1520 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1521 pool->base.stream_enc[i] = NULL;
1522 }
1523 }
1524
1525 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
1526 if (pool->base.hpo_frl_stream_enc[i] != NULL) {
1527 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
1528 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
1529 pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
1530 }
1531 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) {
1532 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt));
1533 pool->base.hpo_frl_stream_enc[i]->afmt = NULL;
1534 }
1535 kfree(DCN401_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
1536 pool->base.hpo_frl_stream_enc[i] = NULL;
1537 }
1538 }
1539
1540 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1541 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1542 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1543 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1544 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1545 }
1546 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1547 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1548 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1549 }
1550 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1551 pool->base.hpo_dp_stream_enc[i] = NULL;
1552 }
1553 }
1554
1555 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1556 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1557 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1558 pool->base.hpo_dp_link_enc[i] = NULL;
1559 }
1560 }
1561
1562 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1563 if (pool->base.dscs[i] != NULL)
1564 dcn401_dsc_destroy(&pool->base.dscs[i]);
1565 }
1566
1567 if (pool->base.mpc != NULL) {
1568 kfree(TO_DCN20_MPC(pool->base.mpc));
1569 pool->base.mpc = NULL;
1570 }
1571 if (pool->base.hubbub != NULL) {
1572 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1573 pool->base.hubbub = NULL;
1574 }
1575 for (i = 0; i < pool->base.pipe_count; i++) {
1576 if (pool->base.dpps[i] != NULL)
1577 dcn401_dpp_destroy(&pool->base.dpps[i]);
1578
1579 if (pool->base.ipps[i] != NULL)
1580 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1581
1582 if (pool->base.hubps[i] != NULL) {
1583 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1584 pool->base.hubps[i] = NULL;
1585 }
1586
1587 if (pool->base.irqs != NULL) {
1588 dal_irq_service_destroy(&pool->base.irqs);
1589 }
1590 }
1591
1592 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1593 if (pool->base.engines[i] != NULL)
1594 dce110_engine_destroy(&pool->base.engines[i]);
1595 if (pool->base.hw_i2cs[i] != NULL) {
1596 kfree(pool->base.hw_i2cs[i]);
1597 pool->base.hw_i2cs[i] = NULL;
1598 }
1599 if (pool->base.sw_i2cs[i] != NULL) {
1600 kfree(pool->base.sw_i2cs[i]);
1601 pool->base.sw_i2cs[i] = NULL;
1602 }
1603 }
1604
1605 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1606 if (pool->base.opps[i] != NULL)
1607 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1608 }
1609
1610 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1611 if (pool->base.timing_generators[i] != NULL) {
1612 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1613 pool->base.timing_generators[i] = NULL;
1614 }
1615 }
1616
1617 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
1618 if (pool->base.dwbc[i] != NULL) {
1619 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1620 pool->base.dwbc[i] = NULL;
1621 }
1622 if (pool->base.mcif_wb[i] != NULL) {
1623 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1624 pool->base.mcif_wb[i] = NULL;
1625 }
1626 }
1627
1628 for (i = 0; i < pool->base.audio_count; i++) {
1629 if (pool->base.audios[i])
1630 dce_aud_destroy(&pool->base.audios[i]);
1631 }
1632
1633 for (i = 0; i < pool->base.clk_src_count; i++) {
1634 if (pool->base.clock_sources[i] != NULL) {
1635 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1636 pool->base.clock_sources[i] = NULL;
1637 }
1638 }
1639
1640 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1641 if (pool->base.mpc_lut[i] != NULL) {
1642 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1643 pool->base.mpc_lut[i] = NULL;
1644 }
1645 if (pool->base.mpc_shaper[i] != NULL) {
1646 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1647 pool->base.mpc_shaper[i] = NULL;
1648 }
1649 }
1650
1651 if (pool->base.dp_clock_source != NULL) {
1652 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1653 pool->base.dp_clock_source = NULL;
1654 }
1655
1656 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1657 if (pool->base.multiple_abms[i] != NULL)
1658 dce_abm_destroy(&pool->base.multiple_abms[i]);
1659 }
1660
1661 if (pool->base.psr != NULL)
1662 dmub_psr_destroy(&pool->base.psr);
1663
1664 if (pool->base.dccg != NULL)
1665 dcn_dccg_destroy(&pool->base.dccg);
1666
1667 if (pool->base.dio != NULL) {
1668 kfree(TO_DCN10_DIO(pool->base.dio));
1669 pool->base.dio = NULL;
1670 }
1671
1672 if (pool->base.oem_device != NULL) {
1673 struct dc *dc = pool->base.oem_device->ctx->dc;
1674
1675 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1676 }
1677 }
1678
1679
dcn401_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1680 static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1681 {
1682 unsigned int i;
1683 uint32_t dwb_count = pool->res_cap->num_dwb;
1684
1685 for (i = 0; i < dwb_count; i++) {
1686 struct dcn30_dwbc *dwbc401 = kzalloc_obj(struct dcn30_dwbc);
1687
1688 if (!dwbc401) {
1689 dm_error("DC: failed to create dwbc401!\n");
1690 return false;
1691 }
1692
1693
1694 #undef REG_STRUCT
1695 #define REG_STRUCT dwbc401_regs
1696 dwbc_regs_dcn401_init(0);
1697
1698 dcn30_dwbc_construct(dwbc401, ctx,
1699 &dwbc401_regs[i],
1700 &dwbc401_shift,
1701 &dwbc401_mask,
1702 i);
1703
1704 pool->dwbc[i] = &dwbc401->base;
1705
1706 }
1707 return true;
1708 }
1709
dcn401_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1710 static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1711 {
1712 unsigned int i;
1713 uint32_t dwb_count = pool->res_cap->num_dwb;
1714
1715 for (i = 0; i < dwb_count; i++) {
1716 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1717
1718 if (!mcif_wb30) {
1719 dm_error("DC: failed to create mcif_wb30!\n");
1720 return false;
1721 }
1722
1723 #undef REG_STRUCT
1724 #define REG_STRUCT mcif_wb401_regs
1725 mcif_wb_regs_dcn401_init(0);
1726
1727 dcn401_mmhubbub_construct(mcif_wb30, ctx,
1728 &mcif_wb401_regs[i],
1729 &mcif_wb401_shift,
1730 &mcif_wb401_mask,
1731 i);
1732
1733 pool->mcif_wb[i] = &mcif_wb30->base;
1734 }
1735 return true;
1736 }
1737
dcn401_dsc_create(struct dc_context * ctx,uint32_t inst)1738 static struct display_stream_compressor *dcn401_dsc_create(
1739 struct dc_context *ctx, uint32_t inst)
1740 {
1741 struct dcn401_dsc *dsc =
1742 kzalloc_obj(struct dcn401_dsc);
1743
1744 if (!dsc) {
1745 BREAK_TO_DEBUGGER();
1746 return NULL;
1747 }
1748
1749 #undef REG_STRUCT
1750 #define REG_STRUCT dsc_regs
1751 dsc_regs_init(0),
1752 dsc_regs_init(1),
1753 dsc_regs_init(2),
1754 dsc_regs_init(3);
1755
1756 dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1757 dsc401_set_fgcg(dsc,
1758 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1759
1760 //dsc->max_image_width = 6016;
1761 dsc->max_image_width = 5760;
1762
1763 return &dsc->base;
1764 }
1765
dcn401_destroy_resource_pool(struct resource_pool ** pool)1766 static void dcn401_destroy_resource_pool(struct resource_pool **pool)
1767 {
1768 struct dcn401_resource_pool *dcn401_pool = TO_DCN401_RES_POOL(*pool);
1769
1770 dcn401_resource_destruct(dcn401_pool);
1771 kfree(dcn401_pool);
1772 *pool = NULL;
1773 }
1774
1775 static struct dc_cap_funcs cap_funcs = {
1776 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
1777 .get_subvp_en = dcn32_subvp_in_use,
1778 };
1779
dcn401_update_bw_bounding_box_fpu(struct dc * dc,struct clk_bw_params * bw_params)1780 static void dcn401_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params)
1781 {
1782 dc_assert_fp_enabled();
1783
1784 /* re-calculate the available MALL size if required */
1785 if (bw_params->num_channels > 0) {
1786 dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(
1787 dc, bw_params->num_channels) *
1788 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1789 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1790 }
1791
1792 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
1793 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
1794
1795 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
1796 dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source);
1797 }
1798
dcn401_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1799 static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1800 {
1801 DC_FP_START();
1802 dcn401_update_bw_bounding_box_fpu(dc, bw_params);
1803 DC_FP_END();
1804 }
dcn401_patch_unknown_plane_state(struct dc_plane_state * plane_state)1805 enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1806 {
1807 plane_state->tiling_info.gfxversion = DcGfxAddr3;
1808 plane_state->tiling_info.gfx_addr3.swizzle = DC_ADDR3_SW_64KB_2D;
1809 return DC_OK;
1810 }
1811
dcn401_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1812 enum dc_status dcn401_validate_bandwidth(struct dc *dc,
1813 struct dc_state *context,
1814 enum dc_validate_mode validate_mode)
1815 {
1816 unsigned int i;
1817 enum dc_status status = DC_OK;
1818 const struct dc_stream_state *stream;
1819
1820 /* reset cursor limitations on subvp */
1821 for (i = 0; i < context->stream_count; i++) {
1822 stream = context->streams[i];
1823
1824 if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) {
1825 dc_state_set_stream_cursor_subvp_limit(stream, context, false);
1826 }
1827 }
1828
1829 if (dc->debug.using_dml2) {
1830 DC_FP_START();
1831 status = dml2_validate(dc, context,
1832 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1833 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1834 DC_FP_END();
1835 }
1836
1837 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_OK && dc_state_is_subvp_in_use(context)) {
1838 /* check new stream configuration still supports cursor if subvp used */
1839 for (i = 0; i < context->stream_count; i++) {
1840 stream = context->streams[i];
1841
1842 if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM &&
1843 stream->cursor_position.enable &&
1844 !dc_stream_check_cursor_attributes(stream, context, &stream->cursor_attributes)) {
1845 /* hw cursor cannot be supported with subvp active, so disable subvp for now */
1846 dc_state_set_stream_cursor_subvp_limit(stream, context, true);
1847 status = DC_FAIL_HW_CURSOR_SUPPORT;
1848 }
1849 }
1850 }
1851
1852 if (validate_mode == DC_VALIDATE_MODE_AND_PROGRAMMING && status == DC_FAIL_HW_CURSOR_SUPPORT) {
1853 /* attempt to validate again with subvp disabled due to cursor */
1854 if (dc->debug.using_dml2) {
1855 DC_FP_START();
1856 status = dml2_validate(dc, context,
1857 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1858 validate_mode) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1859 DC_FP_END();
1860 }
1861 }
1862
1863 return status;
1864 }
1865
dcn401_prepare_mcache_programming(struct dc * dc,struct dc_state * context)1866 void dcn401_prepare_mcache_programming(struct dc *dc,
1867 struct dc_state *context)
1868 {
1869 if (dc->debug.using_dml21) {
1870 DC_FP_START();
1871 dml2_prepare_mcache_programming(dc, context,
1872 context->power_source == DC_POWER_SOURCE_DC ?
1873 context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2);
1874 DC_FP_END();
1875 }
1876 }
1877
dcn401_build_pipe_pix_clk_params(struct pipe_ctx * pipe_ctx)1878 static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
1879 {
1880 const struct dc_stream_state *stream = pipe_ctx->stream;
1881 struct dc_link *link = stream->link;
1882 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;
1883 struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;
1884
1885 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1886
1887 if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)
1888 pixel_clk_params->requested_pix_clk_100hz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz;
1889
1890 if (!pipe_ctx->stream->ctx->dc->config.unify_link_enc_assignment)
1891 link_enc = link_enc_cfg_get_link_enc(link);
1892 if (link_enc)
1893 pixel_clk_params->encoder_object_id = link_enc->id;
1894
1895 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1896 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1897 /* TODO: un-hardcode*/
1898
1899 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1900
1901 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1902 LINK_RATE_REF_FREQ_IN_KHZ;
1903 pixel_clk_params->flags.ENABLE_SS = 0;
1904 pixel_clk_params->color_depth =
1905 stream->timing.display_color_depth;
1906 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1907 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1908
1909 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1910 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1911
1912 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1913 pixel_clk_params->requested_pix_clk_100hz *= 2;
1914 if (dc_is_tmds_signal(stream->signal) &&
1915 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1916 pixel_clk_params->requested_pix_clk_100hz /= 2;
1917
1918 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1919 pipe_ctx->clock_source,
1920 &pipe_ctx->stream_res.pix_clk_params,
1921 &pipe_ctx->pll_settings);
1922
1923 pixel_clk_params->dio_se_pix_per_cycle = 1;
1924 if (dc_is_tmds_signal(stream->signal) &&
1925 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1926 pixel_clk_params->dio_se_pix_per_cycle = 2;
1927 } else if (dc_is_dp_signal(stream->signal)) {
1928 /* round up to nearest power of 2, or max at 8 pixels per cycle */
1929 if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
1930 pixel_clk_params->dio_se_pix_per_cycle = 8;
1931 } else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
1932 pixel_clk_params->dio_se_pix_per_cycle = 4;
1933 } else if ((unsigned int)pixel_clk_params->requested_pix_clk_100hz > (unsigned int)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) {
1934 pixel_clk_params->dio_se_pix_per_cycle = 2;
1935 } else {
1936 pixel_clk_params->dio_se_pix_per_cycle = 1;
1937 }
1938 }
1939 }
1940
dcn401_get_power_profile(const struct dc_state * context)1941 int dcn401_get_power_profile(const struct dc_state *context)
1942 {
1943 unsigned int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000;
1944 int dpm_level = 0;
1945
1946 for (unsigned int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) {
1947 if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 ||
1948 uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
1949 break;
1950 if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz)
1951 dpm_level++;
1952 }
1953
1954 return dpm_level;
1955 }
1956
dcn401_get_vstartup_for_pipe(struct pipe_ctx * pipe_ctx)1957 unsigned int dcn401_get_vstartup_for_pipe(struct pipe_ctx *pipe_ctx)
1958 {
1959 return pipe_ctx->global_sync.dcn4x.vstartup_lines;
1960 }
1961
1962 static struct resource_funcs dcn401_res_pool_funcs = {
1963 .destroy = dcn401_destroy_resource_pool,
1964 .link_enc_create = dcn401_link_encoder_create,
1965 .link_enc_create_minimal = NULL,
1966 .hpo_frl_link_enc_create = dcn401_hpo_frl_link_encoder_create,
1967 .panel_cntl_create = dcn32_panel_cntl_create,
1968 .validate_bandwidth = dcn401_validate_bandwidth,
1969 .calculate_wm_and_dlg = NULL,
1970 .populate_dml_pipes = NULL,
1971 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1972 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
1973 .release_pipe = dcn20_release_pipe,
1974 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1975 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1976 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1977 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1978 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1979 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1980 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1981 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1982 .update_bw_bounding_box = dcn401_update_bw_bounding_box,
1983 .patch_unknown_plane_state = dcn401_patch_unknown_plane_state,
1984 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1985 .add_phantom_pipes = dcn32_add_phantom_pipes,
1986 .prepare_mcache_programming = dcn401_prepare_mcache_programming,
1987 .build_pipe_pix_clk_params = dcn401_build_pipe_pix_clk_params,
1988 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
1989 .get_power_profile = dcn401_get_power_profile,
1990 .get_vstartup_for_pipe = dcn401_get_vstartup_for_pipe,
1991 .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size,
1992 .get_default_tiling_info = dcn401_get_default_tiling_info
1993 };
1994
dcn401_get_default_tiling_info(struct dc_tiling_info * tiling_info)1995 void dcn401_get_default_tiling_info(struct dc_tiling_info *tiling_info)
1996 {
1997 tiling_info->gfxversion = DcGfxAddr3;
1998 tiling_info->gfx_addr3.swizzle = DC_ADDR3_SW_LINEAR;
1999 }
2000
read_pipe_fuses(struct dc_context * ctx)2001 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2002 {
2003 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2004 /* DCN401 support max 4 pipes */
2005 value = value & 0xf;
2006 return value;
2007 }
2008
2009
dcn401_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn401_resource_pool * pool)2010 static bool dcn401_resource_construct(
2011 uint8_t num_virtual_links,
2012 struct dc *dc,
2013 struct dcn401_resource_pool *pool)
2014 {
2015 int i, j;
2016 struct dc_context *ctx = dc->ctx;
2017 struct irq_service_init_data init_data;
2018 struct ddc_service_init_data ddc_init_data = {0};
2019 uint32_t pipe_fuses = 0;
2020 uint32_t num_pipes = 4;
2021
2022 #undef REG_STRUCT
2023 #define REG_STRUCT bios_regs
2024 bios_regs_init();
2025
2026 #undef REG_STRUCT
2027 #define REG_STRUCT clk_src_regs
2028 clk_src_regs_init(0, A),
2029 clk_src_regs_init(1, B),
2030 clk_src_regs_init(2, C),
2031 clk_src_regs_init(3, D);
2032
2033 #undef REG_STRUCT
2034 #define REG_STRUCT abm_regs
2035 abm_regs_init(0),
2036 abm_regs_init(1),
2037 abm_regs_init(2),
2038 abm_regs_init(3);
2039
2040 #undef REG_STRUCT
2041 #define REG_STRUCT dccg_regs
2042 dccg_regs_init();
2043
2044 ctx->dc_bios->regs = &bios_regs;
2045
2046 pool->base.res_cap = &res_cap_dcn4_01;
2047
2048 /* max number of pipes for ASIC before checking for pipe fuses */
2049 num_pipes = pool->base.res_cap->num_timing_generator;
2050 pipe_fuses = read_pipe_fuses(ctx);
2051
2052 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
2053 if (pipe_fuses & 1 << i)
2054 num_pipes--;
2055
2056 if (pipe_fuses & 1)
2057 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
2058
2059 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
2060 ASSERT(0); //Entire DCN is harvested!
2061
2062 pool->base.funcs = &dcn401_res_pool_funcs;
2063
2064 /*************************************************
2065 * Resource + asic cap harcoding *
2066 *************************************************/
2067 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
2068 pool->base.timing_generator_count = num_pipes;
2069 pool->base.pipe_count = num_pipes;
2070 pool->base.mpcc_count = num_pipes;
2071 dc->caps.max_downscale_ratio = 600;
2072 dc->caps.i2c_speed_in_khz = 95;
2073 dc->caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/
2074 /* used to set cursor pitch, so must be aligned to power of 2 (HW actually supported 78x78) */
2075 dc->caps.max_cursor_size = 64;
2076 dc->caps.max_buffered_cursor_size = 64;
2077 dc->caps.cursor_not_scaled = true;
2078 dc->caps.min_horizontal_blanking_period = 80;
2079 dc->caps.dmdata_alloc_size = 2048;
2080 dc->caps.mall_size_per_mem_channel = 4;
2081 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2082 dc->caps.cache_line_size = 64;
2083 dc->caps.cache_num_ways = 16;
2084
2085 /* Calculate the available MALL space */
2086 dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall(
2087 dc, dc->ctx->dc_bios->vram_info.num_chans) *
2088 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
2089 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
2090
2091 dc->caps.subvp_fw_processing_delay_us = 15;
2092 dc->caps.subvp_drr_max_vblank_margin_us = 40;
2093 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
2094 dc->caps.subvp_swath_height_margin_lines = 16;
2095 dc->caps.subvp_pstate_allow_width_us = 20;
2096 dc->caps.subvp_vertical_int_margin_us = 30;
2097 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
2098
2099 dc->caps.max_slave_planes = 3;
2100 dc->caps.max_slave_yuv_planes = 3;
2101 dc->caps.max_slave_rgb_planes = 3;
2102 dc->caps.post_blend_color_processing = true;
2103 dc->caps.force_dp_tps4_for_cp2520 = true;
2104 dc->caps.hdmi_hpo = true;
2105 dc->caps.dp_hpo = true;
2106 dc->caps.dp_hdmi21_pcon_support = true;
2107 dc->caps.edp_dsc_support = true;
2108 dc->caps.extended_aux_timeout_support = true;
2109 dc->caps.dmcub_support = true;
2110 dc->caps.max_v_total = (1 << 15) - 1;
2111 dc->caps.vtotal_limited_by_fp2 = true;
2112
2113 if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev))
2114 dc->caps.dcc_plane_width_limit = 7680;
2115
2116 /* Color pipeline capabilities */
2117 dc->caps.color.dpp.dcn_arch = 1;
2118 dc->caps.color.dpp.input_lut_shared = 0;
2119 dc->caps.color.dpp.icsc = 1;
2120 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2121 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2122 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2123 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2124 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2125 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2126 dc->caps.color.dpp.post_csc = 1;
2127 dc->caps.color.dpp.gamma_corr = 1;
2128 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2129 dc->caps.color.dpp.upsp_pre_scaler = 0;
2130
2131 dc->caps.color.dpp.hw_3d_lut = 0;
2132 dc->caps.color.dpp.ogam_ram = 0;
2133 // no OGAM ROM on DCN2 and later ASICs
2134 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2135 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2136 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2137 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2138 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2139 dc->caps.color.dpp.ocsc = 0;
2140
2141 dc->caps.color.mpc.gamut_remap = 1;
2142 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
2143 dc->caps.color.mpc.ogam_ram = 1;
2144 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2145 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2146 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2147 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2148 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2149 dc->caps.color.mpc.ocsc = 1;
2150 dc->caps.color.mpc.preblend = true;
2151 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
2152 /* HACK: Force FRL support until BIOS is ready. */
2153 dc->config.force_hdmi21_frl_enc_enable = true;
2154 dc->config.use_spl = true;
2155 dc->config.prefer_easf = true;
2156
2157 dc->config.dcn_sharpness_range.sdr_rgb_min = 0;
2158 dc->config.dcn_sharpness_range.sdr_rgb_max = 1750;
2159 dc->config.dcn_sharpness_range.sdr_rgb_mid = 750;
2160 dc->config.dcn_sharpness_range.sdr_yuv_min = 0;
2161 dc->config.dcn_sharpness_range.sdr_yuv_max = 3500;
2162 dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500;
2163 dc->config.dcn_sharpness_range.hdr_rgb_min = 0;
2164 dc->config.dcn_sharpness_range.hdr_rgb_max = 2750;
2165 dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500;
2166
2167 dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0;
2168 dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250;
2169 dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250;
2170 dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0;
2171 dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500;
2172 dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500;
2173 dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0;
2174 dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750;
2175 dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500;
2176
2177 dc->config.dc_mode_clk_limit_support = true;
2178 dc->config.enable_windowed_mpo_odm = true;
2179 dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */
2180
2181 /* read VBIOS LTTPR caps */
2182 {
2183 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2184 enum bp_result bp_query_result;
2185 uint8_t is_vbios_lttpr_enable = 0;
2186
2187 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2188 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2189 }
2190
2191 /* interop bit is implicit */
2192 {
2193 dc->caps.vbios_lttpr_aware = true;
2194 }
2195 }
2196 dc->check_config = config_defaults;
2197
2198 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2199 dc->debug = debug_defaults_drv;
2200
2201 // Init the vm_helper
2202 if (dc->vm_helper)
2203 vm_helper_init(dc->vm_helper, 16);
2204
2205 /*************************************************
2206 * Create resources *
2207 *************************************************/
2208
2209 /* Clock Sources for Pixel Clock*/
2210 pool->base.clock_sources[DCN401_CLK_SRC_PLL0] =
2211 dcn401_clock_source_create(ctx, ctx->dc_bios,
2212 CLOCK_SOURCE_COMBO_PHY_PLL0,
2213 &clk_src_regs[0], false);
2214 pool->base.clock_sources[DCN401_CLK_SRC_PLL1] =
2215 dcn401_clock_source_create(ctx, ctx->dc_bios,
2216 CLOCK_SOURCE_COMBO_PHY_PLL1,
2217 &clk_src_regs[1], false);
2218 pool->base.clock_sources[DCN401_CLK_SRC_PLL2] =
2219 dcn401_clock_source_create(ctx, ctx->dc_bios,
2220 CLOCK_SOURCE_COMBO_PHY_PLL2,
2221 &clk_src_regs[2], false);
2222 pool->base.clock_sources[DCN401_CLK_SRC_PLL3] =
2223 dcn401_clock_source_create(ctx, ctx->dc_bios,
2224 CLOCK_SOURCE_COMBO_PHY_PLL3,
2225 &clk_src_regs[3], false);
2226 // pool->base.clock_sources[DCN401_CLK_SRC_PLL4] =
2227 // dcn401_clock_source_create(ctx, ctx->dc_bios,
2228 // CLOCK_SOURCE_COMBO_PHY_PLL4,
2229 // &clk_src_regs[4], false);
2230
2231 pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL;
2232
2233 /* todo: not reuse phy_pll registers */
2234 pool->base.dp_clock_source =
2235 dcn401_clock_source_create(ctx, ctx->dc_bios,
2236 CLOCK_SOURCE_ID_DP_DTO,
2237 &clk_src_regs[0], true);
2238
2239 for (i = 0; i < (int)pool->base.clk_src_count; i++) {
2240 if (pool->base.clock_sources[i] == NULL) {
2241 dm_error("DC: failed to create clock sources!\n");
2242 BREAK_TO_DEBUGGER();
2243 goto create_fail;
2244 }
2245 }
2246
2247 /* DCCG */
2248 pool->base.dccg = dccg401_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2249 if (pool->base.dccg == NULL) {
2250 dm_error("DC: failed to create dccg!\n");
2251 BREAK_TO_DEBUGGER();
2252 goto create_fail;
2253 }
2254
2255 /* IRQ Service */
2256 init_data.ctx = dc->ctx;
2257 pool->base.irqs = dal_irq_service_dcn401_create(&init_data);
2258 if (!pool->base.irqs)
2259 goto create_fail;
2260
2261 /* HUBBUB */
2262 pool->base.hubbub = dcn401_hubbub_create(ctx);
2263 if (pool->base.hubbub == NULL) {
2264 BREAK_TO_DEBUGGER();
2265 dm_error("DC: failed to create hubbub!\n");
2266 goto create_fail;
2267 }
2268
2269 /* DIO */
2270 pool->base.dio = dcn401_dio_create(ctx);
2271 if (pool->base.dio == NULL) {
2272 BREAK_TO_DEBUGGER();
2273 dm_error("DC: failed to create dio!\n");
2274 goto create_fail;
2275 }
2276
2277 /* HUBPs, DPPs, OPPs, TGs, ABMs */
2278 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2279
2280 /* if pipe is disabled, skip instance of HW pipe,
2281 * i.e, skip ASIC register instance
2282 */
2283 if (pipe_fuses & 1 << i)
2284 continue;
2285
2286 pool->base.hubps[j] = dcn401_hubp_create(ctx, i);
2287 if (pool->base.hubps[j] == NULL) {
2288 BREAK_TO_DEBUGGER();
2289 dm_error(
2290 "DC: failed to create hubps!\n");
2291 goto create_fail;
2292 }
2293
2294 pool->base.dpps[j] = dcn401_dpp_create(ctx, i);
2295 if (pool->base.dpps[j] == NULL) {
2296 BREAK_TO_DEBUGGER();
2297 dm_error(
2298 "DC: failed to create dpps!\n");
2299 goto create_fail;
2300 }
2301
2302 pool->base.opps[j] = dcn401_opp_create(ctx, i);
2303 if (pool->base.opps[j] == NULL) {
2304 BREAK_TO_DEBUGGER();
2305 dm_error(
2306 "DC: failed to create output pixel processor!\n");
2307 goto create_fail;
2308 }
2309
2310 pool->base.timing_generators[j] = dcn401_timing_generator_create(
2311 ctx, i);
2312 if (pool->base.timing_generators[j] == NULL) {
2313 BREAK_TO_DEBUGGER();
2314 dm_error("DC: failed to create tg!\n");
2315 goto create_fail;
2316 }
2317
2318 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2319 &abm_regs[i],
2320 &abm_shift,
2321 &abm_mask);
2322 if (pool->base.multiple_abms[j] == NULL) {
2323 dm_error("DC: failed to create abm for pipe %d!\n", i);
2324 BREAK_TO_DEBUGGER();
2325 goto create_fail;
2326 }
2327
2328 /* index for resource pool arrays for next valid pipe */
2329 j++;
2330 }
2331
2332 /* PSR */
2333 pool->base.psr = dmub_psr_create(ctx);
2334 if (pool->base.psr == NULL) {
2335 dm_error("DC: failed to create psr obj!\n");
2336 BREAK_TO_DEBUGGER();
2337 goto create_fail;
2338 }
2339
2340 /* MPCCs */
2341 pool->base.mpc = dcn401_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2342 if (pool->base.mpc == NULL) {
2343 BREAK_TO_DEBUGGER();
2344 dm_error("DC: failed to create mpc!\n");
2345 goto create_fail;
2346 }
2347
2348 /* DSCs */
2349 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2350 pool->base.dscs[i] = dcn401_dsc_create(ctx, i);
2351 if (pool->base.dscs[i] == NULL) {
2352 BREAK_TO_DEBUGGER();
2353 dm_error("DC: failed to create display stream compressor %d!\n", i);
2354 goto create_fail;
2355 }
2356 }
2357
2358 /* DWB */
2359 if (!dcn401_dwbc_create(ctx, &pool->base)) {
2360 BREAK_TO_DEBUGGER();
2361 dm_error("DC: failed to create dwbc!\n");
2362 goto create_fail;
2363 }
2364
2365 /* MMHUBBUB */
2366 if (!dcn401_mmhubbub_create(ctx, &pool->base)) {
2367 BREAK_TO_DEBUGGER();
2368 dm_error("DC: failed to create mcif_wb!\n");
2369 goto create_fail;
2370 }
2371
2372 /* AUX and I2C */
2373 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2374 pool->base.engines[i] = dcn401_aux_engine_create(ctx, i);
2375 if (pool->base.engines[i] == NULL) {
2376 BREAK_TO_DEBUGGER();
2377 dm_error(
2378 "DC:failed to create aux engine!!\n");
2379 goto create_fail;
2380 }
2381 pool->base.hw_i2cs[i] = dcn401_i2c_hw_create(ctx, i);
2382 if (pool->base.hw_i2cs[i] == NULL) {
2383 BREAK_TO_DEBUGGER();
2384 dm_error(
2385 "DC:failed to create hw i2c!!\n");
2386 goto create_fail;
2387 }
2388 pool->base.sw_i2cs[i] = NULL;
2389 }
2390
2391 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2392 if (!resource_construct(num_virtual_links, dc, &pool->base,
2393 &res_create_funcs))
2394 goto create_fail;
2395
2396 /* HW Sequencer init functions and Plane caps */
2397 dcn401_hw_sequencer_init_functions(dc);
2398
2399 dc->caps.max_planes = pool->base.pipe_count;
2400
2401 for (i = 0; i < (int)dc->caps.max_planes; ++i)
2402 dc->caps.planes[i] = plane_cap;
2403
2404 dc->caps.max_odm_combine_factor = 4;
2405
2406 dc->cap_funcs = cap_funcs;
2407
2408 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2409 ddc_init_data.ctx = dc->ctx;
2410 ddc_init_data.link = NULL;
2411 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2412 ddc_init_data.id.enum_id = 0;
2413 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2414 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2415 } else {
2416 pool->base.oem_device = NULL;
2417 }
2418
2419 //For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided
2420 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2421 dc->config.sdpif_request_limit_words_per_umc = 16;
2422
2423 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2424 dc->dml2_options.use_native_soc_bb_construction = true;
2425 dc->dml2_options.minimize_dispclk_using_odm = true;
2426 dc->dml2_options.map_dc_pipes_with_callbacks = true;
2427 dc->dml2_options.force_tdlut_enable = true;
2428
2429 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2430 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2431 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2432 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2433
2434 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2435 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2436 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2437 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2438
2439 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2440 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2441
2442 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2443 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2444 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2445 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2446 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2447 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2448 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2449
2450 dc->dml2_options.max_segments_per_hubp = 20;
2451 dc->dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB;
2452
2453 /* SPL */
2454 dc->caps.scl_caps.sharpener_support = true;
2455
2456 /* init DC limited DML2 options */
2457 memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options));
2458 dc->dml2_dc_power_options.use_clock_dc_limits = true;
2459
2460 return true;
2461
2462 create_fail:
2463
2464 dcn401_resource_destruct(pool);
2465
2466 return false;
2467 }
2468
dcn401_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2469 struct resource_pool *dcn401_create_resource_pool(
2470 const struct dc_init_data *init_data,
2471 struct dc *dc)
2472 {
2473 struct dcn401_resource_pool *pool =
2474 kzalloc_obj(struct dcn401_resource_pool);
2475
2476 if (!pool)
2477 return NULL;
2478
2479 if (dcn401_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2480 return &pool->base;
2481
2482 BREAK_TO_DEBUGGER();
2483 kfree(pool);
2484 return NULL;
2485 }
2486