1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dm_services.h"
28 #include "dc.h"
29
30 #include "dcn31/dcn31_init.h"
31 #include "dcn35/dcn35_init.h"
32
33 #include "resource.h"
34 #include "include/irq_service_interface.h"
35 #include "basics/conversion.h"
36 #include "dcn35_resource.h"
37 #include "dml2_0/dml2_wrapper.h"
38
39 #include "dcn20/dcn20_resource.h"
40 #include "dcn30/dcn30_resource.h"
41 #include "dcn31/dcn31_resource.h"
42 #include "dcn32/dcn32_resource.h"
43
44 #include "dcn10/dcn10_ipp.h"
45 #include "dcn30/dcn30_hubbub.h"
46 #include "dcn31/dcn31_hubbub.h"
47 #include "dcn35/dcn35_hubbub.h"
48 #include "dcn32/dcn32_mpc.h"
49 #include "dcn35/dcn35_hubp.h"
50 #include "irq/dcn35/irq_service_dcn35.h"
51 #include "dcn35/dcn35_dpp.h"
52 #include "dcn35/dcn35_optc.h"
53 #include "dcn20/dcn20_hwseq.h"
54 #include "dcn30/dcn30_hwseq.h"
55 #include "dce110/dce110_hwseq.h"
56 #include "dcn35/dcn35_opp.h"
57 #include "dcn35/dcn35_dsc.h"
58 #include "dcn30/dcn30_vpg.h"
59 #include "dcn30/dcn30_afmt.h"
60 #include "dcn31/dcn31_dio_link_encoder.h"
61 #include "dcn35/dcn35_dio_stream_encoder.h"
62 #include "dcn30/dcn30_hpo_frl_stream_encoder.h"
63 #include "dcn30/dcn30_hpo_frl_link_encoder.h"
64 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
65 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
66 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
67 #include "link_service.h"
68 #include "dcn31/dcn31_apg.h"
69 #include "dcn32/dcn32_dio_link_encoder.h"
70 #include "dcn31/dcn31_vpg.h"
71 #include "dcn31/dcn31_afmt.h"
72 #include "dce/dce_clock_source.h"
73 #include "dce/dce_audio.h"
74 #include "dce/dce_hwseq.h"
75 #include "clk_mgr.h"
76 #include "dio/virtual/virtual_stream_encoder.h"
77 #include "dio/dcn10/dcn10_dio.h"
78 #include "dce110/dce110_resource.h"
79 #include "dml/display_mode_vba.h"
80 #include "dcn35/dcn35_dccg.h"
81 #include "dcn35/dcn35_pg_cntl.h"
82 #include "dcn10/dcn10_resource.h"
83 #include "dcn31/dcn31_panel_cntl.h"
84 #include "dcn35/dcn35_hwseq.h"
85 #include "dcn35/dcn35_dio_link_encoder.h"
86 #include "dml/dcn31/dcn31_fpu.h" /*todo*/
87 #include "dml/dcn35/dcn35_fpu.h"
88 #include "dcn35/dcn35_dwb.h"
89 #include "dcn35/dcn35_mmhubbub.h"
90
91 #include "dcn/dcn_3_5_0_offset.h"
92 #include "dcn/dcn_3_5_0_sh_mask.h"
93 #include "nbio/nbio_7_11_0_offset.h"
94 #include "mmhub/mmhub_3_3_0_offset.h"
95 #include "mmhub/mmhub_3_3_0_sh_mask.h"
96
97 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
98 #define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
99
100 #include "reg_helper.h"
101 #include "dce/dmub_abm.h"
102 #include "dce/dmub_psr.h"
103 #include "dce/dmub_replay.h"
104 #include "dce/dce_aux.h"
105 #include "dce/dce_i2c.h"
106 #include "dml/dcn31/display_mode_vba_31.h" /*temp*/
107 #include "vm_helper.h"
108 #include "dcn20/dcn20_vmid.h"
109
110 #include "dc_state_priv.h"
111
112 #include "link_enc_cfg.h"
113 #define DC_LOGGER_INIT(logger)
114
115 enum dcn35_clk_src_array_id {
116 DCN35_CLK_SRC_PLL0,
117 DCN35_CLK_SRC_PLL1,
118 DCN35_CLK_SRC_PLL2,
119 DCN35_CLK_SRC_PLL3,
120 DCN35_CLK_SRC_PLL4,
121 DCN35_CLK_SRC_TOTAL
122 };
123
124 /* begin *********************
125 * macros to expend register list macro defined in HW object header file
126 */
127
128 /* DCN */
129 /* TODO awful hack. fixup dcn20_dwb.h */
130 #undef BASE_INNER
131 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
132
133 #define BASE(seg) BASE_INNER(seg)
134
135 #define SR(reg_name)\
136 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
137 reg ## reg_name
138
139 #define SR_ARR(reg_name, id) \
140 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
141
142 #define SR_ARR_INIT(reg_name, id, value) \
143 REG_STRUCT[id].reg_name = value
144
145 #define SRI(reg_name, block, id)\
146 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
147 reg ## block ## id ## _ ## reg_name
148
149 #define SRI_ARR(reg_name, block, id)\
150 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
151 reg ## block ## id ## _ ## reg_name
152
153 #define SR_ARR_I2C(reg_name, id) \
154 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
155
156 #define SRI_ARR_I2C(reg_name, block, id)\
157 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 reg ## block ## id ## _ ## reg_name
159
160 #define SRI_ARR_DME(reg_name, block, id, offset)\
161 REG_STRUCT[id - offset].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
163
164 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
165 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
166 reg ## block ## id ## _ ## reg_name
167
168 #define SRI2(reg_name, block, id)\
169 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
170 reg ## reg_name
171
172 #define SRI2_ARR(reg_name, block, id)\
173 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
174 reg ## reg_name
175
176 #define SRIR(var_name, reg_name, block, id)\
177 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
178 reg ## block ## id ## _ ## reg_name
179
180 #define SRII(reg_name, block, id)\
181 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
182 reg ## block ## id ## _ ## reg_name
183
184 #define SRII_ARR_2(reg_name, block, id, inst)\
185 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
186 reg ## block ## id ## _ ## reg_name
187
188 #define SRII_MPC_RMU(reg_name, block, id)\
189 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
190 reg ## block ## id ## _ ## reg_name
191
192 #define SRII_DWB(reg_name, temp_name, block, id)\
193 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
194 reg ## block ## id ## _ ## temp_name
195
196 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
197 .field_name = reg_name ## __ ## field_name ## post_fix
198
199 #define DCCG_SRII(reg_name, block, id)\
200 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
201 reg ## block ## id ## _ ## reg_name
202
203 #define VUPDATE_SRII(reg_name, block, id)\
204 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
205 reg ## reg_name ## _ ## block ## id
206
207 /* NBIO */
208 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
209
210 #define NBIO_BASE(seg) \
211 NBIO_BASE_INNER(seg)
212
213 #define NBIO_SR(reg_name)\
214 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
215 regBIF_BX1_ ## reg_name
216
217 #define NBIO_SR_ARR(reg_name, id)\
218 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
219 regBIF_BX1_ ## reg_name
220
221 #define bios_regs_init() \
222 ( \
223 NBIO_SR(BIOS_SCRATCH_3),\
224 NBIO_SR(BIOS_SCRATCH_6)\
225 )
226
227 static struct bios_registers bios_regs;
228
229 #define clk_src_regs_init(index, pllid)\
230 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
231
232 static struct dce110_clk_src_regs clk_src_regs[5];
233
234 static const struct dce110_clk_src_shift cs_shift = {
235 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
236 };
237
238 static const struct dce110_clk_src_mask cs_mask = {
239 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
240 };
241
242 #define abm_regs_init(id)\
243 ABM_DCN32_REG_LIST_RI(id)
244
245 static struct dce_abm_registers abm_regs[4];
246
247 static const struct dce_abm_shift abm_shift = {
248 ABM_MASK_SH_LIST_DCN35(__SHIFT)
249 };
250
251 static const struct dce_abm_mask abm_mask = {
252 ABM_MASK_SH_LIST_DCN35(_MASK)
253 };
254
255 #define audio_regs_init(id)\
256 AUD_COMMON_REG_LIST_RI(id)
257
258 static struct dce_audio_registers audio_regs[7];
259
260
261 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
262 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
263 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
264 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
265
266 static const struct dce_audio_shift audio_shift = {
267 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
268 };
269
270 static const struct dce_audio_mask audio_mask = {
271 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
272 };
273
274 #define vpg_regs_init(id)\
275 VPG_DCN31_REG_LIST_RI(id)
276
277 static struct dcn31_vpg_registers vpg_regs[10];
278
279 static const struct dcn31_vpg_shift vpg_shift = {
280 DCN31_VPG_MASK_SH_LIST(__SHIFT)
281 };
282
283 static const struct dcn31_vpg_mask vpg_mask = {
284 DCN31_VPG_MASK_SH_LIST(_MASK)
285 };
286
287 #define afmt_regs_init(id)\
288 AFMT_DCN31_REG_LIST_RI(id)
289
290 static struct dcn31_afmt_registers afmt_regs[6];
291
292 static const struct dcn31_afmt_shift afmt_shift = {
293 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
294 };
295
296 static const struct dcn31_afmt_mask afmt_mask = {
297 DCN31_AFMT_MASK_SH_LIST(_MASK)
298 };
299
300 #define apg_regs_init(id)\
301 APG_DCN31_REG_LIST_RI(id)
302
303 static struct dcn31_apg_registers apg_regs[4];
304
305 static const struct dcn31_apg_shift apg_shift = {
306 DCN31_APG_MASK_SH_LIST(__SHIFT)
307 };
308
309 static const struct dcn31_apg_mask apg_mask = {
310 DCN31_APG_MASK_SH_LIST(_MASK)
311 };
312
313 #define stream_enc_regs_init(id)\
314 SE_DCN35_REG_LIST_RI(id)
315
316 static struct dcn10_stream_enc_registers stream_enc_regs[5];
317
318 static const struct dcn10_stream_encoder_shift se_shift = {
319 SE_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
320 };
321
322 static const struct dcn10_stream_encoder_mask se_mask = {
323 SE_COMMON_MASK_SH_LIST_DCN35(_MASK)
324 };
325
326 #define aux_regs_init(id)\
327 DCN2_AUX_REG_LIST_RI(id)
328
329 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
330
331 #define hpd_regs_init(id)\
332 HPD_REG_LIST_RI(id)
333
334 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
335
336
337 static const struct dce110_aux_registers_shift aux_shift = {
338 DCN_AUX_MASK_SH_LIST(__SHIFT)
339 };
340
341 static const struct dce110_aux_registers_mask aux_mask = {
342 DCN_AUX_MASK_SH_LIST(_MASK)
343 };
344
345 #define link_regs_init(id, phyid)\
346 ( \
347 LE_DCN35_REG_LIST_RI(id), \
348 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
349 )
350
351 static struct dcn10_link_enc_registers link_enc_regs[5];
352
353 static const struct dcn10_link_enc_shift le_shift = {
354 LINK_ENCODER_MASK_SH_LIST_DCN35(__SHIFT), \
355 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
356 };
357
358 static const struct dcn10_link_enc_mask le_mask = {
359 LINK_ENCODER_MASK_SH_LIST_DCN35(_MASK), \
360 //DPCS_DCN31_MASK_SH_LIST(_MASK)
361 };
362
363 #define hpo_frl_stream_encoder_dme_reg_list(id)\
364 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST_RI(id, 6)
365
366 #define hpo_frl_stream_encoder_reg_list(id)\
367 DCN3_0_HPO_FRL_STREAM_ENC_REG_LIST_RI(id)
368
369 static struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[2];
370
371 static const struct dcn30_hpo_frl_stream_encoder_shift hpo_se_shift = {
372 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT)
373 };
374
375 static const struct dcn30_hpo_frl_stream_encoder_mask hpo_se_mask = {
376 DCN3_0_HPO_STREAM_ENC_MASK_SH_LIST(_MASK)
377 };
378
379 #define hpo_frl_link_encoder_reg_list(id)\
380 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST_RI(id)
381
382 static struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[1];
383
384 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = {
385 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT)
386 };
387
388 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = {
389 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK)
390 };
391
392 #define hpo_dp_stream_encoder_reg_init(id)\
393 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
394
395 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
396
397 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
398 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
399 };
400
401 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
402 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
403 };
404
405 #define hpo_dp_link_encoder_reg_init(id)\
406 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
407 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
408 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
409 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
410 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
411
412 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
413
414 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
415 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(__SHIFT)
416 };
417
418 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
419 DCN3_1_HPO_DP_LINK_ENC_COMMON_MASK_SH_LIST(_MASK)
420 };
421
422 #define dpp_regs_init(id)\
423 DPP_REG_LIST_DCN35_RI(id)
424
425 static struct dcn3_dpp_registers dpp_regs[4];
426
427 static const struct dcn35_dpp_shift tf_shift = {
428 DPP_REG_LIST_SH_MASK_DCN35(__SHIFT)
429 };
430
431 static const struct dcn35_dpp_mask tf_mask = {
432 DPP_REG_LIST_SH_MASK_DCN35(_MASK)
433 };
434
435 #define opp_regs_init(id)\
436 OPP_REG_LIST_DCN35_RI(id)
437
438 static struct dcn35_opp_registers opp_regs[4];
439
440 static const struct dcn35_opp_shift opp_shift = {
441 OPP_MASK_SH_LIST_DCN35(__SHIFT)
442 };
443
444 static const struct dcn35_opp_mask opp_mask = {
445 OPP_MASK_SH_LIST_DCN35(_MASK)
446 };
447
448 #define aux_engine_regs_init(id)\
449 ( \
450 AUX_COMMON_REG_LIST0_RI(id), \
451 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
452 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
453 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) \
454 )
455
456 static struct dce110_aux_registers aux_engine_regs[5];
457
458 #define dwbc_regs_dcn3_init(id)\
459 DWBC_COMMON_REG_LIST_DCN30_RI(id)
460
461 static struct dcn30_dwbc_registers dwbc35_regs[1];
462
463 static const struct dcn35_dwbc_shift dwbc35_shift = {
464 DWBC_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
465 };
466
467 static const struct dcn35_dwbc_mask dwbc35_mask = {
468 DWBC_COMMON_MASK_SH_LIST_DCN35(_MASK)
469 };
470
471 #define mcif_wb_regs_dcn3_init(id)\
472 MCIF_WB_COMMON_REG_LIST_DCN3_5_RI(id)
473
474 static struct dcn35_mmhubbub_registers mcif_wb35_regs[1];
475
476 static const struct dcn35_mmhubbub_shift mcif_wb35_shift = {
477 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
478 };
479
480 static const struct dcn35_mmhubbub_mask mcif_wb35_mask = {
481 MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
482 };
483
484 #define dsc_regsDCN35_init(id)\
485 DSC_REG_LIST_DCN20_RI(id)
486
487 static struct dcn20_dsc_registers dsc_regs[4];
488
489 static const struct dcn35_dsc_shift dsc_shift = {
490 DSC_REG_LIST_SH_MASK_DCN35(__SHIFT)
491 };
492
493 static const struct dcn35_dsc_mask dsc_mask = {
494 DSC_REG_LIST_SH_MASK_DCN35(_MASK)
495 };
496
497 static struct dcn30_mpc_registers mpc_regs;
498
499 #define dcn_mpc_regs_init() \
500 MPC_REG_LIST_DCN3_2_RI(0),\
501 MPC_REG_LIST_DCN3_2_RI(1),\
502 MPC_REG_LIST_DCN3_2_RI(2),\
503 MPC_REG_LIST_DCN3_2_RI(3),\
504 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
505 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
506 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
507 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
508 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
509
510 static const struct dcn30_mpc_shift mpc_shift = {
511 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
512 };
513
514 static const struct dcn30_mpc_mask mpc_mask = {
515 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
516 };
517
518 #define optc_regs_init(id)\
519 OPTC_COMMON_REG_LIST_DCN3_5_RI(id)
520
521 static struct dcn_optc_registers optc_regs[4];
522
523 static const struct dcn_optc_shift optc_shift = {
524 OPTC_COMMON_MASK_SH_LIST_DCN3_5(__SHIFT)
525 };
526
527 static const struct dcn_optc_mask optc_mask = {
528 OPTC_COMMON_MASK_SH_LIST_DCN3_5(_MASK)
529 };
530
531 #define hubp_regs_init(id)\
532 HUBP_REG_LIST_DCN30_RI(id)
533
534 static struct dcn_hubp2_registers hubp_regs[4];
535
536
537 static const struct dcn35_hubp2_shift hubp_shift = {
538 HUBP_MASK_SH_LIST_DCN35(__SHIFT)
539 };
540
541 static const struct dcn35_hubp2_mask hubp_mask = {
542 HUBP_MASK_SH_LIST_DCN35(_MASK)
543 };
544
545 static struct dcn_hubbub_registers hubbub_reg;
546
547 #define hubbub_reg_init()\
548 HUBBUB_REG_LIST_DCN35(0)
549
550 static const struct dcn_hubbub_shift hubbub_shift = {
551 HUBBUB_MASK_SH_LIST_DCN35(__SHIFT)
552 };
553
554 static const struct dcn_hubbub_mask hubbub_mask = {
555 HUBBUB_MASK_SH_LIST_DCN35(_MASK)
556 };
557
558 static struct dccg_registers dccg_regs;
559
560 #define dccg_regs_init()\
561 DCCG_REG_LIST_DCN35()
562
563 static const struct dccg_shift dccg_shift = {
564 DCCG_MASK_SH_LIST_DCN35(__SHIFT)
565 };
566
567 static const struct dccg_mask dccg_mask = {
568 DCCG_MASK_SH_LIST_DCN35(_MASK)
569 };
570
571 static struct pg_cntl_registers pg_cntl_regs;
572
573 #define pg_cntl_dcn35_regs_init() \
574 PG_CNTL_REG_LIST_DCN35()
575
576 static const struct pg_cntl_shift pg_cntl_shift = {
577 PG_CNTL_MASK_SH_LIST_DCN35(__SHIFT)
578 };
579
580 static const struct pg_cntl_mask pg_cntl_mask = {
581 PG_CNTL_MASK_SH_LIST_DCN35(_MASK)
582 };
583
584 #define SRII2(reg_name_pre, reg_name_post, id)\
585 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
586 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
587 reg ## reg_name_pre ## id ## _ ## reg_name_post
588
589 static struct dce_hwseq_registers hwseq_reg;
590
591 #define hwseq_reg_init()\
592 HWSEQ_DCN35_REG_LIST()
593
594 #define HWSEQ_DCN35_MASK_SH_LIST(mask_sh)\
595 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
596 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
597 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
598 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
599 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
600 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
601 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
602 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
603 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
604 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
605 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
606 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
607 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
608 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
609 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
610 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
611 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
612 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
613 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
614 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
615 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
616 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
617 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
618 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
619 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
620 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
621 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
622 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
623 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
624 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
625 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
626 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
627 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
628 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
629 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
630 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
631 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
632 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
633 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
634 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
635 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
636 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
637 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
638 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
639 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
640 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh),\
641 HWS_SF(, DMU_CLK_CNTL, DISPCLK_R_DMU_GATE_DIS, mask_sh),\
642 HWS_SF(, DMU_CLK_CNTL, DISPCLK_G_RBBMIF_GATE_DIS, mask_sh),\
643 HWS_SF(, DMU_CLK_CNTL, RBBMIF_FGCG_REP_DIS, mask_sh),\
644 HWS_SF(, DMU_CLK_CNTL, DPREFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
645 HWS_SF(, DMU_CLK_CNTL, DISPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
646 HWS_SF(, DMU_CLK_CNTL, DPPCLK_ALLOW_DS_CLKSTOP, mask_sh),\
647 HWS_SF(, DMU_CLK_CNTL, DTBCLK_ALLOW_DS_CLKSTOP, mask_sh),\
648 HWS_SF(, DMU_CLK_CNTL, DCFCLK_ALLOW_DS_CLKSTOP, mask_sh),\
649 HWS_SF(, DMU_CLK_CNTL, DPIACLK_ALLOW_DS_CLKSTOP, mask_sh),\
650 HWS_SF(, DMU_CLK_CNTL, LONO_FGCG_REP_DIS, mask_sh),\
651 HWS_SF(, DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE, mask_sh),\
652 HWS_SF(, DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE, mask_sh),\
653 HWS_SF(, DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE, mask_sh),\
654 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
655 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
656 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
657 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
658 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
659 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
660 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
661 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
662 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
663 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
664 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_GATE_DISABLE, mask_sh), \
665 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh), \
666 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
667 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
668 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
669 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
670 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
671 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
672 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
673 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
674 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
675 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
676 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
677 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
678 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
679 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
680 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
681 HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
682
683 static const struct dce_hwseq_shift hwseq_shift = {
684 HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
685 };
686
687 static const struct dce_hwseq_mask hwseq_mask = {
688 HWSEQ_DCN35_MASK_SH_LIST(_MASK)
689 };
690
691 #define vmid_regs_init(id)\
692 DCN20_VMID_REG_LIST_RI(id)
693
694 static struct dcn_vmid_registers vmid_regs[16];
695
696 static const struct dcn20_vmid_shift vmid_shifts = {
697 DCN20_VMID_MASK_SH_LIST(__SHIFT)
698 };
699
700 static const struct dcn20_vmid_mask vmid_masks = {
701 DCN20_VMID_MASK_SH_LIST(_MASK)
702 };
703
704 static struct dcn_dio_registers dio_regs;
705
706 #define DIO_MASK_SH_LIST(mask_sh)\
707 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
708
709 static const struct dcn_dio_shift dio_shift = {
710 DIO_MASK_SH_LIST(__SHIFT)
711 };
712
713 static const struct dcn_dio_mask dio_mask = {
714 DIO_MASK_SH_LIST(_MASK)
715 };
716
717 static const struct resource_caps res_cap_dcn35 = {
718 .num_timing_generator = 4,
719 .num_opp = 4,
720 .num_video_plane = 4,
721 .num_audio = 5,
722 .num_stream_encoder = 5,
723 .num_dig_link_enc = 5,
724 .num_hpo_frl = 1,
725 .num_hpo_dp_stream_encoder = 4,
726 .num_hpo_dp_link_encoder = 2,
727 .num_pll = 4,/*1 c10 edp, 3xc20 combo PHY*/
728 .num_dwb = 1,
729 .num_ddc = 5,
730 .num_vmid = 16,
731 .num_mpc_3dlut = 2,
732 .num_dsc = 4,
733 };
734
735 static const struct dc_plane_cap plane_cap = {
736 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
737 .per_pixel_alpha = true,
738
739 .pixel_format_support = {
740 .argb8888 = true,
741 .nv12 = true,
742 .fp16 = true,
743 .p010 = true,
744 .ayuv = false,
745 },
746
747 .max_upscale_factor = {
748 .argb8888 = 16000,
749 .nv12 = 16000,
750 .fp16 = 16000
751 },
752
753 // 6:1 downscaling ratio: 1000/6 = 166.666
754 .max_downscale_factor = {
755 .argb8888 = 250,
756 .nv12 = 167,
757 .fp16 = 167
758 },
759 64,
760 64
761 };
762
763 static const struct dc_debug_options debug_defaults_drv = {
764 .limit_ffe = 3,
765 .disable_dmcu = true,
766 .force_abm_enable = false,
767 .clock_trace = true,
768 .disable_pplib_clock_request = false,
769 .pipe_split_policy = MPC_SPLIT_AVOID,
770 .force_single_disp_pipe_split = false,
771 .disable_dcc = DCC_ENABLE,
772 .disable_dpp_power_gate = true,
773 .disable_hubp_power_gate = true,
774 .disable_optc_power_gate = true, /*should the same as above two*/
775 .disable_hpo_power_gate = true, /*dmubfw force domain25 on*/
776 .disable_clock_gate = false,
777 .disable_dsc_power_gate = true,
778 .vsr_support = true,
779 .performance_trace = false,
780 .max_downscale_src_width = 4096,/*upto true 4k*/
781 .disable_pplib_wm_range = false,
782 .scl_reset_length10 = true,
783 .sanity_checks = false,
784 .underflow_assert_delay_us = 0xFFFFFFFF,
785 .dwb_fi_phase = -1, // -1 = disable,
786 .dmub_command_table = true,
787 .pstate_enabled = true,
788 .use_max_lb = true,
789 .enable_mem_low_power = {
790 .bits = {
791 .vga = false,
792 .i2c = true,
793 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
794 .dscl = true,
795 .cm = true,
796 .mpc = true,
797 .optc = true,
798 .vpg = true,
799 .afmt = true,
800 }
801 },
802 .root_clock_optimization = {
803 .bits = {
804 .dpp = true,
805 .dsc = true,/*dscclk and dsc pg*/
806 .hdmistream = true,
807 .hdmichar = true,
808 .dpstream = true,
809 .symclk32_se = true,
810 .symclk32_le = true,
811 .symclk_fe = true,
812 .physymclk = false,
813 .dpiasymclk = true,
814 }
815 },
816 .seamless_boot_odm_combine = DML_FAIL_SOURCE_PIXEL_FORMAT,
817 .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
818 .minimum_z8_residency_time = 1, /* Always allow when other conditions are met */
819 .using_dml2 = true,
820 .support_eDP1_5 = true,
821 .enable_hpo_pg_support = false,
822 .enable_single_display_2to1_odm_policy = true,
823 .disable_idle_power_optimizations = false,
824 .disable_boot_optimizations = false,
825 .disable_unbounded_requesting = false,
826 .disable_mem_low_power = false,
827 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
828 .enable_double_buffered_dsc_pg_support = true,
829 .enable_dp_dig_pixel_rate_div_policy = 1,
830 .disable_z10 = false,
831 .ignore_pg = true,
832 .psp_disabled_wa = true,
833 .ips2_eval_delay_us = 2000,
834 .ips2_entry_delay_us = 800,
835 .disable_dmub_reallow_idle = false,
836 .static_screen_wait_frames = 2,
837 .disable_timeout = true,
838 .min_disp_clk_khz = 50000,
839 };
840
841 static const struct dc_check_config config_defaults = {
842 .enable_legacy_fast_update = false,
843 };
844
845 static const struct dc_panel_config panel_config_defaults = {
846 .psr = {
847 .disable_psr = false,
848 .disallow_psrsu = false,
849 .disallow_replay = false,
850 },
851 .ilr = {
852 .optimize_edp_link_rate = true,
853 },
854 };
855
dcn35_dpp_destroy(struct dpp ** dpp)856 static void dcn35_dpp_destroy(struct dpp **dpp)
857 {
858 kfree(TO_DCN20_DPP(*dpp));
859 *dpp = NULL;
860 }
861
dcn35_dpp_create(struct dc_context * ctx,uint32_t inst)862 static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)
863 {
864 struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);
865 bool success = (dpp != NULL);
866
867 if (!success)
868 return NULL;
869
870 #undef REG_STRUCT
871 #define REG_STRUCT dpp_regs
872 dpp_regs_init(0),
873 dpp_regs_init(1),
874 dpp_regs_init(2),
875 dpp_regs_init(3);
876
877 success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,
878 &tf_mask);
879 if (success) {
880 dpp35_set_fgcg(
881 dpp,
882 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
883 return &dpp->base;
884 }
885
886 BREAK_TO_DEBUGGER();
887 kfree(dpp);
888 return NULL;
889 }
890
dcn35_opp_create(struct dc_context * ctx,uint32_t inst)891 static struct output_pixel_processor *dcn35_opp_create(
892 struct dc_context *ctx, uint32_t inst)
893 {
894 struct dcn20_opp *opp =
895 kzalloc_obj(struct dcn20_opp);
896
897 if (!opp) {
898 BREAK_TO_DEBUGGER();
899 return NULL;
900 }
901
902 #undef REG_STRUCT
903 #define REG_STRUCT opp_regs
904 opp_regs_init(0),
905 opp_regs_init(1),
906 opp_regs_init(2),
907 opp_regs_init(3);
908
909 dcn35_opp_construct(opp, ctx, inst,
910 &opp_regs[inst], &opp_shift, &opp_mask);
911
912 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
913
914 return &opp->base;
915 }
916
dcn31_aux_engine_create(struct dc_context * ctx,uint32_t inst)917 static struct dce_aux *dcn31_aux_engine_create(
918 struct dc_context *ctx,
919 uint32_t inst)
920 {
921 struct aux_engine_dce110 *aux_engine =
922 kzalloc_obj(struct aux_engine_dce110);
923
924 if (!aux_engine)
925 return NULL;
926
927 #undef REG_STRUCT
928 #define REG_STRUCT aux_engine_regs
929 aux_engine_regs_init(0),
930 aux_engine_regs_init(1),
931 aux_engine_regs_init(2),
932 aux_engine_regs_init(3),
933 aux_engine_regs_init(4);
934
935 dce110_aux_engine_construct(aux_engine, ctx, inst,
936 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
937 &aux_engine_regs[inst],
938 &aux_mask,
939 &aux_shift,
940 ctx->dc->caps.extended_aux_timeout_support);
941
942 return &aux_engine->base;
943 }
944
945 #define i2c_inst_regs_init(id)\
946 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
947
948 static struct dce_i2c_registers i2c_hw_regs[5];
949
950 static const struct dce_i2c_shift i2c_shifts = {
951 I2C_COMMON_MASK_SH_LIST_DCN35(__SHIFT)
952 };
953
954 static const struct dce_i2c_mask i2c_masks = {
955 I2C_COMMON_MASK_SH_LIST_DCN35(_MASK)
956 };
957
958 /* ========================================================== */
959
960 /*
961 * DPIA index | Preferred Encoder | Host Router
962 * 0 | C | 0
963 * 1 | First Available | 0
964 * 2 | D | 1
965 * 3 | First Available | 1
966 */
967 /* ========================================================== */
968 static const enum engine_id dpia_to_preferred_enc_id_table[] = {
969 ENGINE_ID_DIGC,
970 ENGINE_ID_DIGC,
971 ENGINE_ID_DIGD,
972 ENGINE_ID_DIGD
973 };
974
dcn35_get_preferred_eng_id_dpia(unsigned int dpia_index)975 static enum engine_id dcn35_get_preferred_eng_id_dpia(unsigned int dpia_index)
976 {
977 return dpia_to_preferred_enc_id_table[dpia_index];
978 }
979
dcn31_i2c_hw_create(struct dc_context * ctx,uint32_t inst)980 static struct dce_i2c_hw *dcn31_i2c_hw_create(
981 struct dc_context *ctx,
982 uint32_t inst)
983 {
984 struct dce_i2c_hw *dce_i2c_hw =
985 kzalloc_obj(struct dce_i2c_hw);
986
987 if (!dce_i2c_hw)
988 return NULL;
989
990 #undef REG_STRUCT
991 #define REG_STRUCT i2c_hw_regs
992 i2c_inst_regs_init(1),
993 i2c_inst_regs_init(2),
994 i2c_inst_regs_init(3),
995 i2c_inst_regs_init(4),
996 i2c_inst_regs_init(5);
997
998 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
999 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1000
1001 return dce_i2c_hw;
1002 }
dcn35_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)1003 static struct mpc *dcn35_mpc_create(
1004 struct dc_context *ctx,
1005 int num_mpcc,
1006 int num_rmu)
1007 {
1008 struct dcn30_mpc *mpc30 = kzalloc_obj(struct dcn30_mpc);
1009
1010 if (!mpc30)
1011 return NULL;
1012
1013 #undef REG_STRUCT
1014 #define REG_STRUCT mpc_regs
1015 dcn_mpc_regs_init();
1016
1017 dcn32_mpc_construct(mpc30, ctx,
1018 &mpc_regs,
1019 &mpc_shift,
1020 &mpc_mask,
1021 num_mpcc,
1022 num_rmu);
1023
1024 return &mpc30->base;
1025 }
1026
dcn35_dio_create(struct dc_context * ctx)1027 static struct dio *dcn35_dio_create(struct dc_context *ctx)
1028 {
1029 struct dcn10_dio *dio10 = kzalloc_obj(struct dcn10_dio);
1030
1031 if (!dio10)
1032 return NULL;
1033
1034 #undef REG_STRUCT
1035 #define REG_STRUCT dio_regs
1036 DIO_REG_LIST_DCN10();
1037
1038 dcn10_dio_construct(dio10, ctx, &dio_regs, &dio_shift, &dio_mask);
1039
1040 return &dio10->base;
1041 }
1042
dcn35_hubbub_create(struct dc_context * ctx)1043 static struct hubbub *dcn35_hubbub_create(struct dc_context *ctx)
1044 {
1045 int i;
1046
1047 struct dcn20_hubbub *hubbub3 = kzalloc_obj(struct dcn20_hubbub);
1048
1049 if (!hubbub3)
1050 return NULL;
1051
1052 #undef REG_STRUCT
1053 #define REG_STRUCT hubbub_reg
1054 hubbub_reg_init();
1055
1056 #undef REG_STRUCT
1057 #define REG_STRUCT vmid_regs
1058 vmid_regs_init(0),
1059 vmid_regs_init(1),
1060 vmid_regs_init(2),
1061 vmid_regs_init(3),
1062 vmid_regs_init(4),
1063 vmid_regs_init(5),
1064 vmid_regs_init(6),
1065 vmid_regs_init(7),
1066 vmid_regs_init(8),
1067 vmid_regs_init(9),
1068 vmid_regs_init(10),
1069 vmid_regs_init(11),
1070 vmid_regs_init(12),
1071 vmid_regs_init(13),
1072 vmid_regs_init(14),
1073 vmid_regs_init(15);
1074
1075 hubbub35_construct(hubbub3, ctx,
1076 &hubbub_reg,
1077 &hubbub_shift,
1078 &hubbub_mask,
1079 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
1080 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
1081 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
1082
1083
1084 for (i = 0; i < res_cap_dcn35.num_vmid; i++) {
1085 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1086
1087 vmid->ctx = ctx;
1088
1089 vmid->regs = &vmid_regs[i];
1090 vmid->shifts = &vmid_shifts;
1091 vmid->masks = &vmid_masks;
1092 }
1093
1094 return &hubbub3->base;
1095 }
1096
dcn35_timing_generator_create(struct dc_context * ctx,uint32_t instance)1097 static struct timing_generator *dcn35_timing_generator_create(
1098 struct dc_context *ctx,
1099 uint32_t instance)
1100 {
1101 struct optc *tgn10 =
1102 kzalloc_obj(struct optc);
1103
1104 if (!tgn10)
1105 return NULL;
1106
1107 #undef REG_STRUCT
1108 #define REG_STRUCT optc_regs
1109 optc_regs_init(0),
1110 optc_regs_init(1),
1111 optc_regs_init(2),
1112 optc_regs_init(3);
1113
1114 tgn10->base.inst = instance;
1115 tgn10->base.ctx = ctx;
1116
1117 tgn10->tg_regs = &optc_regs[instance];
1118 tgn10->tg_shift = &optc_shift;
1119 tgn10->tg_mask = &optc_mask;
1120
1121 dcn35_timing_generator_init(tgn10);
1122
1123 return &tgn10->base;
1124 }
1125
1126 static const struct encoder_feature_support link_enc_feature = {
1127 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1128 .max_hdmi_pixel_clock = 600000,
1129 .hdmi_ycbcr420_supported = true,
1130 .dp_ycbcr420_supported = true,
1131 .fec_supported = true,
1132 .flags.bits.IS_HBR2_CAPABLE = true,
1133 .flags.bits.IS_HBR3_CAPABLE = true,
1134 .flags.bits.IS_TPS3_CAPABLE = true,
1135 .flags.bits.IS_TPS4_CAPABLE = true
1136 };
1137
dcn35_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1138 static struct link_encoder *dcn35_link_encoder_create(
1139 struct dc_context *ctx,
1140 const struct encoder_init_data *enc_init_data)
1141 {
1142 struct dcn20_link_encoder *enc20 =
1143 kzalloc_obj(struct dcn20_link_encoder);
1144
1145 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1146 return NULL;
1147
1148 #undef REG_STRUCT
1149 #define REG_STRUCT link_enc_aux_regs
1150 aux_regs_init(0),
1151 aux_regs_init(1),
1152 aux_regs_init(2),
1153 aux_regs_init(3),
1154 aux_regs_init(4);
1155
1156 #undef REG_STRUCT
1157 #define REG_STRUCT link_enc_hpd_regs
1158 hpd_regs_init(0),
1159 hpd_regs_init(1),
1160 hpd_regs_init(2),
1161 hpd_regs_init(3),
1162 hpd_regs_init(4);
1163
1164 #undef REG_STRUCT
1165 #define REG_STRUCT link_enc_regs
1166 link_regs_init(0, A),
1167 link_regs_init(1, B),
1168 link_regs_init(2, C),
1169 link_regs_init(3, D),
1170 link_regs_init(4, E);
1171
1172 dcn35_link_encoder_construct(enc20,
1173 enc_init_data,
1174 &link_enc_feature,
1175 &link_enc_regs[enc_init_data->transmitter],
1176 &link_enc_aux_regs[enc_init_data->channel - 1],
1177 &link_enc_hpd_regs[enc_init_data->hpd_source],
1178 &le_shift,
1179 &le_mask);
1180
1181 return &enc20->enc10.base;
1182 }
1183
1184 /* Create a minimal link encoder object not associated with a particular
1185 * physical connector.
1186 * resource_funcs.link_enc_create_minimal
1187 */
dcn31_link_enc_create_minimal(struct dc_context * ctx,enum engine_id eng_id)1188 static struct link_encoder *dcn31_link_enc_create_minimal(
1189 struct dc_context *ctx, enum engine_id eng_id)
1190 {
1191 struct dcn20_link_encoder *enc20;
1192
1193 if (((unsigned int)eng_id - ENGINE_ID_DIGA) >= ctx->dc->res_pool->res_cap->num_dig_link_enc)
1194 return NULL;
1195
1196 enc20 = kzalloc_obj(struct dcn20_link_encoder);
1197 if (!enc20)
1198 return NULL;
1199
1200 dcn31_link_encoder_construct_minimal(
1201 enc20,
1202 ctx,
1203 &link_enc_feature,
1204 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1205 &le_shift,
1206 &le_mask,
1207 eng_id);
1208
1209 return &enc20->enc10.base;
1210 }
1211
dcn31_panel_cntl_create(const struct panel_cntl_init_data * init_data)1212 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1213 {
1214 struct dcn31_panel_cntl *panel_cntl =
1215 kzalloc_obj(struct dcn31_panel_cntl);
1216
1217 if (!panel_cntl)
1218 return NULL;
1219
1220 dcn31_panel_cntl_construct(panel_cntl, init_data);
1221
1222 return &panel_cntl->base;
1223 }
1224
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1225 static void read_dce_straps(
1226 struct dc_context *ctx,
1227 struct resource_straps *straps)
1228 {
1229 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1230 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1231
1232 }
1233
dcn31_create_audio(struct dc_context * ctx,unsigned int inst)1234 static struct audio *dcn31_create_audio(
1235 struct dc_context *ctx, unsigned int inst)
1236 {
1237
1238 #undef REG_STRUCT
1239 #define REG_STRUCT audio_regs
1240 audio_regs_init(0),
1241 audio_regs_init(1),
1242 audio_regs_init(2),
1243 audio_regs_init(3),
1244 audio_regs_init(4);
1245 audio_regs_init(5);
1246 audio_regs_init(6);
1247
1248 return dce_audio_create(ctx, inst,
1249 &audio_regs[inst], &audio_shift, &audio_mask);
1250 }
1251
dcn31_vpg_create(struct dc_context * ctx,uint32_t inst)1252 static struct vpg *dcn31_vpg_create(
1253 struct dc_context *ctx,
1254 uint32_t inst)
1255 {
1256 struct dcn31_vpg *vpg31 = kzalloc_obj(struct dcn31_vpg);
1257
1258 if (!vpg31)
1259 return NULL;
1260
1261 #undef REG_STRUCT
1262 #define REG_STRUCT vpg_regs
1263 vpg_regs_init(0),
1264 vpg_regs_init(1),
1265 vpg_regs_init(2),
1266 vpg_regs_init(3),
1267 vpg_regs_init(4),
1268 vpg_regs_init(5),
1269 vpg_regs_init(6),
1270 vpg_regs_init(7),
1271 vpg_regs_init(8),
1272 vpg_regs_init(9);
1273
1274 vpg31_construct(vpg31, ctx, inst,
1275 &vpg_regs[inst],
1276 &vpg_shift,
1277 &vpg_mask);
1278
1279 return &vpg31->base;
1280 }
1281
dcn31_afmt_create(struct dc_context * ctx,uint32_t inst)1282 static struct afmt *dcn31_afmt_create(
1283 struct dc_context *ctx,
1284 uint32_t inst)
1285 {
1286 struct dcn31_afmt *afmt31 = kzalloc_obj(struct dcn31_afmt);
1287
1288 if (!afmt31)
1289 return NULL;
1290
1291 #undef REG_STRUCT
1292 #define REG_STRUCT afmt_regs
1293 afmt_regs_init(0),
1294 afmt_regs_init(1),
1295 afmt_regs_init(2),
1296 afmt_regs_init(3),
1297 afmt_regs_init(4),
1298 afmt_regs_init(5);
1299
1300 afmt31_construct(afmt31, ctx, inst,
1301 &afmt_regs[inst],
1302 &afmt_shift,
1303 &afmt_mask);
1304
1305 // Light sleep by default, no need to power down here
1306
1307 return &afmt31->base;
1308 }
1309
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1310 static struct apg *dcn31_apg_create(
1311 struct dc_context *ctx,
1312 uint32_t inst)
1313 {
1314 struct dcn31_apg *apg31 = kzalloc_obj(struct dcn31_apg);
1315
1316 if (!apg31)
1317 return NULL;
1318
1319 #undef REG_STRUCT
1320 #define REG_STRUCT apg_regs
1321 apg_regs_init(0),
1322 apg_regs_init(1),
1323 apg_regs_init(2),
1324 apg_regs_init(3);
1325
1326 apg31_construct(apg31, ctx, inst,
1327 &apg_regs[inst],
1328 &apg_shift,
1329 &apg_mask);
1330
1331 return &apg31->base;
1332 }
1333
dcn35_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1334 static struct stream_encoder *dcn35_stream_encoder_create(
1335 enum engine_id eng_id,
1336 struct dc_context *ctx)
1337 {
1338 struct dcn10_stream_encoder *enc1;
1339 struct vpg *vpg;
1340 struct afmt *afmt;
1341 int vpg_inst;
1342 int afmt_inst;
1343
1344 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1345 if (eng_id < 0 || eng_id >= ARRAY_SIZE(stream_enc_regs))
1346 return NULL;
1347
1348 vpg_inst = eng_id;
1349 afmt_inst = eng_id;
1350
1351 enc1 = kzalloc_obj(struct dcn10_stream_encoder);
1352 vpg = dcn31_vpg_create(ctx, vpg_inst);
1353 afmt = dcn31_afmt_create(ctx, afmt_inst);
1354
1355 if (!enc1 || !vpg || !afmt) {
1356 kfree(enc1);
1357 kfree(vpg);
1358 kfree(afmt);
1359 return NULL;
1360 }
1361
1362 #undef REG_STRUCT
1363 #define REG_STRUCT stream_enc_regs
1364 stream_enc_regs_init(0),
1365 stream_enc_regs_init(1),
1366 stream_enc_regs_init(2),
1367 stream_enc_regs_init(3),
1368 stream_enc_regs_init(4);
1369
1370 dcn35_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1371 eng_id, vpg, afmt,
1372 &stream_enc_regs[eng_id],
1373 &se_shift, &se_mask);
1374
1375 return &enc1->base;
1376 }
1377
dcn31_hpo_frl_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1378 static struct hpo_frl_stream_encoder *dcn31_hpo_frl_stream_encoder_create(
1379 enum engine_id eng_id,
1380 struct dc_context *ctx)
1381 {
1382 struct dcn30_hpo_frl_stream_encoder *hpo_enc3;
1383 struct vpg *vpg;
1384 struct afmt *afmt;
1385 int vpg_inst;
1386 int afmt_inst;
1387
1388 #undef REG_STRUCT
1389 #define REG_STRUCT hpo_frl_stream_enc_regs
1390 hpo_frl_stream_encoder_reg_list(0),
1391 hpo_frl_stream_encoder_dme_reg_list(6);
1392
1393 /* Mapping of VPG, AFMT, DME register blocks to HPO block instance */
1394 if (eng_id == ENGINE_ID_HPO_0) {
1395 vpg_inst = 5;
1396 afmt_inst = 5;
1397 } else
1398 return NULL;
1399
1400 /* allocate HPO stream encoder and create VPG, AFMT sub-blocks */
1401 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_stream_encoder);
1402 vpg = dcn31_vpg_create(ctx, vpg_inst);
1403 afmt = dcn31_afmt_create(ctx, afmt_inst);
1404
1405 if (!hpo_enc3 || !vpg || !afmt) {
1406 kfree(hpo_enc3);
1407 kfree(vpg);
1408 kfree(afmt);
1409 return NULL;
1410 }
1411
1412 dcn30_hpo_frl_stream_encoder_construct(hpo_enc3, ctx, ctx->dc_bios,
1413 eng_id, vpg, afmt,
1414 &hpo_frl_stream_enc_regs[eng_id-ENGINE_ID_HPO_0],
1415 &hpo_se_shift, &hpo_se_mask);
1416
1417 return &hpo_enc3->base;
1418 }
1419
dcn31_hpo_frl_link_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1420 static struct hpo_frl_link_encoder *dcn31_hpo_frl_link_encoder_create(
1421 enum engine_id eng_id,
1422 struct dc_context *ctx)
1423 {
1424 struct dcn30_hpo_frl_link_encoder *hpo_enc3;
1425
1426 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1));
1427
1428 #undef REG_STRUCT
1429 #define REG_STRUCT hpo_frl_link_enc_regs
1430 hpo_frl_link_encoder_reg_list(0);
1431
1432 /* allocate HPO link encoder */
1433 hpo_enc3 = kzalloc_obj(struct dcn30_hpo_frl_link_encoder);
1434 if (!hpo_enc3)
1435 return NULL; /* out of memory */
1436
1437 hpo_frl_link_encoder3_construct(hpo_enc3, ctx, eng_id-ENGINE_ID_HPO_0,
1438 &hpo_frl_link_enc_regs[eng_id-ENGINE_ID_HPO_0],
1439 &hpo_le_shift, &hpo_le_mask);
1440
1441 return &hpo_enc3->base;
1442 }
1443
dcn31_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1444 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1445 enum engine_id eng_id,
1446 struct dc_context *ctx)
1447 {
1448 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1449 struct vpg *vpg;
1450 struct apg *apg;
1451 uint32_t hpo_dp_inst;
1452 uint32_t vpg_inst;
1453 uint32_t apg_inst;
1454
1455 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1456 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1457
1458 /* Mapping of VPG register blocks to HPO DP block instance:
1459 * VPG[6] -> HPO_DP[0]
1460 * VPG[7] -> HPO_DP[1]
1461 * VPG[8] -> HPO_DP[2]
1462 * VPG[9] -> HPO_DP[3]
1463 */
1464 vpg_inst = hpo_dp_inst + 6;
1465
1466 /* Mapping of APG register blocks to HPO DP block instance:
1467 * APG[0] -> HPO_DP[0]
1468 * APG[1] -> HPO_DP[1]
1469 * APG[2] -> HPO_DP[2]
1470 * APG[3] -> HPO_DP[3]
1471 */
1472 apg_inst = hpo_dp_inst;
1473
1474 /* allocate HPO stream encoder and create VPG sub-block */
1475 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder);
1476 vpg = dcn31_vpg_create(ctx, vpg_inst);
1477 apg = dcn31_apg_create(ctx, apg_inst);
1478
1479 if (!hpo_dp_enc31 || !vpg || !apg) {
1480 kfree(hpo_dp_enc31);
1481 kfree(vpg);
1482 kfree(apg);
1483 return NULL;
1484 }
1485
1486 #undef REG_STRUCT
1487 #define REG_STRUCT hpo_dp_stream_enc_regs
1488 hpo_dp_stream_encoder_reg_init(0),
1489 hpo_dp_stream_encoder_reg_init(1),
1490 hpo_dp_stream_encoder_reg_init(2),
1491 hpo_dp_stream_encoder_reg_init(3);
1492
1493 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1494 hpo_dp_inst, eng_id, vpg, apg,
1495 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1496 &hpo_dp_se_shift, &hpo_dp_se_mask);
1497
1498 return &hpo_dp_enc31->base;
1499 }
1500
dcn31_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1501 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1502 uint8_t inst,
1503 struct dc_context *ctx)
1504 {
1505 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1506
1507 /* allocate HPO link encoder */
1508 hpo_dp_enc31 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder);
1509 if (!hpo_dp_enc31)
1510 return NULL; /* out of memory */
1511
1512 #undef REG_STRUCT
1513 #define REG_STRUCT hpo_dp_link_enc_regs
1514 hpo_dp_link_encoder_reg_init(0),
1515 hpo_dp_link_encoder_reg_init(1);
1516
1517 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1518 &hpo_dp_link_enc_regs[inst],
1519 &hpo_dp_le_shift, &hpo_dp_le_mask);
1520
1521 return &hpo_dp_enc31->base;
1522 }
1523
dcn35_hwseq_create(struct dc_context * ctx)1524 static struct dce_hwseq *dcn35_hwseq_create(
1525 struct dc_context *ctx)
1526 {
1527 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq);
1528
1529 #undef REG_STRUCT
1530 #define REG_STRUCT hwseq_reg
1531 hwseq_reg_init();
1532
1533 if (hws) {
1534 hws->ctx = ctx;
1535 hws->regs = &hwseq_reg;
1536 hws->shifts = &hwseq_shift;
1537 hws->masks = &hwseq_mask;
1538 }
1539 return hws;
1540 }
1541 static const struct resource_create_funcs res_create_funcs = {
1542 .read_dce_straps = read_dce_straps,
1543 .create_audio = dcn31_create_audio,
1544 .create_stream_encoder = dcn35_stream_encoder_create,
1545 .create_hpo_frl_stream_encoder = dcn31_hpo_frl_stream_encoder_create,
1546 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1547 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1548 .create_hwseq = dcn35_hwseq_create,
1549 };
1550
dcn35_resource_destruct(struct dcn35_resource_pool * pool)1551 static void dcn35_resource_destruct(struct dcn35_resource_pool *pool)
1552 {
1553 unsigned int i;
1554
1555 for (i = 0; i < pool->base.stream_enc_count; i++) {
1556 if (pool->base.stream_enc[i] != NULL) {
1557 if (pool->base.stream_enc[i]->vpg != NULL) {
1558 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1559 pool->base.stream_enc[i]->vpg = NULL;
1560 }
1561 if (pool->base.stream_enc[i]->afmt != NULL) {
1562 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1563 pool->base.stream_enc[i]->afmt = NULL;
1564 }
1565 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1566 pool->base.stream_enc[i] = NULL;
1567 }
1568 }
1569
1570 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) {
1571 if (pool->base.hpo_frl_stream_enc[i] != NULL) {
1572 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) {
1573 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg));
1574 pool->base.hpo_frl_stream_enc[i]->vpg = NULL;
1575 }
1576 if (pool->base.hpo_frl_stream_enc[i]->afmt != NULL) {
1577 kfree(DCN30_AFMT_FROM_AFMT(pool->base.hpo_frl_stream_enc[i]->afmt));
1578 pool->base.hpo_frl_stream_enc[i]->afmt = NULL;
1579 }
1580 kfree(DCN30_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i]));
1581 pool->base.hpo_frl_stream_enc[i] = NULL;
1582 }
1583 }
1584
1585 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1586 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1587 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1588 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1589 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1590 }
1591 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1592 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1593 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1594 }
1595 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1596 pool->base.hpo_dp_stream_enc[i] = NULL;
1597 }
1598 }
1599
1600 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1601 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1602 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1603 pool->base.hpo_dp_link_enc[i] = NULL;
1604 }
1605 }
1606
1607 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) {
1608 if (pool->base.dscs[i] != NULL)
1609 dcn20_dsc_destroy(&pool->base.dscs[i]);
1610 }
1611
1612 if (pool->base.mpc != NULL) {
1613 kfree(TO_DCN20_MPC(pool->base.mpc));
1614 pool->base.mpc = NULL;
1615 }
1616 if (pool->base.hubbub != NULL) {
1617 kfree(pool->base.hubbub);
1618 pool->base.hubbub = NULL;
1619 }
1620 for (i = 0; i < pool->base.pipe_count; i++) {
1621 if (pool->base.dpps[i] != NULL)
1622 dcn35_dpp_destroy(&pool->base.dpps[i]);
1623
1624 if (pool->base.ipps[i] != NULL)
1625 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1626
1627 if (pool->base.hubps[i] != NULL) {
1628 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1629 pool->base.hubps[i] = NULL;
1630 }
1631
1632 if (pool->base.irqs != NULL) {
1633 dal_irq_service_destroy(&pool->base.irqs);
1634 }
1635 }
1636
1637 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) {
1638 if (pool->base.engines[i] != NULL)
1639 dce110_engine_destroy(&pool->base.engines[i]);
1640 if (pool->base.hw_i2cs[i] != NULL) {
1641 kfree(pool->base.hw_i2cs[i]);
1642 pool->base.hw_i2cs[i] = NULL;
1643 }
1644 if (pool->base.sw_i2cs[i] != NULL) {
1645 kfree(pool->base.sw_i2cs[i]);
1646 pool->base.sw_i2cs[i] = NULL;
1647 }
1648 }
1649
1650 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) {
1651 if (pool->base.opps[i] != NULL)
1652 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1653 }
1654
1655 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1656 if (pool->base.timing_generators[i] != NULL) {
1657 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1658 pool->base.timing_generators[i] = NULL;
1659 }
1660 }
1661
1662 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dwb; i++) {
1663 if (pool->base.dwbc[i] != NULL) {
1664 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1665 pool->base.dwbc[i] = NULL;
1666 }
1667 if (pool->base.mcif_wb[i] != NULL) {
1668 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1669 pool->base.mcif_wb[i] = NULL;
1670 }
1671 }
1672
1673 for (i = 0; i < pool->base.audio_count; i++) {
1674 if (pool->base.audios[i])
1675 dce_aud_destroy(&pool->base.audios[i]);
1676 }
1677
1678 for (i = 0; i < pool->base.clk_src_count; i++) {
1679 if (pool->base.clock_sources[i] != NULL) {
1680 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1681 pool->base.clock_sources[i] = NULL;
1682 }
1683 }
1684
1685 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) {
1686 if (pool->base.mpc_lut[i] != NULL) {
1687 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1688 pool->base.mpc_lut[i] = NULL;
1689 }
1690 if (pool->base.mpc_shaper[i] != NULL) {
1691 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1692 pool->base.mpc_shaper[i] = NULL;
1693 }
1694 }
1695
1696 if (pool->base.dp_clock_source != NULL) {
1697 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1698 pool->base.dp_clock_source = NULL;
1699 }
1700
1701 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) {
1702 if (pool->base.multiple_abms[i] != NULL)
1703 dce_abm_destroy(&pool->base.multiple_abms[i]);
1704 }
1705
1706 if (pool->base.psr != NULL)
1707 dmub_psr_destroy(&pool->base.psr);
1708
1709 if (pool->base.replay != NULL)
1710 dmub_replay_destroy(&pool->base.replay);
1711
1712 if (pool->base.pg_cntl != NULL)
1713 dcn_pg_cntl_destroy(&pool->base.pg_cntl);
1714
1715 if (pool->base.dccg != NULL)
1716 dcn_dccg_destroy(&pool->base.dccg);
1717
1718 if (pool->base.dio != NULL) {
1719 kfree(TO_DCN10_DIO(pool->base.dio));
1720 pool->base.dio = NULL;
1721 }
1722 }
1723
dcn35_hubp_create(struct dc_context * ctx,uint32_t inst)1724 static struct hubp *dcn35_hubp_create(
1725 struct dc_context *ctx,
1726 uint32_t inst)
1727 {
1728 struct dcn20_hubp *hubp2 =
1729 kzalloc_obj(struct dcn20_hubp);
1730
1731 if (!hubp2)
1732 return NULL;
1733
1734 #undef REG_STRUCT
1735 #define REG_STRUCT hubp_regs
1736 hubp_regs_init(0),
1737 hubp_regs_init(1),
1738 hubp_regs_init(2),
1739 hubp_regs_init(3);
1740
1741 if (hubp35_construct(hubp2, ctx, inst,
1742 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1743 return &hubp2->base;
1744
1745 BREAK_TO_DEBUGGER();
1746 kfree(hubp2);
1747 return NULL;
1748 }
1749
dcn35_dwbc_init(struct dcn30_dwbc * dwbc30,struct dc_context * ctx)1750 static void dcn35_dwbc_init(struct dcn30_dwbc *dwbc30, struct dc_context *ctx)
1751 {
1752 dcn35_dwbc_set_fgcg(
1753 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1754 }
1755
dcn35_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1756 static bool dcn35_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1757 {
1758 unsigned int i;
1759 uint32_t pipe_count = pool->res_cap->num_dwb;
1760
1761 for (i = 0; i < pipe_count; i++) {
1762 struct dcn30_dwbc *dwbc30 = kzalloc_obj(struct dcn30_dwbc);
1763
1764 if (!dwbc30) {
1765 dm_error("DC: failed to create dwbc30!\n");
1766 return false;
1767 }
1768
1769 #undef REG_STRUCT
1770 #define REG_STRUCT dwbc35_regs
1771 dwbc_regs_dcn3_init(0);
1772
1773 dcn35_dwbc_construct(dwbc30, ctx,
1774 &dwbc35_regs[i],
1775 &dwbc35_shift,
1776 &dwbc35_mask,
1777 i);
1778
1779 pool->dwbc[i] = &dwbc30->base;
1780
1781 dcn35_dwbc_init(dwbc30, ctx);
1782 }
1783 return true;
1784 }
1785
dcn35_mmhubbub_init(struct dcn30_mmhubbub * mcif_wb30,struct dc_context * ctx)1786 static void dcn35_mmhubbub_init(struct dcn30_mmhubbub *mcif_wb30,
1787 struct dc_context *ctx)
1788 {
1789 dcn35_mmhubbub_set_fgcg(
1790 mcif_wb30,
1791 ctx->dc->debug.enable_fine_grain_clock_gating.bits.mmhubbub);
1792 }
1793
dcn35_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1794 static bool dcn35_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1795 {
1796 unsigned int i;
1797 uint32_t pipe_count = pool->res_cap->num_dwb;
1798
1799 for (i = 0; i < pipe_count; i++) {
1800 struct dcn30_mmhubbub *mcif_wb30 = kzalloc_obj(struct dcn30_mmhubbub);
1801
1802 if (!mcif_wb30) {
1803 dm_error("DC: failed to create mcif_wb30!\n");
1804 return false;
1805 }
1806
1807 #undef REG_STRUCT
1808 #define REG_STRUCT mcif_wb35_regs
1809 mcif_wb_regs_dcn3_init(0);
1810
1811 dcn35_mmhubbub_construct(mcif_wb30, ctx,
1812 &mcif_wb35_regs[i],
1813 &mcif_wb35_shift,
1814 &mcif_wb35_mask,
1815 i);
1816
1817 dcn35_mmhubbub_init(mcif_wb30, ctx);
1818
1819 pool->mcif_wb[i] = &mcif_wb30->base;
1820 }
1821 return true;
1822 }
1823
dcn35_dsc_create(struct dc_context * ctx,uint32_t inst)1824 static struct display_stream_compressor *dcn35_dsc_create(
1825 struct dc_context *ctx, uint32_t inst)
1826 {
1827 struct dcn20_dsc *dsc =
1828 kzalloc_obj(struct dcn20_dsc);
1829
1830 if (!dsc) {
1831 BREAK_TO_DEBUGGER();
1832 return NULL;
1833 }
1834
1835 #undef REG_STRUCT
1836 #define REG_STRUCT dsc_regs
1837 dsc_regsDCN35_init(0),
1838 dsc_regsDCN35_init(1),
1839 dsc_regsDCN35_init(2),
1840 dsc_regsDCN35_init(3);
1841
1842 dsc35_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1843 dsc35_set_fgcg(dsc,
1844 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1845 return &dsc->base;
1846 }
1847
dcn35_destroy_resource_pool(struct resource_pool ** pool)1848 static void dcn35_destroy_resource_pool(struct resource_pool **pool)
1849 {
1850 struct dcn35_resource_pool *dcn35_pool = TO_DCN35_RES_POOL(*pool);
1851
1852 dcn35_resource_destruct(dcn35_pool);
1853 kfree(dcn35_pool);
1854 *pool = NULL;
1855 }
1856
dcn35_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1857 static struct clock_source *dcn35_clock_source_create(
1858 struct dc_context *ctx,
1859 struct dc_bios *bios,
1860 enum clock_source_id id,
1861 const struct dce110_clk_src_regs *regs,
1862 bool dp_clk_src)
1863 {
1864 struct dce110_clk_src *clk_src =
1865 kzalloc_obj(struct dce110_clk_src);
1866
1867 if (!clk_src)
1868 return NULL;
1869
1870 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1871 regs, &cs_shift, &cs_mask)) {
1872 clk_src->base.dp_clk_src = dp_clk_src;
1873 return &clk_src->base;
1874 }
1875
1876 kfree(clk_src);
1877 BREAK_TO_DEBUGGER();
1878 return NULL;
1879 }
1880
1881 static struct dc_cap_funcs cap_funcs = {
1882 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1883 };
1884
dcn35_get_panel_config_defaults(struct dc_panel_config * panel_config)1885 static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config)
1886 {
1887 *panel_config = panel_config_defaults;
1888 }
1889
1890
dcn35_validate_bandwidth(struct dc * dc,struct dc_state * context,enum dc_validate_mode validate_mode)1891 static enum dc_status dcn35_validate_bandwidth(struct dc *dc,
1892 struct dc_state *context,
1893 enum dc_validate_mode validate_mode)
1894 {
1895 bool out = false;
1896
1897 DC_FP_START();
1898 out = dml2_validate(dc, context,
1899 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1900 validate_mode);
1901 DC_FP_END();
1902
1903 if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
1904 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1905
1906 DC_FP_START();
1907 dcn35_decide_zstate_support(dc, context);
1908 DC_FP_END();
1909
1910 return out ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1911 }
1912
dcn35_patch_unknown_plane_state(struct dc_plane_state * plane_state)1913 enum dc_status dcn35_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1914 {
1915 plane_state->tiling_info.gfxversion = DcGfxVersion9;
1916 dcn20_patch_unknown_plane_state(plane_state);
1917 return DC_OK;
1918 }
1919
1920
populate_dml_pipes_from_context_fpu(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,enum dc_validate_mode validate_mode)1921 static int populate_dml_pipes_from_context_fpu(struct dc *dc,
1922 struct dc_state *context,
1923 display_e2e_pipe_params_st *pipes,
1924 enum dc_validate_mode validate_mode)
1925 {
1926 int ret;
1927
1928 DC_FP_START();
1929 ret = dcn35_populate_dml_pipes_from_context_fpu(dc, context, pipes, validate_mode);
1930 DC_FP_END();
1931
1932 return ret;
1933 }
1934
dcn35_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1935 void dcn35_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1936 {
1937 DC_FP_START();
1938 dcn35_update_bw_bounding_box_fpu(dc, bw_params);
1939 DC_FP_END();
1940 }
1941 static struct resource_funcs dcn35_res_pool_funcs = {
1942 .destroy = dcn35_destroy_resource_pool,
1943 .link_enc_create = dcn35_link_encoder_create,
1944 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1945 .link_encs_assign = link_enc_cfg_link_encs_assign,
1946 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1947 .hpo_frl_link_enc_create = dcn31_hpo_frl_link_encoder_create,
1948 .panel_cntl_create = dcn31_panel_cntl_create,
1949 .validate_bandwidth = dcn35_validate_bandwidth,
1950 .calculate_wm_and_dlg = NULL,
1951 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1952 .populate_dml_pipes = populate_dml_pipes_from_context_fpu,
1953 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
1954 .release_pipe = dcn20_release_pipe,
1955 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1956 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1957 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1958 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1959 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1960 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1961 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1962 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1963 .update_bw_bounding_box = dcn35_update_bw_bounding_box,
1964 .patch_unknown_plane_state = dcn35_patch_unknown_plane_state,
1965 .get_panel_config_defaults = dcn35_get_panel_config_defaults,
1966 .get_preferred_eng_id_dpia = dcn35_get_preferred_eng_id_dpia,
1967 .get_det_buffer_size = dcn31_get_det_buffer_size,
1968 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
1969 .update_dc_state_for_encoder_switch = dcn31_update_dc_state_for_encoder_switch,
1970 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
1971 .get_default_tiling_info = dcn10_get_default_tiling_info
1972 };
1973
dcn35_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn35_resource_pool * pool)1974 static bool dcn35_resource_construct(
1975 uint8_t num_virtual_links,
1976 struct dc *dc,
1977 struct dcn35_resource_pool *pool)
1978 {
1979 int i;
1980 struct dc_context *ctx = dc->ctx;
1981 struct irq_service_init_data init_data;
1982
1983 #undef REG_STRUCT
1984 #define REG_STRUCT bios_regs
1985 bios_regs_init();
1986
1987 #undef REG_STRUCT
1988 #define REG_STRUCT clk_src_regs
1989 clk_src_regs_init(0, A),
1990 clk_src_regs_init(1, B),
1991 clk_src_regs_init(2, C),
1992 clk_src_regs_init(3, D),
1993 clk_src_regs_init(4, E);
1994
1995 /* Enable 4to1MPC by default */
1996 dc->config.allow_4to1MPC = true;
1997
1998 #undef REG_STRUCT
1999 #define REG_STRUCT abm_regs
2000 abm_regs_init(0),
2001 abm_regs_init(1),
2002 abm_regs_init(2),
2003 abm_regs_init(3);
2004
2005 #undef REG_STRUCT
2006 #define REG_STRUCT dccg_regs
2007 dccg_regs_init();
2008
2009 ctx->dc_bios->regs = &bios_regs;
2010
2011 pool->base.res_cap = &res_cap_dcn35;
2012
2013 pool->base.funcs = &dcn35_res_pool_funcs;
2014
2015 /*************************************************
2016 * Resource + asic cap harcoding *
2017 *************************************************/
2018 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE;
2019 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2020 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2021 dc->caps.max_downscale_ratio = 600;
2022 dc->caps.i2c_speed_in_khz = 100;
2023 dc->caps.i2c_speed_in_khz_hdcp = 100;
2024 dc->caps.max_cursor_size = 256;
2025 dc->caps.min_horizontal_blanking_period = 80;
2026 dc->caps.dmdata_alloc_size = 2048;
2027 dc->caps.max_slave_planes = 3;
2028 dc->caps.max_slave_yuv_planes = 3;
2029 dc->caps.max_slave_rgb_planes = 3;
2030 dc->caps.post_blend_color_processing = true;
2031 dc->caps.force_dp_tps4_for_cp2520 = true;
2032 if (dc->config.forceHBR2CP2520)
2033 dc->caps.force_dp_tps4_for_cp2520 = false;
2034 dc->caps.hdmi_hpo = true;
2035 dc->caps.dp_hpo = true;
2036 dc->caps.dp_hdmi21_pcon_support = true;
2037
2038 dc->caps.edp_dsc_support = true;
2039 dc->caps.extended_aux_timeout_support = true;
2040 dc->caps.dmcub_support = true;
2041 dc->caps.is_apu = true;
2042 dc->caps.seamless_odm = true;
2043
2044 dc->caps.zstate_support = true;
2045 dc->caps.ips_support = true;
2046 dc->caps.max_v_total = (1 << 15) - 1;
2047 dc->caps.vtotal_limited_by_fp2 = true;
2048
2049 /* Color pipeline capabilities */
2050 dc->caps.color.dpp.dcn_arch = 1;
2051 dc->caps.color.dpp.input_lut_shared = 0;
2052 dc->caps.color.dpp.icsc = 1;
2053 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2054 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2055 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2056 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2057 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2058 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2059 dc->caps.color.dpp.post_csc = 1;
2060 dc->caps.color.dpp.gamma_corr = 1;
2061 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2062 dc->caps.color.dpp.upsp_pre_scaler = 0;
2063
2064 dc->caps.color.dpp.hw_3d_lut = 0;
2065 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
2066 // no OGAM ROM on DCN301
2067 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2068 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2069 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2070 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2071 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2072 dc->caps.color.dpp.ocsc = 0;
2073
2074 dc->caps.color.mpc.gamut_remap = 1;
2075 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
2076 dc->caps.color.mpc.ogam_ram = 1;
2077 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2078 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2079 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2080 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2081 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2082 dc->caps.color.mpc.ocsc = 1;
2083 dc->caps.color.mpc.preblend = true;
2084 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER);
2085
2086 dc->caps.num_of_host_routers = 2;
2087 dc->caps.num_of_dpias_per_host_router = 2;
2088
2089 /* max_disp_clock_khz_at_vmin is slightly lower than the STA value in order
2090 * to provide some margin.
2091 * It's expected for furture ASIC to have equal or higher value, in order to
2092 * have determinstic power improvement from generate to genration.
2093 * (i.e., we should not expect new ASIC generation with lower vmin rate)
2094 */
2095 dc->caps.max_disp_clock_khz_at_vmin = 650000;
2096
2097 /* Sequential ONO is based on ASIC. */
2098 if (dc->ctx->asic_id.hw_internal_rev >= 0x40)
2099 dc->caps.sequential_ono = true;
2100
2101 /* Use pipe context based otg sync logic */
2102 dc->config.use_pipe_ctx_sync_logic = true;
2103
2104
2105 dc->config.disable_hbr_audio_dp2 = true;
2106 /* read VBIOS LTTPR caps */
2107 {
2108 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2109 enum bp_result bp_query_result;
2110 uint8_t is_vbios_lttpr_enable = 0;
2111
2112 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2113 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2114 }
2115
2116 /* interop bit is implicit */
2117 {
2118 dc->caps.vbios_lttpr_aware = true;
2119 }
2120 }
2121 dc->check_config = config_defaults;
2122
2123 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2124 dc->debug = debug_defaults_drv;
2125 /*HW default is to have all the FGCG enabled, SW no need to program them*/
2126 dc->debug.enable_fine_grain_clock_gating.u32All = 0xFFFF;
2127 // Init the vm_helper
2128 if (dc->vm_helper)
2129 vm_helper_init(dc->vm_helper, 16);
2130
2131 /*************************************************
2132 * Create resources *
2133 *************************************************/
2134
2135 /* Clock Sources for Pixel Clock*/
2136 pool->base.clock_sources[DCN35_CLK_SRC_PLL0] =
2137 dcn35_clock_source_create(ctx, ctx->dc_bios,
2138 CLOCK_SOURCE_COMBO_PHY_PLL0,
2139 &clk_src_regs[0], false);
2140 pool->base.clock_sources[DCN35_CLK_SRC_PLL1] =
2141 dcn35_clock_source_create(ctx, ctx->dc_bios,
2142 CLOCK_SOURCE_COMBO_PHY_PLL1,
2143 &clk_src_regs[1], false);
2144 pool->base.clock_sources[DCN35_CLK_SRC_PLL2] =
2145 dcn35_clock_source_create(ctx, ctx->dc_bios,
2146 CLOCK_SOURCE_COMBO_PHY_PLL2,
2147 &clk_src_regs[2], false);
2148 pool->base.clock_sources[DCN35_CLK_SRC_PLL3] =
2149 dcn35_clock_source_create(ctx, ctx->dc_bios,
2150 CLOCK_SOURCE_COMBO_PHY_PLL3,
2151 &clk_src_regs[3], false);
2152 pool->base.clock_sources[DCN35_CLK_SRC_PLL4] =
2153 dcn35_clock_source_create(ctx, ctx->dc_bios,
2154 CLOCK_SOURCE_COMBO_PHY_PLL4,
2155 &clk_src_regs[4], false);
2156
2157 pool->base.clk_src_count = DCN35_CLK_SRC_TOTAL;
2158
2159 /* todo: not reuse phy_pll registers */
2160 pool->base.dp_clock_source =
2161 dcn35_clock_source_create(ctx, ctx->dc_bios,
2162 CLOCK_SOURCE_ID_DP_DTO,
2163 &clk_src_regs[0], true);
2164
2165 for (i = 0; i < (int)pool->base.clk_src_count; i++) {
2166 if (pool->base.clock_sources[i] == NULL) {
2167 dm_error("DC: failed to create clock sources!\n");
2168 BREAK_TO_DEBUGGER();
2169 goto create_fail;
2170 }
2171 }
2172 /*temp till dml2 fully work without dml1*/
2173 dml_init_instance(&dc->dml, &dcn3_5_soc, &dcn3_5_ip, DML_PROJECT_DCN31);
2174
2175 /* TODO: DCCG */
2176 pool->base.dccg = dccg35_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2177 if (pool->base.dccg == NULL) {
2178 dm_error("DC: failed to create dccg!\n");
2179 BREAK_TO_DEBUGGER();
2180 goto create_fail;
2181 }
2182
2183 #undef REG_STRUCT
2184 #define REG_STRUCT pg_cntl_regs
2185 pg_cntl_dcn35_regs_init();
2186
2187 pool->base.pg_cntl = pg_cntl35_create(ctx, &pg_cntl_regs, &pg_cntl_shift, &pg_cntl_mask);
2188 if (pool->base.pg_cntl == NULL) {
2189 dm_error("DC: failed to create power gate control!\n");
2190 BREAK_TO_DEBUGGER();
2191 goto create_fail;
2192 }
2193
2194 /* TODO: IRQ */
2195 init_data.ctx = dc->ctx;
2196 pool->base.irqs = dal_irq_service_dcn35_create(&init_data);
2197 if (!pool->base.irqs)
2198 goto create_fail;
2199
2200 /* HUBBUB */
2201 pool->base.hubbub = dcn35_hubbub_create(ctx);
2202 if (pool->base.hubbub == NULL) {
2203 BREAK_TO_DEBUGGER();
2204 dm_error("DC: failed to create hubbub!\n");
2205 goto create_fail;
2206 }
2207
2208 /* DIO */
2209 pool->base.dio = dcn35_dio_create(ctx);
2210 if (pool->base.dio == NULL) {
2211 BREAK_TO_DEBUGGER();
2212 dm_error("DC: failed to create dio!\n");
2213 goto create_fail;
2214 }
2215
2216 /* HUBPs, DPPs, OPPs and TGs */
2217 for (i = 0; i < (int)pool->base.pipe_count; i++) {
2218 pool->base.hubps[i] = dcn35_hubp_create(ctx, i);
2219 if (pool->base.hubps[i] == NULL) {
2220 BREAK_TO_DEBUGGER();
2221 dm_error(
2222 "DC: failed to create hubps!\n");
2223 goto create_fail;
2224 }
2225
2226 pool->base.dpps[i] = dcn35_dpp_create(ctx, i);
2227 if (pool->base.dpps[i] == NULL) {
2228 BREAK_TO_DEBUGGER();
2229 dm_error(
2230 "DC: failed to create dpps!\n");
2231 goto create_fail;
2232 }
2233 }
2234
2235 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2236 pool->base.opps[i] = dcn35_opp_create(ctx, i);
2237 if (pool->base.opps[i] == NULL) {
2238 BREAK_TO_DEBUGGER();
2239 dm_error(
2240 "DC: failed to create output pixel processor!\n");
2241 goto create_fail;
2242 }
2243 }
2244
2245 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2246 pool->base.timing_generators[i] = dcn35_timing_generator_create(
2247 ctx, i);
2248 if (pool->base.timing_generators[i] == NULL) {
2249 BREAK_TO_DEBUGGER();
2250 dm_error("DC: failed to create tg!\n");
2251 goto create_fail;
2252 }
2253 }
2254 pool->base.timing_generator_count = i;
2255
2256 /* PSR */
2257 pool->base.psr = dmub_psr_create(ctx);
2258 if (pool->base.psr == NULL) {
2259 dm_error("DC: failed to create psr obj!\n");
2260 BREAK_TO_DEBUGGER();
2261 goto create_fail;
2262 }
2263
2264 /* Replay */
2265 pool->base.replay = dmub_replay_create(ctx);
2266 if (pool->base.replay == NULL) {
2267 dm_error("DC: failed to create replay obj!\n");
2268 BREAK_TO_DEBUGGER();
2269 goto create_fail;
2270 }
2271
2272 /* ABM */
2273 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2274 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2275 &abm_regs[i],
2276 &abm_shift,
2277 &abm_mask);
2278 if (pool->base.multiple_abms[i] == NULL) {
2279 dm_error("DC: failed to create abm for pipe %d!\n", i);
2280 BREAK_TO_DEBUGGER();
2281 goto create_fail;
2282 }
2283 }
2284
2285 /* MPC and DSC */
2286 pool->base.mpc = dcn35_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2287 if (pool->base.mpc == NULL) {
2288 BREAK_TO_DEBUGGER();
2289 dm_error("DC: failed to create mpc!\n");
2290 goto create_fail;
2291 }
2292
2293 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2294 pool->base.dscs[i] = dcn35_dsc_create(ctx, i);
2295 if (pool->base.dscs[i] == NULL) {
2296 BREAK_TO_DEBUGGER();
2297 dm_error("DC: failed to create display stream compressor %d!\n", i);
2298 goto create_fail;
2299 }
2300 }
2301
2302 /* DWB and MMHUBBUB */
2303 if (!dcn35_dwbc_create(ctx, &pool->base)) {
2304 BREAK_TO_DEBUGGER();
2305 dm_error("DC: failed to create dwbc!\n");
2306 goto create_fail;
2307 }
2308
2309 if (!dcn35_mmhubbub_create(ctx, &pool->base)) {
2310 BREAK_TO_DEBUGGER();
2311 dm_error("DC: failed to create mcif_wb!\n");
2312 goto create_fail;
2313 }
2314
2315 /* AUX and I2C */
2316 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2317 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2318 if (pool->base.engines[i] == NULL) {
2319 BREAK_TO_DEBUGGER();
2320 dm_error(
2321 "DC:failed to create aux engine!!\n");
2322 goto create_fail;
2323 }
2324 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2325 if (pool->base.hw_i2cs[i] == NULL) {
2326 BREAK_TO_DEBUGGER();
2327 dm_error(
2328 "DC:failed to create hw i2c!!\n");
2329 goto create_fail;
2330 }
2331 pool->base.sw_i2cs[i] = NULL;
2332 }
2333
2334 /* DCN3.5 has 6 DPIA */
2335 pool->base.usb4_dpia_count = 4;
2336 if (dc->debug.dpia_debug.bits.disable_dpia)
2337 pool->base.usb4_dpia_count = 0;
2338
2339 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2340 if (!resource_construct(num_virtual_links, dc, &pool->base,
2341 &res_create_funcs))
2342 goto create_fail;
2343
2344 /* HW Sequencer and Plane caps */
2345 dcn35_hw_sequencer_construct(dc);
2346
2347 dc->caps.max_planes = pool->base.pipe_count;
2348
2349 for (i = 0; i < (int)dc->caps.max_planes; ++i)
2350 dc->caps.planes[i] = plane_cap;
2351
2352 dc->caps.max_odm_combine_factor = 4;
2353
2354 dc->cap_funcs = cap_funcs;
2355
2356 dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
2357
2358 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2359 dc->dml2_options.use_native_soc_bb_construction = true;
2360 dc->dml2_options.minimize_dispclk_using_odm = false;
2361 if (dc->config.EnableMinDispClkODM)
2362 dc->dml2_options.minimize_dispclk_using_odm = true;
2363 dc->dml2_options.enable_windowed_mpo_odm = dc->config.enable_windowed_mpo_odm;
2364
2365 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2366 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2367
2368 dc->dml2_options.max_segments_per_hubp = 24;
2369 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/
2370 dc->dml2_options.override_det_buffer_size_kbytes = true;
2371
2372 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2373 dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/
2374
2375 return true;
2376
2377 create_fail:
2378
2379 dcn35_resource_destruct(pool);
2380
2381 return false;
2382 }
2383
dcn35_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2384 struct resource_pool *dcn35_create_resource_pool(
2385 const struct dc_init_data *init_data,
2386 struct dc *dc)
2387 {
2388 struct dcn35_resource_pool *pool =
2389 kzalloc_obj(struct dcn35_resource_pool);
2390
2391 if (!pool)
2392 return NULL;
2393
2394 if (dcn35_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
2395 return &pool->base;
2396
2397 BREAK_TO_DEBUGGER();
2398 kfree(pool);
2399 return NULL;
2400 }
2401